void kgdb_params_early_init(void) { mtspr(SPRN_M_TWB, virt_to_phys(tmp_sw_page)); #ifdef CONFIG_PPC_8xx __initial_memory_limit = 0x800000; #endif get_from_flat_dt("cpu", "clock-frequency", &ppc_proc_freq); get_from_flat_dt("soc", "reg", &immrbase); get_from_flat_dt("cpm", "brg-frequency", &brgfreq); #ifdef CONFIG_PPC_EP88XC cpm_reset(); init_ioports(); #ifdef CONFIG_KGDB_CPM_UART_SMC1 cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX); #endif #ifdef CONFIG_KGDB_CPM_UART_SCC2 cpm1_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX); cpm1_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX); #endif #else /* early dpmem init */ m8xx_cpm_dpinit(); #endif }
static void __init init_ioports(void) { int i; for (i = 0; i < ARRAY_SIZE(ep88xc_pins); i++) { struct cpm_pin *pin = &ep88xc_pins[i]; cpm1_set_pin(pin->port, pin->pin, pin->flags); } cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX); cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_TX); /* USB */ cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_RX); cpm1_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX); cpm1_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX); }
static void __init init_ioports(void) { int i; for (i = 0; i < ARRAY_SIZE(mpc866ads_pins); i++) { struct cpm_pin *pin = &mpc866ads_pins[i]; cpm1_set_pin(pin->port, pin->pin, pin->flags); } cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX); cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX); cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK1, CPM_CLK_TX); cpm1_clk_setup(CPM_CLK_SCC1, CPM_CLK2, CPM_CLK_RX); /* Set FEC1 and FEC2 to MII mode */ clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180); }
static void __init init_ioports(void) { struct device_node *dnode; struct property *prop; int len; init_pins(ARRAY_SIZE(tqm8xx_pins), &tqm8xx_pins[0]); cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX); dnode = of_find_node_by_name(NULL, "aliases"); if (dnode == NULL) return; prop = of_find_property(dnode, "ethernet1", &len); if (prop == NULL) return; /* init FEC pins */ init_pins(ARRAY_SIZE(tqm8xx_fec_pins), &tqm8xx_fec_pins[0]); }