void kgdb_params_early_init(void)
{
mtspr(SPRN_M_TWB, virt_to_phys(tmp_sw_page));
#ifdef CONFIG_PPC_8xx
__initial_memory_limit = 0x800000;
#endif
get_from_flat_dt("cpu", "clock-frequency", &ppc_proc_freq);
get_from_flat_dt("soc", "reg", &immrbase);
get_from_flat_dt("cpm", "brg-frequency", &brgfreq);
#ifdef CONFIG_PPC_EP88XC
cpm_reset();
init_ioports();
#ifdef CONFIG_KGDB_CPM_UART_SMC1
cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
#endif
#ifdef CONFIG_KGDB_CPM_UART_SCC2
cpm1_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
cpm1_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
#endif
#else
/* early dpmem init */
m8xx_cpm_dpinit();
#endif
}
static void __init mpc86xads_setup_arch(void)
{
struct device_node *np;
u32 __iomem *bcsr_io;
cpm_reset();
init_ioports();
np = of_find_compatible_node(NULL, NULL, "fsl,mpc866ads-bcsr");
if (!np) {
printk(KERN_CRIT "Could not find fsl,mpc866ads-bcsr node\n");
return;
}
bcsr_io = of_iomap(np, 0);
of_node_put(np);
if (bcsr_io == NULL) {
printk(KERN_CRIT "Could not remap BCSR\n");
return;
}
clrbits32(bcsr_io, BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN);
iounmap(bcsr_io);
}
static void __init ep88xc_setup_arch(void)
{
struct device_node *np;
cpm_reset();
init_ioports();
np = of_find_compatible_node(NULL, NULL, "fsl,ep88xc-bcsr");
if (!np) {
printk(KERN_CRIT "Could not find fsl,ep88xc-bcsr node\n");
return;
}
ep88xc_bcsr = of_iomap(np, 0);
of_node_put(np);
if (!ep88xc_bcsr) {
printk(KERN_CRIT "Could not remap BCSR\n");
return;
}
setbits8(&ep88xc_bcsr[7], BCSR7_SCC2_ENABLE);
setbits8(&ep88xc_bcsr[8], BCSR8_PHY1_ENABLE | BCSR8_PHY1_POWER |
BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER);
}
int __init setup_init(void)
{
cpm_reset();
/* Set bus priority here */
*(volatile unsigned int *)0xb34f0240 = 0x00010003;
*(volatile unsigned int *)0xb34f0244 = 0x00010003;
return 0;
}
int __init setup_init(void)
{
cpm_reset();
// CPU on AHB0 & AHB2
/* If CPU0_PRIO=3, may cause CIM overflow and IPU underrun. so set CPU0_PRIO=0, 2013-02-01 */
/* If CPU0_PRIO=0, may cause touch panel "i2c i2c-1: --I2C irq read timeout", so rollback CPU0_PRIO=3. 2013-02-04 */
setup_priority(HARB0_IOBASE, 6, 3);
setup_priority(HARB2_IOBASE, 10, 3);
return 0;
}
int __init setup_init(void)
{
cpm_reset();
#ifdef CONFIG_RESET_KEEP_POWER
reset_keep_power();
#endif
// CPU on AHB0 & AHB2
setup_priority(HARB0_IOBASE, 6, 3);
setup_priority(HARB2_IOBASE, 10, 3);
return 0;
}
int __init setup_init(void)
{
cpm_reset();
/* #ifdef CONFIG_RESET_KEEP_POWER */
/* reset_keep_power(); */
/* #endif */
/* // CPU on AHB0 & AHB2 */
/* setup_priority(HARB0_IOBASE, 6, 3); */
/* setup_priority(HARB2_IOBASE, 10, 3); */
return 0;
}
static void __init mpc885ads_setup_arch(void)
{
struct device_node *cpu;
cpu = of_find_node_by_type(NULL, "cpu");
if (cpu != 0) {
const unsigned int *fp;
fp = of_get_property(cpu, "clock-frequency", NULL);
if (fp != 0)
loops_per_jiffy = *fp / HZ;
else
loops_per_jiffy = 50000000 / HZ;
of_node_put(cpu);
}
cpm_reset();
mpc885ads_board_setup();
ROOT_DEV = Root_NFS;
}
static void __init adder875_setup(void)
{
cpm_reset();
init_ioports();
}
static void __init tqm8xx_setup_arch(void)
{
cpm_reset();
init_ioports();
}
int __init setup_init(void)
{
cpm_reset();
g_is_use_rtc = reset_keep_power();
return 0;
}
static void __init mpc885ads_setup_arch(void)
{
struct device_node *np;
cpm_reset();
init_ioports();
np = of_find_compatible_node(NULL, NULL, "fsl,mpc885ads-bcsr");
if (!np) {
printk(KERN_CRIT "Could not find fsl,mpc885ads-bcsr node\n");
return;
}
bcsr = of_iomap(np, 0);
bcsr5 = of_iomap(np, 1);
of_node_put(np);
if (!bcsr || !bcsr5) {
printk(KERN_CRIT "Could not remap BCSR\n");
return;
}
clrbits32(&bcsr[1], BCSR1_RS232EN_1);
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
setbits32(&bcsr[1], BCSR1_RS232EN_2);
#else
clrbits32(&bcsr[1], BCSR1_RS232EN_2);
#endif
clrbits32(bcsr5, BCSR5_MII1_EN);
setbits32(bcsr5, BCSR5_MII1_RST);
udelay(1000);
clrbits32(bcsr5, BCSR5_MII1_RST);
#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
clrbits32(bcsr5, BCSR5_MII2_EN);
setbits32(bcsr5, BCSR5_MII2_RST);
udelay(1000);
clrbits32(bcsr5, BCSR5_MII2_RST);
#else
setbits32(bcsr5, BCSR5_MII2_EN);
#endif
#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
clrbits32(&bcsr[4], BCSR4_ETH10_RST);
udelay(1000);
setbits32(&bcsr[4], BCSR4_ETH10_RST);
setbits32(&bcsr[1], BCSR1_ETHEN);
np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
#else
np = of_find_node_by_path("/soc@ff000000/cpm@9c0/ethernet@a40");
#endif
/* The SCC3 enet registers overlap the SMC1 registers, so
* one of the two must be removed from the device tree.
*/
if (np) {
of_detach_node(np);
of_node_put(np);
}
}
