void nxp_cpu_arch_init(void) { cpu_base_init(); cpu_bus_init(); #ifdef CONFIG_SMP /* * CCI400 BUS */ #define CCI_REG __PB_IO_MAP_CCI4_VIRT // 0xe0090000 writel(0x8, (CCI_REG + 0x0000)); // CCI writel(0x0, (CCI_REG + 0x1000)); // S0 : coresight writel(0x0, (CCI_REG + 0x2000)); // S1 : bottom bus writel(0x0, (CCI_REG + 0x3000)); // S2 : top bus writel((0x3<<30) | 0x3, (CCI_REG + 0x4000)); // S3: cpu cluster 1 writel((0x3<<30) | 0x3, (CCI_REG + 0x5000)); // S4: cpu cluster 0 #endif #if (CFG_BUS_RECONFIG_ENB == 1) // nxp_set_bus_config(); #endif /* Check version */ if (-1 != cpu_version) return; cpu_version = 1; }
void nxp_cpu_init(void) { cpu_base_init(); cpu_bus_init(); #if (CFG_BUS_RECONFIG_ENB == 1) nxp_set_bus_config(); #endif }
void nxp_cpu_base_init(void) { unsigned int rev = 0; unsigned int string[12] = { 0, }; #ifdef CONFIG_SMP unsigned int scu_ctrl = 0x0009; #endif cpu_base_init(); cpu_bus_init(); #ifdef CONFIG_SMP writel(0x0000, __PB_IO_MAP_REGS_VIRT + 0x11080); // ACP Bus Disable #if defined (CONFIG_CPU_S5P4418_EX_PERI_BUS) writel(0xC0000000, __PB_IO_MAP_MPPR_VIRT + 0x40); // SCU Address Filtering writel(0xCFF00000, __PB_IO_MAP_MPPR_VIRT + 0x44); scu_ctrl |= (1<<1); // SCU Address Filtering Enable #endif writel(0xffff, __PB_IO_MAP_MPPR_VIRT + 0x0c); // SCU writel(scu_ctrl, __PB_IO_MAP_MPPR_VIRT + 0x00); // SCU L2 Spec... Enable. #endif #if (CFG_BUS_RECONFIG_ENB == 1) nxp_set_bus_config(); #endif /* Check version */ if (-1 != cpu_version) return; nxp_cpu_id_string(string); rev = __raw_readl(__PB_IO_MAP_IROM_VIRT + 0x0100); switch(rev) { case 0xe153000a: cpu_version = 1; break; default: cpu_version = 0; break; } if (0xE4418000 == string[0]) cpu_version = 2; printk(KERN_INFO "CPU : VERSION = %u (0x%X)", cpu_version, rev); #if defined (CONFIG_CPU_S5P4418_EX_PERI_BUS) printk(", Assign Peripheral Exclusive Bus"); #endif printk("\n"); }
/* * CPU initialize */ void nxp_cpu_init(void) { cpu_base_init(); cpu_bus_init(); }