static void cpu_set_irq(void *opaque, int irq, int level) { CPUState *env = (CPUState *)opaque; if (level) { DPRINTF("Raise CPU IRQ %d\n", irq); env->halted = 0; env->pil_in |= 1 << irq; cpu_check_irqs(env); } else { DPRINTF("Lower CPU IRQ %d\n", irq); env->pil_in &= ~(1 << irq); cpu_check_irqs(env); } }
void cpu_put_psr(CPUSPARCState *env, target_ulong val) { cpu_put_psr_raw(env, val); #if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY)) cpu_check_irqs(env); #endif }
static void cpu_kick_irq(SPARCCPU *cpu) { CPUSPARCState *env = &cpu->env; env->halted = 0; cpu_check_irqs(env); qemu_cpu_kick(CPU(cpu)); }
static void cpu_kick_irq(SPARCCPU *cpu) { CPUSPARCState *env = &cpu->env; CPUState *cs = CPU(cpu); cs->halted = 0; cpu_check_irqs(env); qemu_cpu_kick(cs); }
static bool do_modify_softint(CPUSPARCState *env, uint32_t value) { if (env->softint != value) { env->softint = value; #if !defined(CONFIG_USER_ONLY) if (cpu_interrupts_enabled(env)) { cpu_check_irqs(env); } #endif return true; } return false; }
static void cpu_set_irq(void *opaque, int irq, int level) { SPARCCPU *cpu = opaque; CPUSPARCState *env = &cpu->env; if (level) { trace_sun4m_cpu_set_irq_raise(irq); env->pil_in |= 1 << irq; cpu_kick_irq(cpu); } else { trace_sun4m_cpu_set_irq_lower(irq); env->pil_in &= ~(1 << irq); cpu_check_irqs(env); } }
static void put_psr(target_ulong val) { env->psr = val & PSR_ICC; #if !defined(TARGET_SPARC64) env->psref = (val & PSR_EF) ? 1 : 0; env->psrpil = (val & PSR_PIL) >> 8; #endif #if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY)) cpu_check_irqs(env); #endif #if !defined(TARGET_SPARC64) env->psrs = (val & PSR_S) ? 1 : 0; env->psrps = (val & PSR_PS) ? 1 : 0; env->psret = (val & PSR_ET) ? 1 : 0; set_cwp(val & PSR_CWP); #endif env->cc_op = CC_OP_FLAGS; }
static void cpu_kick_irq(CPUSPARCState *env) { env->halted = 0; cpu_check_irqs(env); qemu_cpu_kick(env); }
static void cpu_kick_irq(CPUState *env) { env->halted = 0; cpu_check_irqs(env); }