static int
iodi_setup_intr(device_t dev, device_t child,
struct resource *ires, int flags, driver_filter_t *filt,
driver_intr_t *intr, void *arg, void **cookiep)
{
const char *name = device_get_name(child);
if (strcmp(name, "uart") == 0) {
/* FIXME uart 1? */
cpu_establish_hardintr("uart", filt, intr, arg,
PIC_UART_0_IRQ, flags, cookiep);
pic_setup_intr(PIC_IRT_UART_0_INDEX, PIC_UART_0_IRQ, 0x1, 1);
} else if (strcmp(name, "rge") == 0 || strcmp(name, "nlge") == 0) {
int irq;
/* This is a hack to pass in the irq */
irq = (intptr_t)ires->__r_i;
cpu_establish_hardintr("rge", filt, intr, arg, irq, flags,
cookiep);
pic_setup_intr(irq - PIC_IRQ_BASE, irq, 0x1, 1);
} else if (strcmp(name, "ehci") == 0) {
cpu_establish_hardintr("ehci", filt, intr, arg, PIC_USB_IRQ, flags,
cookiep);
pic_setup_intr(PIC_USB_IRQ - PIC_IRQ_BASE, PIC_USB_IRQ, 0x1, 1);
} else if (strcmp(name, "ata") == 0) {
xlr_establish_intr("ata", filt, intr, arg, PIC_PCMCIA_IRQ, flags,
cookiep, bridge_pcmcia_ack);
pic_setup_intr(PIC_PCMCIA_IRQ - PIC_IRQ_BASE, PIC_PCMCIA_IRQ, 0x1, 1);
}
return (0);
}
static int
iodi_setup_intr(device_t dev, device_t child,
struct resource *ires, int flags, driver_filter_t * filt, driver_intr_t * intr, void *arg,
void **cookiep)
{
int level;
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
xlr_reg_t reg;
/* FIXME is this the right place to fiddle with PIC? */
if (strcmp(device_get_name(child), "uart") == 0) {
/* FIXME uart 1? */
if (rmi_spin_mutex_safe)
mtx_lock_spin(&xlr_pic_lock);
level = PIC_IRQ_IS_EDGE_TRIGGERED(PIC_IRT_UART_0_INDEX);
xlr_write_reg(mmio, PIC_IRT_0_UART_0, 0x01);
xlr_write_reg(mmio, PIC_IRT_1_UART_0, ((1 << 31) | (level << 30) | (1 << 6) | (PIC_UART_0_IRQ)));
if (rmi_spin_mutex_safe)
mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("uart", filt,
(driver_intr_t *) intr, (void *)arg, PIC_UART_0_IRQ, flags, cookiep);
} else if (strcmp(device_get_name(child), "rge") == 0) {
int irq;
/* This is a hack to pass in the irq */
irq = (intptr_t)ires->__r_i;
if (rmi_spin_mutex_safe)
mtx_lock_spin(&xlr_pic_lock);
reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
xlr_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, reg | (1 << 6) | (1 << 30) | (1 << 31));
if (rmi_spin_mutex_safe)
mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("rge", filt, (driver_intr_t *) intr, (void *)arg, irq, flags, cookiep);
} else if (strcmp(device_get_name(child), "ehci") == 0) {
if (rmi_spin_mutex_safe)
mtx_lock_spin(&xlr_pic_lock);
reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + PIC_USB_IRQ - PIC_IRQ_BASE);
xlr_write_reg(mmio, PIC_IRT_1_BASE + PIC_USB_IRQ - PIC_IRQ_BASE, reg | (1 << 6) | (1 << 30) | (1 << 31));
if (rmi_spin_mutex_safe)
mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("ehci", filt, (driver_intr_t *) intr, (void *)arg, PIC_USB_IRQ, flags, cookiep);
}
/*
* This causes a panic and looks recursive to me (RRS).
* BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, filt,
* intr, arg, cookiep);
*/
return (0);
}
static int
nexus_setup_intr(device_t dev, device_t child, struct resource *res, int flags,
driver_filter_t *filt, driver_intr_t *intr, void *arg, void **cookiep)
{
#ifdef INTRNG
return (intr_setup_irq(child, res, filt, intr, arg, flags, cookiep));
#else
int irq;
register_t s;
s = intr_disable();
irq = rman_get_start(res);
if (irq >= NUM_MIPS_IRQS) {
intr_restore(s);
return (0);
}
cpu_establish_hardintr(device_get_nameunit(child), filt, intr, arg,
irq, flags, cookiep);
intr_restore(s);
return (0);
#endif
}
static int
apb_attach(device_t dev)
{
struct apb_softc *sc = device_get_softc(dev);
#ifdef INTRNG
intptr_t xref = pic_xref(dev);
int miscirq;
#else
int rid = 0;
#endif
sc->apb_dev = dev;
sc->apb_mem_rman.rm_type = RMAN_ARRAY;
sc->apb_mem_rman.rm_descr = "APB memory window";
if(ar531x_soc >= AR531X_SOC_AR5315) {
if (rman_init(&sc->apb_mem_rman) != 0 ||
rman_manage_region(&sc->apb_mem_rman,
AR5315_APB_BASE,
AR5315_APB_BASE + AR5315_APB_SIZE - 1) != 0)
panic("apb_attach: failed to set up memory rman");
} else {
if (rman_init(&sc->apb_mem_rman) != 0 ||
rman_manage_region(&sc->apb_mem_rman,
AR5312_APB_BASE,
AR5312_APB_BASE + AR5312_APB_SIZE - 1) != 0)
panic("apb_attach: failed to set up memory rman");
}
sc->apb_irq_rman.rm_type = RMAN_ARRAY;
sc->apb_irq_rman.rm_descr = "APB IRQ";
if (rman_init(&sc->apb_irq_rman) != 0 ||
rman_manage_region(&sc->apb_irq_rman,
APB_IRQ_BASE, APB_IRQ_END) != 0)
panic("apb_attach: failed to set up IRQ rman");
#ifndef INTRNG
if ((sc->sc_misc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_SHAREABLE | RF_ACTIVE)) == NULL) {
device_printf(dev, "unable to allocate IRQ resource\n");
return (ENXIO);
}
if ((bus_setup_intr(dev, sc->sc_misc_irq, INTR_TYPE_MISC,
apb_filter, NULL, sc, &sc->sc_misc_ih))) {
device_printf(dev,
"WARNING: unable to register interrupt handler\n");
return (ENXIO);
}
#else
/* Register the interrupts */
if (apb_pic_register_isrcs(sc) != 0) {
device_printf(dev, "could not register PIC ISRCs\n");
return (ENXIO);
}
/*
* Now, when everything is initialized, it's right time to
* register interrupt controller to interrupt framefork.
*/
if (intr_pic_register(dev, xref) == NULL) {
device_printf(dev, "could not register PIC\n");
return (ENXIO);
}
if(ar531x_soc >= AR531X_SOC_AR5315) {
miscirq = AR5315_CPU_IRQ_MISC;
} else {
miscirq = AR5312_IRQ_MISC;
}
cpu_establish_hardintr("aric", apb_filter, NULL, sc, miscirq,
INTR_TYPE_MISC, NULL);
#endif
/* mask all misc interrupt */
if(ar531x_soc >= AR531X_SOC_AR5315) {
ATH_WRITE_REG(AR5315_SYSREG_BASE
+ AR5315_SYSREG_MISC_INTMASK, 0);
} else {
ATH_WRITE_REG(AR5312_SYSREG_BASE
+ AR5312_SYSREG_MISC_INTMASK, 0);
}
bus_generic_probe(dev);
bus_enumerate_hinted_children(dev);
bus_generic_attach(dev);
return (0);
}
static int
mtk_gic_attach(device_t dev)
{
struct mtk_gic_softc *sc;
intptr_t xref = gic_xref(dev);
int i;
sc = device_get_softc(dev);
if (bus_alloc_resources(dev, mtk_gic_spec, sc->gic_res)) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
}
sc->gic_dev = dev;
/* Initialize mutex */
mtx_init(&sc->mutex, "PIC lock", "", MTX_SPIN);
/* Set the number of interrupts */
sc->nirqs = nitems(sc->gic_irqs);
/* Mask all interrupts */
WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF);
/* All interrupts are of type level */
WRITE4(sc, MTK_INTTRIG, 0x00000000);
/* All interrupts are of positive polarity */
WRITE4(sc, MTK_INTPOL, 0xFFFFFFFF);
/*
* Route all interrupts to pin 0 on VPE 0;
*/
for (i = 0; i < 32; i++) {
WRITE4(sc, MTK_MAPPIN(i), MTK_PIN_BITS(0));
WRITE4(sc, MTK_MAPVPE(i, 0), MTK_VPE_BITS(0));
}
/* Register the interrupts */
if (mtk_gic_register_isrcs(sc) != 0) {
device_printf(dev, "could not register GIC ISRCs\n");
goto cleanup;
}
/*
* Now, when everything is initialized, it's right time to
* register interrupt controller to interrupt framefork.
*/
if (intr_pic_register(dev, xref) == NULL) {
device_printf(dev, "could not register PIC\n");
goto cleanup;
}
cpu_establish_hardintr("gic", mtk_gic_intr, NULL, sc, 0, INTR_TYPE_CLK,
NULL);
return (0);
cleanup:
bus_release_resources(dev, mtk_gic_spec, sc->gic_res);
return(ENXIO);
}