CPUX86State *cpu_x86_init(const char *cpu_model) { CPUX86State *env; static int inited; env = qemu_mallocz(sizeof(CPUX86State)); if (!env) return NULL; cpu_exec_init(env); env->cpu_model_str = cpu_model; /* init various static tables */ if (!inited) { inited = 1; optimize_flags_init(); } if (cpu_x86_register(env, cpu_model) < 0) { cpu_x86_close(env); return NULL; } argos_init(env); cpu_reset(env); #ifdef USE_KQEMU kqemu_init(env); #endif return env; }
static void uc32_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); UniCore32CPU *cpu = UNICORE32_CPU(obj); CPUUniCore32State *env = &cpu->env; static bool inited; cs->env_ptr = env; cpu_exec_init(env); #ifdef CONFIG_USER_ONLY env->uncached_asr = ASR_MODE_USER; env->regs[31] = 0; #else env->uncached_asr = ASR_MODE_PRIV; env->regs[31] = 0x03000000; #endif tlb_flush(cs, 1); if (tcg_enabled() && !inited) { inited = true; uc32_translate_init(); } }
static void xtensa_cpu_initfn(Object *obj) { XtensaCPU *cpu = XTENSA_CPU(obj); CPUXtensaState *env = &cpu->env; cpu_exec_init(env); }
static void arm_cpu_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); cpu_exec_init(&cpu->env); cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); }
static void s390_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); S390CPU *cpu = S390_CPU(obj); CPUS390XState *env = &cpu->env; static bool inited; static int cpu_num = 0; #if !defined(CONFIG_USER_ONLY) struct tm tm; #endif cs->env_ptr = env; cpu_exec_init(env); #if !defined(CONFIG_USER_ONLY) qemu_register_reset(s390_cpu_machine_reset_cb, cpu); qemu_get_timedate(&tm, 0); env->tod_offset = TOD_UNIX_EPOCH + (time2tod(mktimegm(&tm)) * 1000000000ULL); env->tod_basetime = 0; env->tod_timer = qemu_new_timer_ns(vm_clock, s390x_tod_timer, cpu); env->cpu_timer = qemu_new_timer_ns(vm_clock, s390x_cpu_timer, cpu); /* set CPUState::halted state to 1 to avoid decrementing the running * cpu counter in s390_cpu_reset to a negative number at * initial ipl */ cs->halted = 1; #endif env->cpu_num = cpu_num++; env->ext_index = -1; if (tcg_enabled() && !inited) { inited = true; s390x_translate_init(); } }
CPUXtensaState *cpu_xtensa_init(const char *cpu_model) { static int tcg_inited; CPUXtensaState *env; const XtensaConfig *config = NULL; int i; for (i = 0; i < ARRAY_SIZE(core_config); ++i) if (strcmp(core_config[i].name, cpu_model) == 0) { config = core_config + i; break; } if (config == NULL) { return NULL; } env = g_malloc0(sizeof(*env)); env->config = config; cpu_exec_init(env); if (!tcg_inited) { tcg_inited = 1; xtensa_translate_init(); } xtensa_irq_init(env); qemu_init_vcpu(env); return env; }
static void arm_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); ARMCPU *cpu = ARM_CPU(obj); static bool inited; cs->env_ptr = &cpu->env; cpu_exec_init(&cpu->env); cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); #ifndef CONFIG_USER_ONLY /* Our inbound IRQ and FIQ lines */ if (kvm_enabled()) { qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2); } else { qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2); } cpu->gt_timer[GTIMER_PHYS] = qemu_new_timer(vm_clock, GTIMER_SCALE, arm_gt_ptimer_cb, cpu); cpu->gt_timer[GTIMER_VIRT] = qemu_new_timer(vm_clock, GTIMER_SCALE, arm_gt_vtimer_cb, cpu); qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs, ARRAY_SIZE(cpu->gt_timer_outputs)); #endif if (tcg_enabled() && !inited) { inited = true; arm_translate_init(); } }
static void s390_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); S390CPU *cpu = S390_CPU(obj); CPUS390XState *env = &cpu->env; static bool inited; static int cpu_num = 0; #if !defined(CONFIG_USER_ONLY) struct tm tm; #endif cs->env_ptr = env; cpu_exec_init(env); #if !defined(CONFIG_USER_ONLY) qemu_register_reset(s390_cpu_machine_reset_cb, cpu); qemu_get_timedate(&tm, 0); env->tod_offset = TOD_UNIX_EPOCH + (time2tod(mktimegm(&tm)) * 1000000000ULL); env->tod_basetime = 0; env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu); env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu); s390_cpu_set_state(CPU_STATE_STOPPED, cpu); #endif env->cpu_num = cpu_num++; if (tcg_enabled() && !inited) { inited = true; s390x_translate_init(); } }
CPUState *cpu_lm32_init(const char *cpu_model) { CPUState *env; const LM32Def *def; static int tcg_initialized; def = cpu_lm32_find_by_name(cpu_model); if (!def) { return NULL; } env = qemu_mallocz(sizeof(CPUState)); env->features = def->features; env->num_bps = def->num_breakpoints; env->num_wps = def->num_watchpoints; env->cfg = cfg_by_def(def); env->flags = 0; cpu_exec_init(env); cpu_reset(env); if (!tcg_initialized) { tcg_initialized = 1; lm32_translate_init(); } return env; }
static void superh_cpu_initfn(Object *obj) { SuperHCPU *cpu = SUPERH_CPU(obj); CPUSH4State *env = &cpu->env; cpu_exec_init(env); env->movcal_backup_tail = &(env->movcal_backup); }
static void mb_cpu_initfn(Object *obj) { MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); CPUMBState *env = &cpu->env; cpu_exec_init(env); set_float_rounding_mode(float_round_nearest_even, &env->fp_status); }
static void lm32_cpu_initfn(Object *obj) { LM32CPU *cpu = LM32_CPU(obj); CPULM32State *env = &cpu->env; cpu_exec_init(env); env->flags = 0; cpu_reset(CPU(cpu)); }
CPUSH4State *cpu_sh4_init(void) { CPUSH4State *env; env = qemu_mallocz(sizeof(CPUSH4State)); if (!env) return NULL; cpu_exec_init(env); cpu_sh4_reset(env); tlb_flush(env, 1); return env; }
static void riscv_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj); CPURISCVState *env = &cpu->env; cs->env_ptr = env; cpu_exec_init(env); if (tcg_enabled()) { riscv_tcg_init(); } }
static void sparc_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); SPARCCPU *cpu = SPARC_CPU(obj); CPUSPARCState *env = &cpu->env; cs->env_ptr = env; cpu_exec_init(env); if (tcg_enabled()) { gen_intermediate_code_init(env); } }
static void mips_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); MIPSCPU *cpu = MIPS_CPU(obj); CPUMIPSState *env = &cpu->env; cs->env_ptr = env; cpu_exec_init(env); if (tcg_enabled()) { mips_tcg_init(); } }
static void tricore_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); TriCoreCPU *cpu = TRICORE_CPU(obj); CPUTriCoreState *env = &cpu->env; cs->env_ptr = env; cpu_exec_init(cs, &error_abort); if (tcg_enabled()) { tricore_tcg_init(); } }
static void moxie_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); MoxieCPU *cpu = MOXIE_CPU(obj); static int inited; cs->env_ptr = &cpu->env; cpu_exec_init(cs, &error_abort); if (tcg_enabled() && !inited) { inited = 1; moxie_translate_init(); } }
static void tilegx_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); TileGXCPU *cpu = TILEGX_CPU(obj); CPUTLGState *env = &cpu->env; static bool tcg_initialized; cs->env_ptr = env; cpu_exec_init(cs, &error_abort); if (tcg_enabled() && !tcg_initialized) { tcg_initialized = true; tilegx_tcg_init(); } }
static void superh_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); SuperHCPU *cpu = SUPERH_CPU(obj); CPUSH4State *env = &cpu->env; cs->env_ptr = env; cpu_exec_init(env); env->movcal_backup_tail = &(env->movcal_backup); if (tcg_enabled()) { sh4_translate_init(); } }
static void xtensa_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); XtensaCPU *cpu = XTENSA_CPU(obj); CPUXtensaState *env = &cpu->env; static bool tcg_inited; cs->env_ptr = env; cpu_exec_init(env); if (tcg_enabled() && !tcg_inited) { tcg_inited = true; xtensa_translate_init(); cpu_set_debug_excp_handler(xtensa_breakpoint_handler); } }
static void arm_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); ARMCPU *cpu = ARM_CPU(obj); static bool inited; cs->env_ptr = &cpu->env; cpu_exec_init(&cpu->env); cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); if (tcg_enabled() && !inited) { inited = true; arm_translate_init(); } }
CPUSPARCState *cpu_sparc_init(const char *cpu_model) { CPUSPARCState *env; env = g_new0(CPUSPARCState, 1); cpu_exec_init(env); gen_intermediate_code_init(env); if (cpu_sparc_register(env, cpu_model) < 0) { cpu_sparc_close(env); return NULL; } qemu_init_vcpu(env); return env; }
static void xtensa_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); XtensaCPU *cpu = XTENSA_CPU(obj); XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj); CPUXtensaState *env = &cpu->env; static bool tcg_inited; cs->env_ptr = env; env->config = xcc->config; cpu_exec_init(cs, &error_abort); if (tcg_enabled() && !tcg_inited) { tcg_inited = true; xtensa_translate_init(); } }
static void lm32_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); LM32CPU *cpu = LM32_CPU(obj); CPULM32State *env = &cpu->env; static bool tcg_initialized; cs->env_ptr = env; cpu_exec_init(env); env->flags = 0; if (tcg_enabled() && !tcg_initialized) { tcg_initialized = true; lm32_translate_init(); } }
static void uc32_cpu_initfn(Object *obj) { UniCore32CPU *cpu = UNICORE32_CPU(obj); CPUUniCore32State *env = &cpu->env; cpu_exec_init(env); #ifdef CONFIG_USER_ONLY env->uncached_asr = ASR_MODE_USER; env->regs[31] = 0; #else env->uncached_asr = ASR_MODE_PRIV; env->regs[31] = 0x03000000; #endif tlb_flush(env, 1); }
static void mb_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); CPUMBState *env = &cpu->env; static bool tcg_initialized; cs->env_ptr = env; cpu_exec_init(env); set_float_rounding_mode(float_round_nearest_even, &env->fp_status); if (tcg_enabled() && !tcg_initialized) { tcg_initialized = true; mb_tcg_init(); } }
CPUAVR32State *cpu_avr32_init(const char *cpu_model) { /* SN: TBD */ CPUAVR32State *env; static int inited = 0; env = g_malloc0(sizeof(CPUAVR32State)); cpu_exec_init(env); if (!inited) { inited = 1; avr32_translate_init(); } cpu_reset(env); qemu_init_vcpu(env); return env; }
static void alpha_cpu_initfn(Object *obj) { AlphaCPU *cpu = ALPHA_CPU(obj); CPUAlphaState *env = &cpu->env; cpu_exec_init(env); tlb_flush(env, 1); #if defined(CONFIG_USER_ONLY) env->ps = PS_USER_MODE; cpu_alpha_store_fpcr(env, (FPCR_INVD | FPCR_DZED | FPCR_OVFD | FPCR_UNFD | FPCR_INED | FPCR_DNOD | FPCR_DYN_NORMAL)); #endif env->lock_addr = -1; env->fen = 1; }
static void openrisc_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); OpenRISCCPU *cpu = OPENRISC_CPU(obj); static int inited; cs->env_ptr = &cpu->env; cpu_exec_init(&cpu->env); #ifndef CONFIG_USER_ONLY cpu_openrisc_mmu_init(cpu); #endif if (tcg_enabled() && !inited) { inited = 1; openrisc_translate_init(); } }