示例#1
0
ROM_END

/***************************************************************************

  Game driver(s)

***************************************************************************/

static KONAMI_SETLINES_CALLBACK( crimfght_banking )
{
	UINT8 *RAM = memory_region(device->machine, "maincpu");
	int offs = 0;

	/* bit 5 = select work RAM or palette */
	if (lines & 0x20)
	{
		memory_install_readwrite8_handler(cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM), 0x0000, 0x03ff, 0, 0, (read8_space_func)SMH_BANK(3), paletteram_xBBBBBGGGGGRRRRR_be_w);
		memory_set_bankptr(device->machine, 3, paletteram);
	}
	else
		memory_install_readwrite8_handler(cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM), 0x0000, 0x03ff, 0, 0, (read8_space_func)SMH_BANK(1), (write8_space_func)SMH_BANK(1));								/* RAM */

	/* bit 6 = enable char ROM reading through the video RAM */
	K052109_set_RMRD_line((lines & 0x40) ? ASSERT_LINE : CLEAR_LINE);

	offs = 0x10000 + ((lines & 0x0f) * 0x2000);
	memory_set_bankptr(device->machine, 2, &RAM[offs]);
}
示例#2
0
static void galpani2_write_kaneko(running_device *device)
{
	const address_space *dstspace = cpu_get_address_space(device, ADDRESS_SPACE_PROGRAM);
	int i,x,tpattidx;
	unsigned char testpattern[] = {0xFF,0x55,0xAA,0xDD,0xBB,0x99};

	/* Write "KANEKO" to 100000-100005, but do not clash with ram test */

	x  = 0;

	for (i = 0x100000; i < 0x100007; i++)
	{
		for (tpattidx = 0; tpattidx < 6; tpattidx++)
		{
			if (memory_read_byte(dstspace,i) == testpattern[tpattidx]) x = 1; //ram test fragment present
		}
	}

	if	( x == 0 )
	{
		memory_write_byte(dstspace,0x100000,0x4b); //K
		memory_write_byte(dstspace,0x100001,0x41); //A
		memory_write_byte(dstspace,0x100002,0x4e); //N
		memory_write_byte(dstspace,0x100003,0x45); //E
		memory_write_byte(dstspace,0x100004,0x4b); //K
		memory_write_byte(dstspace,0x100005,0x4f); //O
	}
}
示例#3
0
static STATE_POSTLOAD( schaser_reinit_555_time_remain )
{
    mw8080bw_state *state = machine->driver_data<mw8080bw_state>();
    address_space *space = cpu_get_address_space(state->maincpu, ADDRESS_SPACE_PROGRAM);
    state->schaser_effect_555_time_remain = double_to_attotime(state->schaser_effect_555_time_remain_savable);
    schaser_sh_port_2_w(space, 0, state->port_2_last_extra);
}
示例#4
0
/***************************************************************************

    The FairyLand Story

    added Victorious Nine by BUT

    TODO:
    - TA7630 emulation needs filter support (bass sounds from MSM5232 should be about 2 times louder)

***************************************************************************/

#include "emu.h"
#include "deprecat.h"
#include "cpu/z80/z80.h"
#include "cpu/m6805/m6805.h"
#include "sound/ay8910.h"
#include "sound/msm5232.h"
#include "sound/dac.h"
#include "includes/flstory.h"

static READ8_HANDLER( from_snd_r )
{
    flstory_state *state = (flstory_state *)space->machine->driver_data;
    state->snd_flag = 0;
    return state->snd_data;
}

static READ8_HANDLER( snd_flag_r )
{
    flstory_state *state = (flstory_state *)space->machine->driver_data;
    return state->snd_flag | 0xfd;
}

static WRITE8_HANDLER( to_main_w )
{
    flstory_state *state = (flstory_state *)space->machine->driver_data;
    state->snd_data = data;
    state->snd_flag = 2;
}

static TIMER_CALLBACK( nmi_callback )
{
    flstory_state *state = (flstory_state *)machine->driver_data;
    if (state->sound_nmi_enable)
        cpu_set_input_line(state->audiocpu, INPUT_LINE_NMI, PULSE_LINE);
    else
        state->pending_nmi = 1;
}

static WRITE8_HANDLER( sound_command_w )
{
    soundlatch_w(space, 0, data);
    timer_call_after_resynch(space->machine, NULL, data, nmi_callback);
}


static WRITE8_HANDLER( nmi_disable_w )
{
    flstory_state *state = (flstory_state *)space->machine->driver_data;
    state->sound_nmi_enable = 0;
}

static WRITE8_HANDLER( nmi_enable_w )
{
    flstory_state *state = (flstory_state *)space->machine->driver_data;
    state->sound_nmi_enable = 1;
    if (state->pending_nmi)
    {
        cpu_set_input_line(state->audiocpu, INPUT_LINE_NMI, PULSE_LINE);
        state->pending_nmi = 0;
    }
}

static ADDRESS_MAP_START( flstory_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0xbfff) AM_ROM
AM_RANGE(0xc000, 0xc7ff) AM_RAM_WRITE(flstory_videoram_w) AM_BASE_SIZE_MEMBER(flstory_state, videoram, videoram_size)
AM_RANGE(0xc800, 0xcfff) AM_RAM /* unknown */
AM_RANGE(0xd000, 0xd000) AM_READWRITE(flstory_mcu_r, flstory_mcu_w)
AM_RANGE(0xd001, 0xd001) AM_WRITENOP	/* watchdog? */
AM_RANGE(0xd002, 0xd002) AM_WRITENOP	/* coin lock out? */
AM_RANGE(0xd400, 0xd400) AM_READWRITE(from_snd_r, sound_command_w)
AM_RANGE(0xd401, 0xd401) AM_READ(snd_flag_r)
AM_RANGE(0xd403, 0xd403) AM_NOP	/* unknown */
AM_RANGE(0xd800, 0xd800) AM_READ_PORT("DSW0")
AM_RANGE(0xd801, 0xd801) AM_READ_PORT("DSW1")
AM_RANGE(0xd802, 0xd802) AM_READ_PORT("DSW2")
AM_RANGE(0xd803, 0xd803) AM_READ_PORT("SYSTEM")
AM_RANGE(0xd804, 0xd804) AM_READ_PORT("P1")
AM_RANGE(0xd805, 0xd805) AM_READ(flstory_mcu_status_r)
AM_RANGE(0xd806, 0xd806) AM_READ_PORT("P2")
//  AM_RANGE(0xda00, 0xda00) AM_WRITEONLY
AM_RANGE(0xdc00, 0xdc9f) AM_RAM AM_BASE_SIZE_MEMBER(flstory_state, spriteram, spriteram_size)
AM_RANGE(0xdca0, 0xdcbf) AM_RAM_WRITE(flstory_scrlram_w) AM_BASE_MEMBER(flstory_state, scrlram)
AM_RANGE(0xdcc0, 0xdcff) AM_RAM /* unknown */
AM_RANGE(0xdd00, 0xdeff) AM_READWRITE(flstory_palette_r, flstory_palette_w)
AM_RANGE(0xdf03, 0xdf03) AM_WRITE(flstory_gfxctrl_w)
AM_RANGE(0xe000, 0xe7ff) AM_RAM	/* work RAM */
ADDRESS_MAP_END

static ADDRESS_MAP_START( onna34ro_map, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0xbfff) AM_ROM
AM_RANGE(0xc000, 0xc7ff) AM_RAM_WRITE(flstory_videoram_w) AM_BASE_SIZE_MEMBER(flstory_state, videoram, videoram_size)
AM_RANGE(0xc800, 0xcfff) AM_RAM	/* unknown */
AM_RANGE(0xd000, 0xd000) AM_READWRITE(onna34ro_mcu_r, onna34ro_mcu_w)
AM_RANGE(0xd001, 0xd001) AM_WRITENOP	/* watchdog? */
AM_RANGE(0xd002, 0xd002) AM_WRITENOP	/* coin lock out? */
AM_RANGE(0xd400, 0xd400) AM_READWRITE(from_snd_r, sound_command_w)
AM_RANGE(0xd401, 0xd401) AM_READ(snd_flag_r)
AM_RANGE(0xd403, 0xd403) AM_NOP	/* unknown */
AM_RANGE(0xd800, 0xd800) AM_READ_PORT("DSW0")
AM_RANGE(0xd801, 0xd801) AM_READ_PORT("DSW1")
AM_RANGE(0xd802, 0xd802) AM_READ_PORT("DSW2")
AM_RANGE(0xd803, 0xd803) AM_READ_PORT("SYSTEM")
AM_RANGE(0xd804, 0xd804) AM_READ_PORT("P1")
AM_RANGE(0xd805, 0xd805) AM_READ(onna34ro_mcu_status_r)
AM_RANGE(0xd806, 0xd806) AM_READ_PORT("P2")
//  AM_RANGE(0xda00, 0xda00) AM_WRITEONLY
AM_RANGE(0xdc00, 0xdc9f) AM_RAM AM_BASE_SIZE_MEMBER(flstory_state, spriteram, spriteram_size)
AM_RANGE(0xdca0, 0xdcbf) AM_RAM_WRITE(flstory_scrlram_w) AM_BASE_MEMBER(flstory_state, scrlram)
AM_RANGE(0xdcc0, 0xdcff) AM_RAM /* unknown */
AM_RANGE(0xdd00, 0xdeff) AM_READWRITE(flstory_palette_r, flstory_palette_w)
AM_RANGE(0xdf03, 0xdf03) AM_WRITE(flstory_gfxctrl_w)
AM_RANGE(0xe000, 0xe7ff) AM_RAM AM_BASE_MEMBER(flstory_state, workram) /* work RAM */
ADDRESS_MAP_END

static CUSTOM_INPUT( victnine_mcu_status_bit01_r )
{
    flstory_state *state = (flstory_state *)field->port->machine->driver_data;
    const address_space *space = cpu_get_address_space(state->maincpu, ADDRESS_SPACE_PROGRAM);

    return (victnine_mcu_status_r(space, 0) & 3);
}
示例#5
0
static void update_memory_mapping(running_machine *machine, struct memory_mapper_chip *chip, int decrypt)
{
	int rgnum;

	if (LOG_MEMORY_MAP) mame_printf_debug("----\nRemapping:\n");

	/* first reset everything back to the beginning */
	memory_install_readwrite16_handler(cpu_get_address_space(chip->cpu, ADDRESS_SPACE_PROGRAM), 0x000000, 0xffffff, 0, 0, segaic16_memory_mapper_lsb_r, segaic16_memory_mapper_lsb_w);

	/* loop over the regions */
	for (rgnum = 0; chip->map[rgnum].regbase != 0; rgnum++)
	{
		static const offs_t region_size_map[4] = { 0x00ffff, 0x01ffff, 0x07ffff, 0x1fffff };
		const segaic16_memory_map_entry *rgn = &chip->map[rgnum];
		offs_t region_size = region_size_map[chip->regs[rgn->regbase] & 3];
		offs_t region_base = (chip->regs[rgn->regbase + 1] << 16) & ~region_size;
		offs_t region_mirror = rgn->mirror & region_size;
		offs_t region_start = region_base + (rgn->regoffs & region_size);
		offs_t region_end = region_start + ((rgn->length - 1 < region_size) ? rgn->length - 1 : region_size);
		const char *writebank = rgn->writebank;
		write16_space_func write = rgn->write;
		const char *readbank = rgn->readbank;
		read16_space_func read = rgn->read;

		/* ROM areas need extra clamping */
		if (rgn->romoffset != ~0)
		{
			offs_t romsize = chip->cpu->region()->bytes();
			if (region_start >= romsize)
				read = NULL;
			else if (region_start + rgn->length > romsize)
				region_end = romsize - 1;
		}

		/* map it */
		if (read != NULL)
			memory_install_read16_handler(cpu_get_address_space(chip->cpu, ADDRESS_SPACE_PROGRAM), region_start, region_end, 0, region_mirror, read);
		else if (readbank != NULL)
			memory_install_read_bank(cpu_get_address_space(chip->cpu, ADDRESS_SPACE_PROGRAM), region_start, region_end, 0, region_mirror, readbank);
		if (write != NULL)
			memory_install_write16_handler(cpu_get_address_space(chip->cpu, ADDRESS_SPACE_PROGRAM), region_start, region_end, 0, region_mirror, write);
		else if (writebank != NULL)
			memory_install_write_bank(cpu_get_address_space(chip->cpu, ADDRESS_SPACE_PROGRAM), region_start, region_end, 0, region_mirror, writebank);

		/* set the bank pointer */
		if (readbank != NULL)
		{
			if (rgn->base != NULL)
			{
				memory_configure_bank(machine, readbank, 0, 1, *rgn->base, 0);
				memory_set_bank(machine, readbank, 0);
			}
			else if (rgn->romoffset != ~0)
			{
				UINT8 *decrypted = NULL;

				if (decrypt)
				{
					decrypted = (UINT8 *)fd1094_get_decrypted_base();
					if (!decrypted)
						decrypted = (UINT8 *)fd1089_get_decrypted_base();
				}

				memory_configure_bank(machine, readbank, 0, 1, chip->cpu->region()->base() + region_start, 0);
				if (decrypted)
					memory_configure_bank_decrypted(machine, readbank, 0, 1, decrypted + region_start, 0);

				memory_set_bank(machine, readbank, 0);
			}
		}

		if (LOG_MEMORY_MAP) mame_printf_debug("  %06X-%06X (%06X) = %s\n", region_start, region_end, region_mirror, rgn->name);
	}
}
示例#6
0
static void memory_mapper_w(const address_space *space, struct memory_mapper_chip *chip, offs_t offset, UINT8 data)
{
	UINT8 oldval;

	/* wraps every 32 bytes */
	offset &= 0x1f;

	/* remember the previous value and swap in the new one */
	oldval = chip->regs[offset];
	chip->regs[offset] = data;

	/* switch off the offset */
	switch (offset)
	{
		case 0x02:
			/* misc commands */
			/*   00 - resume execution after 03 */
			/*   03 - maybe controls halt and reset lines together? */
			if ((oldval ^ chip->regs[offset]) & 3)
			{
				if ((chip->regs[offset] & 3) == 3)
					fd1094_machine_init(chip->cpu);

				/* fd1094_machine_init calls device_reset on the CPU, so we must do this afterwards */
				cpu_set_input_line(chip->cpu, INPUT_LINE_RESET, (chip->regs[offset] & 3) == 3 ? ASSERT_LINE : CLEAR_LINE);
			}
			break;

		case 0x03:
			if (chip->sound_w)
				(*chip->sound_w)(space->machine, data);
			break;

		case 0x04:
			/* controls IRQ lines to 68000, negative logic -- write $B to signal IRQ4 */
			if ((chip->regs[offset] & 7) != 7)
			{
				int irqnum;
				for (irqnum = 0; irqnum < 8; irqnum++)
					cpu_set_input_line(chip->cpu, irqnum, (irqnum == (~chip->regs[offset] & 7)) ? HOLD_LINE : CLEAR_LINE);
			}
			break;

		case 0x05:
			/* read/write control */
			/*   01 - write data latched in 00,01 to 2 * (address in 0A,0B,0C) */
			/*   02 - read data into latches 00,01 from 2 * (address in 07,08,09) */
			if (data == 0x01)
			{
				const address_space *targetspace = cpu_get_address_space(chip->cpu, ADDRESS_SPACE_PROGRAM);
				offs_t addr = (chip->regs[0x0a] << 17) | (chip->regs[0x0b] << 9) | (chip->regs[0x0c] << 1);
				memory_write_word(targetspace, addr, (chip->regs[0x00] << 8) | chip->regs[0x01]);
			}
			else if (data == 0x02)
			{
				const address_space *targetspace = cpu_get_address_space(chip->cpu, ADDRESS_SPACE_PROGRAM);
				offs_t addr = (chip->regs[0x07] << 17) | (chip->regs[0x08] << 9) | (chip->regs[0x09] << 1);
				UINT16 result;
				result = memory_read_word(targetspace, addr);
				chip->regs[0x00] = result >> 8;
				chip->regs[0x01] = result;
			}
			break;

		case 0x07:	case 0x08:	case 0x09:
			/* writes here latch a 68000 address for writing */
			break;

		case 0x0a:	case 0x0b:	case 0x0c:
			/* writes here latch a 68000 address for reading */
			break;

		case 0x10:	case 0x11:
		case 0x12:	case 0x13:
		case 0x14:	case 0x15:
		case 0x16:	case 0x17:
		case 0x18:	case 0x19:
		case 0x1a:	case 0x1b:
		case 0x1c:	case 0x1d:
		case 0x1e:	case 0x1f:
			if (oldval != data)
				update_memory_mapping(space->machine, chip, 1);
			break;

		default:
			logerror("Unknown memory_mapper_w to address %02X = %02X\n", offset, data);
			break;
	}
}