uint32_t* get_reg_pointer_32(int reg) { switch(reg) { case R_0_32 ... R_7_32: /* R0-R7 aka Global0-7 */ return &(cpu->gregs[reg]); case R_8_32 ... R_31_32: /* R8 to 31 : Out0-7, Local0-7, In0-7 */ return &(cpu->regwptr[reg-R_8_32]); case PSR_32: /* Compute PSR before exposing state. */ if (cpu->cc_op != CC_OP_FLAGS) { cpu_get_psr(cpu); } return &(cpu->psr); case TBR_32: return &(cpu->tbr); case Y_32: return &(cpu->y); case PC_32: return &(cpu->pc); case NPC_32: return &(cpu->npc); case ASR_16_32 ... ASR_31_32: return &(cpu->asr[reg-ASR_16_32]); case WIM_32: return &(cpu->wim); default: return NULL; } }
static void put_psr(QEMUFile *f, void *opaque, size_t size) { SPARCCPU *cpu = opaque; CPUSPARCState *env = &cpu->env; uint32_t val; val = cpu_get_psr(env); qemu_put_be32(f, val); }
static int put_psr(QEMUFile *f, void *opaque, size_t size, const VMStateField *field, QJSON *vmdesc) { SPARCCPU *cpu = opaque; CPUSPARCState *env = &cpu->env; uint32_t val; val = cpu_get_psr(env); qemu_put_be32(f, val); return 0; }
void cpu_dump_state(CPUSPARCState *env, FILE *f, fprintf_function cpu_fprintf, int flags) { int i, x; cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, env->npc); for (i = 0; i < 8; i++) { if (i % REGS_PER_LINE == 0) { cpu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1); } cpu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]); if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { cpu_fprintf(f, "\n"); } } for (x = 0; x < 3; x++) { for (i = 0; i < 8; i++) { if (i % REGS_PER_LINE == 0) { cpu_fprintf(f, "%%%c%d-%d: ", x == 0 ? 'o' : (x == 1 ? 'l' : 'i'), i, i + REGS_PER_LINE - 1); } cpu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]); if (i % REGS_PER_LINE == REGS_PER_LINE - 1) { cpu_fprintf(f, "\n"); } } } for (i = 0; i < TARGET_DPREGS; i++) { if ((i & 3) == 0) { cpu_fprintf(f, "%%f%02d: ", i * 2); } cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); if ((i & 3) == 3) { cpu_fprintf(f, "\n"); } } #ifdef TARGET_SPARC64 cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, (unsigned)cpu_get_ccr(env)); cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << PSR_CARRY_SHIFT); cpu_fprintf(f, " xcc: "); cpu_print_cc(f, cpu_fprintf, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4)); cpu_fprintf(f, ") asi: %02x tl: %d pil: %x\n", env->asi, env->tl, env->psrpil); cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d " "cleanwin: %d cwp: %d\n", env->cansave, env->canrestore, env->otherwin, env->wstate, env->cleanwin, env->nwindows - 1 - env->cwp); cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: " TARGET_FMT_lx "\n", env->fsr, env->y, env->fprs); #else cpu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env)); cpu_print_cc(f, cpu_fprintf, cpu_get_psr(env)); cpu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-', env->psrps ? 'P' : '-', env->psret ? 'E' : '-', env->wim); cpu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n", env->fsr, env->y); #endif cpu_fprintf(f, "\n"); }
void sparc_cpu_do_interrupt(CPUState *cs) { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; int intno = cs->exception_index; trap_state *tsptr; /* Compute PSR before exposing state. */ if (env->cc_op != CC_OP_FLAGS) { cpu_get_psr(env); } #ifdef DEBUG_PCALL if (qemu_loglevel_mask(CPU_LOG_INT)) { static int count; const char *name; if (intno < 0 || intno >= 0x180) { name = "Unknown"; } else if (intno >= 0x100) { name = "Trap Instruction"; } else if (intno >= 0xc0) { name = "Window Fill"; } else if (intno >= 0x80) { name = "Window Spill"; } else { name = excp_names[intno]; if (!name) { name = "Unknown"; } } qemu_log("%6d: %s (v=%04x)\n", count, name, intno); log_cpu_state(cs, 0); #if 0 { int i; uint8_t *ptr; qemu_log(" code="); ptr = (uint8_t *)env->pc; for (i = 0; i < 16; i++) { qemu_log(" %02x", ldub(ptr + i)); } qemu_log("\n"); } #endif count++; } #endif #if !defined(CONFIG_USER_ONLY) if (env->tl >= env->maxtl) { cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d)," " Error state", cs->exception_index, env->tl, env->maxtl); return; } #endif if (env->tl < env->maxtl - 1) { env->tl++; } else { env->pstate |= PS_RED; if (env->tl < env->maxtl) { env->tl++; } } tsptr = cpu_tsptr(env); tsptr->tstate = (cpu_get_ccr(env) << 32) | ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) | cpu_get_cwp64(env); tsptr->tpc = env->pc; tsptr->tnpc = env->npc; tsptr->tt = intno; switch (intno) { case TT_IVEC: cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG); break; case TT_TFAULT: case TT_DFAULT: case TT_TMISS ... TT_TMISS + 3: case TT_DMISS ... TT_DMISS + 3: case TT_DPROT ... TT_DPROT + 3: cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG); break; default: cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG); break; } if (intno == TT_CLRWIN) { cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - 1)); } else if ((intno & 0x1c0) == TT_SPILL) { cpu_set_cwp(env, cpu_cwp_dec(env, env->cwp - env->cansave - 2)); } else if ((intno & 0x1c0) == TT_FILL) { cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1)); } env->tbr &= ~0x7fffULL; env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5); env->pc = env->tbr; env->npc = env->pc + 4; cs->exception_index = -1; }
target_ulong helper_rdpsr(CPUSPARCState *env) { return cpu_get_psr(env); }
static target_long monitor_get_psr (const struct MonitorDef *md, int val) { CPUArchState *env = mon_get_cpu_env(); return cpu_get_psr(env); }
void cpu_save(QEMUFile *f, void *opaque) { CPUSPARCState *env = opaque; int i; uint32_t tmp; // if env->cwp == env->nwindows - 1, this will set the ins of the last // window as the outs of the first window cpu_set_cwp(env, env->cwp); for(i = 0; i < 8; i++) qemu_put_betls(f, &env->gregs[i]); qemu_put_be32s(f, &env->nwindows); for(i = 0; i < env->nwindows * 16; i++) qemu_put_betls(f, &env->regbase[i]); /* FPU */ for (i = 0; i < TARGET_DPREGS; i++) { qemu_put_be32(f, env->fpr[i].l.upper); qemu_put_be32(f, env->fpr[i].l.lower); } qemu_put_betls(f, &env->pc); qemu_put_betls(f, &env->npc); qemu_put_betls(f, &env->y); tmp = cpu_get_psr(env); qemu_put_be32(f, tmp); qemu_put_betls(f, &env->fsr); qemu_put_betls(f, &env->tbr); tmp = env->interrupt_index; qemu_put_be32(f, tmp); qemu_put_be32s(f, &env->pil_in); #ifndef TARGET_SPARC64 qemu_put_be32s(f, &env->wim); /* MMU */ for (i = 0; i < 32; i++) qemu_put_be32s(f, &env->mmuregs[i]); for (i = 0; i < 4; i++) { qemu_put_be64s(f, &env->mxccdata[i]); } for (i = 0; i < 8; i++) { qemu_put_be64s(f, &env->mxccregs[i]); } qemu_put_be32s(f, &env->mmubpctrv); qemu_put_be32s(f, &env->mmubpctrc); qemu_put_be32s(f, &env->mmubpctrs); qemu_put_be64s(f, &env->mmubpaction); for (i = 0; i < 4; i++) { qemu_put_be64s(f, &env->mmubpregs[i]); } #else qemu_put_be64s(f, &env->lsu); for (i = 0; i < 16; i++) { qemu_put_be64s(f, &env->immuregs[i]); qemu_put_be64s(f, &env->dmmuregs[i]); } for (i = 0; i < 64; i++) { qemu_put_be64s(f, &env->itlb[i].tag); qemu_put_be64s(f, &env->itlb[i].tte); qemu_put_be64s(f, &env->dtlb[i].tag); qemu_put_be64s(f, &env->dtlb[i].tte); } qemu_put_be32s(f, &env->mmu_version); for (i = 0; i < MAXTL_MAX; i++) { qemu_put_be64s(f, &env->ts[i].tpc); qemu_put_be64s(f, &env->ts[i].tnpc); qemu_put_be64s(f, &env->ts[i].tstate); qemu_put_be32s(f, &env->ts[i].tt); } qemu_put_be32s(f, &env->xcc); qemu_put_be32s(f, &env->asi); qemu_put_be32s(f, &env->pstate); qemu_put_be32s(f, &env->tl); qemu_put_be32s(f, &env->cansave); qemu_put_be32s(f, &env->canrestore); qemu_put_be32s(f, &env->otherwin); qemu_put_be32s(f, &env->wstate); qemu_put_be32s(f, &env->cleanwin); for (i = 0; i < 8; i++) qemu_put_be64s(f, &env->agregs[i]); for (i = 0; i < 8; i++) qemu_put_be64s(f, &env->bgregs[i]); for (i = 0; i < 8; i++) qemu_put_be64s(f, &env->igregs[i]); for (i = 0; i < 8; i++) qemu_put_be64s(f, &env->mgregs[i]); qemu_put_be64s(f, &env->fprs); qemu_put_be64s(f, &env->tick_cmpr); qemu_put_be64s(f, &env->stick_cmpr); cpu_put_timer(f, env->tick); cpu_put_timer(f, env->stick); qemu_put_be64s(f, &env->gsr); qemu_put_be32s(f, &env->gl); qemu_put_be64s(f, &env->hpstate); for (i = 0; i < MAXTL_MAX; i++) qemu_put_be64s(f, &env->htstate[i]); qemu_put_be64s(f, &env->hintp); qemu_put_be64s(f, &env->htba); qemu_put_be64s(f, &env->hver); qemu_put_be64s(f, &env->hstick_cmpr); qemu_put_be64s(f, &env->ssr); cpu_put_timer(f, env->hstick); #endif }
void sparc_cpu_do_interrupt(CPUState *cs) { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; int cwp, intno = cs->exception_index; /* Compute PSR before exposing state. */ if (env->cc_op != CC_OP_FLAGS) { cpu_get_psr(env); } #ifdef DEBUG_PCALL if (qemu_loglevel_mask(CPU_LOG_INT)) { static int count; const char *name; if (intno < 0 || intno >= 0x100) { name = "Unknown"; } else if (intno >= 0x80) { name = "Trap Instruction"; } else { name = excp_names[intno]; if (!name) { name = "Unknown"; } } qemu_log("%6d: %s (v=%02x)\n", count, name, intno); log_cpu_state(cs, 0); #if 0 { int i; uint8_t *ptr; qemu_log(" code="); ptr = (uint8_t *)env->pc; for (i = 0; i < 16; i++) { qemu_log(" %02x", ldub(ptr + i)); } qemu_log("\n"); } #endif count++; } #endif #if !defined(CONFIG_USER_ONLY) if (env->psret == 0) { if (cs->exception_index == 0x80 && env->def->features & CPU_FEATURE_TA0_SHUTDOWN) { qemu_system_shutdown_request(); } else { cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error state", cs->exception_index); } return; } #endif env->psret = 0; cwp = cpu_cwp_dec(env, env->cwp - 1); cpu_set_cwp(env, cwp); env->regwptr[9] = env->pc; env->regwptr[10] = env->npc; env->psrps = env->psrs; env->psrs = 1; env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4); env->pc = env->tbr; env->npc = env->pc + 4; cs->exception_index = -1; #if !defined(CONFIG_USER_ONLY) /* IRQ acknowledgment */ if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) { env->qemu_irq_ack(env, env->irq_manager, intno); } #endif }