static READ8_HANDLER( solomon_0xe603_r )
{
if (cpu_get_pc(space->cpu) == 0x161) // all the time .. return 0 to act as before for coin / startup etc.
{
return 0;
}
else if (cpu_get_pc(space->cpu) == 0x4cf0) // stop it clearing the screen at certain scores
{
return (cpu_get_reg(space->cpu, Z80_BC) & 0x08);
}
else
{
mame_printf_debug("unhandled solomon_0xe603_r %04x\n", cpu_get_pc(space->cpu));
return 0;
}
}
static READ16_HANDLER( bmc_protection_r )
{
switch(cpu_get_previouspc(&space->device()))
{
case 0xca68:
switch(cpu_get_reg(&space->device(), M68K_D2))
{
case 0: return 0x37<<8;
case 0x1013: return 0;
default: return 0x46<<8;
}
break;
}
logerror("Protection read @ %X\n",cpu_get_previouspc(&space->device()));
return space->machine().rand();
}
static READ32_HANDLER( ddp2_speedup_r )
{
pgm_arm_type2_state *state = space->machine().driver_data<pgm_arm_type2_state>();
int pc = cpu_get_pc(&space->device());
UINT32 data = state->m_arm_ram[0x300c/4];
if (pc==0x080109b4)
{
/* if we've hit the loop where this is read and both values are 0 then the only way out is an interrupt */
int r4 = (cpu_get_reg(&space->device(), ARM7_R4));
r4 += 0xe;
if (r4==0x18002f9e)
{
UINT32 data2 = state->m_arm_ram[0x2F9C/4]&0xffff0000;
if ((data==0x00000000) && (data2==0x00000000)) device_spin_until_interrupt(&space->device());
}
}
return data;
}
/* Returns the address of a 68HC12 indexed operand.
Pre and post modifications are handled on the source register. */
uint16
cpu_get_indexed_operand_addr (sim_cpu* cpu, int restrict)
{
uint8 reg;
uint16 sval;
uint16 addr;
uint8 code;
code = cpu_fetch8 (cpu);
/* n,r with 5-bit signed constant. */
if ((code & 0x20) == 0)
{
reg = (code >> 6) & 3;
sval = (code & 0x1f);
if (code & 0x10)
sval |= 0xfff0;
addr = cpu_get_reg (cpu, reg);
addr += sval;
}
ROM_END
/*************************************
*
* Driver speedups
*
*************************************/
/*
In-game hotspot @ 0180F8D8
*/
READ32_MEMBER( beathead_state::speedup_r )
{
int result = *m_speedup_data;
if ((cpu_get_previouspc(&space.device()) & 0xfffff) == 0x006f0 && result == cpu_get_reg(&space.device(), ASAP_R3))
device_spin_until_interrupt(&space.device());
return result;
}
void meadows_sh_update(running_machine &machine)
{
meadows_state *state = machine.driver_data<meadows_state>();
samples_device *samples = machine.device<samples_device>("samples");
int preset, amp;
if (state->m_latched_0c01 != state->m_0c01 || state->m_latched_0c03 != state->m_0c03)
{
/* amplitude is a combination of the upper 4 bits of 0c01 */
/* and bit 4 merged from S2650's flag output */
amp = ((state->m_0c03 & ENABLE_CTR1) == 0) ? 0 : (state->m_0c01 & 0xf0) >> 1;
if( cpu_get_reg(machine.device("maincpu"), S2650_FO) )
amp += 0x80;
/* calculate frequency for counter #1 */
/* bit 0..3 of 0c01 are ctr preset */
preset = (state->m_0c01 & 15) ^ 15;
if (preset)
state->m_freq1 = BASE_CTR1 / (preset + 1);
else amp = 0;
logerror("meadows ctr1 channel #%d preset:%3d freq:%5d amp:%d\n", state->m_channel, preset, state->m_freq1, amp);
samples->set_frequency(0, state->m_freq1 * sizeof(waveform)/2);
samples->set_volume(0,amp/255.0);
}
/* if a read from this address doesn't return the value it expects. */
static READ8_HANDLER( mrdo_SECRE_r )
{
UINT8 *RAM = space->machine().region("maincpu")->base();
return RAM[cpu_get_reg(&space->device(), Z80_HL)];
}
/* if a read from this address doesn't return the value it expects. */
int mrdo_SECRE_r(int offset)
{
unsigned char *RAM = memory_region(REGION_CPU1);
return RAM[ cpu_get_reg(Z80_HL) ];
}
static TIMER_CALLBACK( kaypro_timer_callback )
{
if (cpu_get_reg(machine.device("maincpu"), Z80_HALT))
cputag_set_input_line(machine, "maincpu", INPUT_LINE_NMI, ASSERT_LINE);
}
/* if a read from this address doesn't return the value it expects. */
static READ8_HANDLER( mrdo_SECRE_r )
{
UINT8 *RAM = memory_region(space->machine, "maincpu");
return RAM[cpu_get_reg(space->cpu, Z80_HL)];
}
static INTERRUPT_GEN( popeye_interrupt )
{
/* NMIs are enabled by the I register?? How can that be? */
if (cpu_get_reg(device, Z80_I) & 1) /* skyskipr: 0/1, popeye: 2/3 but also 0/1 */
device_set_input_line(device, INPUT_LINE_NMI, PULSE_LINE);
}
/* if a read from this address doesn't return the value it expects. */
int mrdo_SECRE_r(int offset)
{
unsigned char *RAM = Machine->memory_region[Machine->drv->cpu[0].memory_region];
return RAM[ cpu_get_reg(Z80_HL) ];
}
/*
draw the operator control panel (dynamic elements)
*/
static void tx0_draw_panel(running_machine &machine, bitmap_ind16 &bitmap)
{
int cm_sel, lr_sel;
int i;
/* column 1: registers, test accumulator, test buffer, toggle switch storage */
tx0_draw_multipleled(machine, bitmap, x_panel_col1b_offset+2*8, y_panel_pc_offset+8, cpu_get_reg(machine.device("maincpu"), TX0_PC), 16);
tx0_draw_multipleled(machine, bitmap, x_panel_col1b_offset+2*8, y_panel_mar_offset+8, cpu_get_reg(machine.device("maincpu"), TX0_MAR), 16);
tx0_draw_multipleled(machine, bitmap, x_panel_col1b_offset, y_panel_mbr_offset+8, cpu_get_reg(machine.device("maincpu"), TX0_MBR), 18);
tx0_draw_multipleled(machine, bitmap, x_panel_col1b_offset, y_panel_ac_offset+8, cpu_get_reg(machine.device("maincpu"), TX0_AC), 18);
tx0_draw_multipleled(machine, bitmap, x_panel_col1b_offset, y_panel_lr_offset+8, cpu_get_reg(machine.device("maincpu"), TX0_LR), 18);
tx0_draw_multipleled(machine, bitmap, x_panel_col1b_offset+4*8, y_panel_xr_offset+8, cpu_get_reg(machine.device("maincpu"), TX0_XR), 14);
tx0_draw_multipleswitch(machine, bitmap, x_panel_col1b_offset, y_panel_tbr_offset+8, cpu_get_reg(machine.device("maincpu"), TX0_TBR), 18);
tx0_draw_multipleswitch(machine, bitmap, x_panel_col1b_offset, y_panel_tac_offset+8, cpu_get_reg(machine.device("maincpu"), TX0_TAC), 18);
cm_sel = cpu_get_reg(machine.device("maincpu"), TX0_CM_SEL);
lr_sel = cpu_get_reg(machine.device("maincpu"), TX0_LR_SEL);
for (i=0; i<16; i++)
{
tx0_draw_switch(machine, bitmap, x_panel_col1a_offset+16, y_panel_tss_offset+8+i*8, (cm_sel >> i) & 1);
tx0_draw_multipleswitch(machine, bitmap, x_panel_col1a_offset+24, y_panel_tss_offset+8+i*8, cpu_get_reg(machine.device("maincpu"), TX0_TSS00+i), 18);
tx0_draw_switch(machine, bitmap, x_panel_col1a_offset+168, y_panel_tss_offset+8+i*8, (lr_sel >> i) & 1);
}
/* column 2: stop c0, stop c1, cm sel, 1-bit indicators, instr, flags */
tx0_draw_switch(machine, bitmap, x_panel_col2_offset, y_panel_stop_c0_offset, cpu_get_reg(machine.device("maincpu"), TX0_STOP_CYC0));
tx0_draw_switch(machine, bitmap, x_panel_col2_offset, y_panel_stop_c1_offset, cpu_get_reg(machine.device("maincpu"), TX0_STOP_CYC1));
tx0_draw_switch(machine, bitmap, x_panel_col2_offset, y_panel_gbl_cm_sel_offset, cpu_get_reg(machine.device("maincpu"), TX0_GBL_CM_SEL));
tx0_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_run_offset, cpu_get_reg(machine.device("maincpu"), TX0_RUN));
tx0_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_cycle1_offset, cpu_get_reg(machine.device("maincpu"), TX0_CYCLE) & 1);
tx0_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_cycle2_offset, cpu_get_reg(machine.device("maincpu"), TX0_CYCLE) & 2);
tx0_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_rim_offset, cpu_get_reg(machine.device("maincpu"), TX0_RIM));
tx0_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_ioh_offset, cpu_get_reg(machine.device("maincpu"), TX0_IOH));
tx0_draw_led(machine, bitmap, x_panel_col2_offset, y_panel_ios_offset, cpu_get_reg(machine.device("maincpu"), TX0_IOS));
tx0_draw_multipleled(machine, bitmap, x_panel_col2_offset, y_panel_ir_offset+8, cpu_get_reg(machine.device("maincpu"), TX0_IR), 5);
tx0_draw_multipleled(machine, bitmap, x_panel_col2_offset, y_panel_pf_offset+8, cpu_get_reg(machine.device("maincpu"), TX0_PF), 6);
}
