void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
{
struct platform_device *pdev = NULL;
if (WARN_ON(cpu_is_davinci_dm646x()))
return;
/* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too;
* for example if MMCSD1 is used for SDIO, maybe DAT2 is unused.
*
* FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are
* not handled right here ...
*/
switch (module) {
case 1:
if (cpu_is_davinci_dm365()) {
void __iomem *pupdctl1 =
IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c);
/* Configure pull down control */
__raw_writel((__raw_readl(pupdctl1) & ~0xfc0),
pupdctl1);
mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
SZ_4K - 1;
mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1;
} else
break;
pdev = &davinci_mmcsd1_device;
break;
case 0:
if (cpu_is_davinci_dm365()) {
mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
}
pdev = &davinci_mmcsd0_device;
break;
}
if (WARN_ON(!pdev))
return;
pdev->dev.platform_data = config;
platform_device_register(pdev);
}
static inline void phy_on(void)
{
u32 phy_ctrl = __raw_readl(USB_PHY_CTRL);
/* power everything up; start the on-chip PHY and its PLL */
phy_ctrl &= ~(USBPHY_OSCPDWN | USBPHY_OTGPDWN | USBPHY_PHYPDWN);
phy_ctrl |= USBPHY_SESNDEN | USBPHY_VBDTCTEN | USBPHY_PHYPLLON;
if (cpu_is_davinci_dm646x()) {
phy_ctrl |= USBPHY_NDATAPOL | USBPHY_SESSION_VBUS;
phy_ctrl |= is_peripheral_enabled() ? USBPHY_PERI_USBID :
phy_ctrl;
phy_ctrl &= ~USBPHY_VBDTCTEN;
}
if (cpu_is_davinci_dm365()) {
/*
* DM365 PHYCLKFREQ field [15:12] is set to 2
* to get clock from 24MHz crystal
*/
phy_ctrl |= USBPHY_CLKFREQ_24MHZ;
/*phy_ctrl &= ~USBPHY_PHYPDWN;*/
}
__raw_writel(phy_ctrl, USB_PHY_CTRL);
/* wait for PLL to lock before proceeding */
while ((__raw_readl(USB_PHY_CTRL) & USBPHY_PHYCLKGD) == 0)
cpu_relax();
}
static int __init dm365_init_devices(void)
{
if (!cpu_is_davinci_dm365())
return 0;
davinci_cfg_reg(DM365_INT_EDMA_CC);
platform_device_register(&dm365_edma_device);
platform_device_register(&dm365_emac_device);
/*
* setup Mux configuration for vpfe input and register
* vpfe capture platform device
*/
platform_device_register(&dm365_vpss_device);
platform_device_register(&dm365_ipipeif_dev);
platform_device_register(&dm365_isif_dev);
platform_device_register(&vpfe_capture_dev);
/* Register OSD device */
platform_device_register(&dm365_osd_dev);
/* Register VENC device */
platform_device_register(&dm365_venc_dev);
return 0;
}
void __init davinci_mux_init(void)
{
const struct pin_config *table;
unsigned size;
if (cpu_is_davinci_dm365()) {
davinci_pins = dm365_pins;
davinci_num_pins = ARRAY_SIZE(dm365_pins);
table = davinci_dm365_pinmux;
size = ARRAY_SIZE(davinci_dm365_pinmux);
} else if (cpu_is_davinci_dm355()) {
davinci_pins = dm355_pins;
davinci_num_pins = ARRAY_SIZE(dm355_pins);
table = davinci_dm355_pinmux;
size = ARRAY_SIZE(davinci_dm355_pinmux);
} else if (cpu_is_davinci_dm6467()) {
davinci_pins = dm646x_pins;
davinci_num_pins = ARRAY_SIZE(dm646x_pins);
table = davinci_dm646x_pinmux;
size = ARRAY_SIZE(davinci_dm646x_pinmux);
} else if (cpu_is_davinci_dm644x()) {
davinci_pins = dm644x_pins;
davinci_num_pins = ARRAY_SIZE(dm644x_pins);
table = davinci_dm644x_pinmux;
size = ARRAY_SIZE(davinci_dm644x_pinmux);
} else {
if (!cpu_is_davinci_dm357())
BUG();
davinci_pins = dm357_pins;
davinci_num_pins = ARRAY_SIZE(dm357_pins);
table = davinci_dm357_pinmux;
size = ARRAY_SIZE(davinci_dm357_pinmux);
}
davinci_mux_register(table, size, davinci_get_pins, pinmux_in_use);
}
int mt9xxx_set_input_mux(unsigned char channel)
{
int err = 0;
u8 val[2];
u32 val1;
val[0] = 8;
if (cpu_is_davinci_dm644x())
return err;
val[1] = 0x80;
if (cpu_is_davinci_dm355()) {
//Logi err = davinci_i2c_write(2, val, MSP430_I2C_ADDR);
if (err)
return err;
} else if (cpu_is_davinci_dm365()) {
/* Drive TVP5146 Reset to low */
tvp514x_hw_reset(0);
/* drive the sensor reset line high */
image_sensor_hw_reset(1);
/* Set Mux for image sensor */
val1 = cpld_read(DM365_CPLD_REGISTER3);
val1 &= ~DM365_VIDEO_MUX_MASK;
val1 |= DM365_SENSOR_SEL;
cpld_write(val1, DM365_CPLD_REGISTER3);
}
/* For image sensor we need to program I2C switch
* PCA9543A
*/
//Logi val[0] = 0x01;
//Logi davinci_i2c_write(1, val, PCA9543A_I2C_ADDR);
return 0;
}
/* type = 0 for TVP5146 and 1 for Image sensor */
int tvp514x_set_input_mux(unsigned char channel)
{
int err = 0;
u8 val[2];
u32 val1;
val[0] = 8;
val[1] = 0x0;
if (cpu_is_davinci_dm644x())
return err;
/* Logi if (cpu_is_davinci_dm355())
err = davinci_i2c_write(2, val, MSP430_I2C_ADDR);
else */if (cpu_is_davinci_dm365()) {
/* drive the sensor reset line low */
image_sensor_hw_reset(0);
/* set tvp5146 reset line high */
tvp514x_hw_reset(1);
/* Set Mux for TVP5146 */
val1 = cpld_read(DM365_CPLD_REGISTER3);
val1 &= ~DM365_VIDEO_MUX_MASK;
val1 |= DM365_TVP5146_SEL;
cpld_write(val1, DM365_CPLD_REGISTER3);
}
return err;
}
/* Om DM365, Imager and TVP5146 I2C address collide. So we need to
* keep imager on reset when working with tvp5146 and vice-versa
* This function use GIO40 to act as reset to imager
*/
void image_sensor_hw_reset(int state)
{
u32 val1;
if (cpu_is_davinci_dm365()) {
val1 = cpld_read(DM365_CPLD_REGISTER3);
val1 |= DM365_IMAGER_RST_MASK;
cpld_write(val1, DM365_CPLD_REGISTER3);
/* CPLD to Route GPIO to Imager Reset line */
val1 = cpld_read(DM365_CPLD_REGISTER16);
val1 &= ~0x40404040;
cpld_write(val1, DM365_CPLD_REGISTER16);
val1 = cpld_read(DM365_CPLD_REGISTER18);
val1 |= 0x20202020;
cpld_write(val1, DM365_CPLD_REGISTER18);
val1 = cpld_read(DM365_CPLD_REGISTER18);
val1 &= ~0x01010101;
cpld_write(val1, DM365_CPLD_REGISTER18);
#ifndef CONFIG_MTD_CFI /* When NOR flash is use and at 16-bit access mode. GPIO 40 is used as address bus */
/* Pin mux to use GPIO40 */
davinci_cfg_reg(DM365_GPIO40, PINMUX_RESV);
/* Configure GPIO40 to be output and hight */
if (state)
gpio_direction_output(40, 1);
else
gpio_direction_output(40, 0);
#endif
}
}
static void davinci_source_power(struct musb *musb, int is_on, int immediate)
{
#if defined(CONFIG_MACH_DAVINCI_EVM) || defined(CONFIG_MACH_DAVINCI_DM6467_EVM)
if (is_on)
is_on = 1;
if (vbus_state == is_on)
return;
vbus_state = !is_on; /* 0/1 vs "-1 == unknown/init" */
if (machine_is_davinci_evm() || machine_is_davinci_dm6467_evm()) {
static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
if (immediate) {
if (machine_is_davinci_evm())
gpio_set_value_cansleep(GPIO_nVBUS_DRV,
vbus_state);
if (machine_is_davinci_dm6467_evm())
usb_vbus_control(vbus_state);
} else
schedule_work(&evm_vbus_work);
}
if (immediate)
vbus_state = is_on;
#endif
if (cpu_is_davinci_dm365())
gpio_set_value(33, is_on);
}
void davinci_gpio_init(void)
{
struct gpio_bank *gpio_bank;
#if defined(CONFIG_ARCH_DAVINCI644x) || defined(CONFIG_ARCH_DAVINCI_DM357)
if (cpu_is_davinci_dm644x() || cpu_is_davinci_dm357())
gpio_bank = &gpio_bank_dm6446;
#endif
#ifdef CONFIG_ARCH_DAVINCI_DM355
if (cpu_is_davinci_dm355())
gpio_bank = &gpio_bank_dm355;
#endif
#ifdef CONFIG_ARCH_DAVINCI_DM365
if (cpu_is_davinci_dm365())
gpio_bank = &gpio_bank_dm365;
#endif
#ifdef CONFIG_ARCH_DAVINCI_DM646x
if (cpu_is_davinci_dm6467())
gpio_bank = &gpio_bank_dm646x;
#endif
if (!gpio_bank)
BUG();
davinci_gpio_irq_setup(gpio_bank);
}
int vpfe_resizer_init(struct vpfe_resizer_device *vpfe_rsz,
struct platform_device *pdev)
{
struct v4l2_subdev *resizer = &vpfe_rsz->subdev;
struct media_pad *pads = &vpfe_rsz->pads[0];
struct media_entity *me = &resizer->entity;
struct imp_logical_channel *channel = &vpfe_rsz->channel;
int ret;
if (cpu_is_davinci_dm365() || cpu_is_davinci_dm355()) {
vpfe_rsz->imp_hw_if = imp_get_hw_if();
if (ISNULL(vpfe_rsz->imp_hw_if))
return -1;
} else
return -1;
vpfe_rsz->video_in.ops = &video_in_ops;
vpfe_rsz->video_out.ops = &video_out1_ops;
/*TODO:enable with rsz-b*/
v4l2_subdev_init(resizer, &resizer_v4l2_ops);
strlcpy(resizer->name, "DAVINCI RESIZER", sizeof(resizer->name));
resizer->grp_id = 1 << 16; /* group ID for davinci subdevs */
v4l2_set_subdevdata(resizer, vpfe_rsz);
resizer->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
pads[RESIZER_PAD_SINK].flags = MEDIA_PAD_FL_INPUT;
pads[RESIZER_PAD_SOURCE].flags = MEDIA_PAD_FL_OUTPUT;
vpfe_rsz->input = RESIZER_INPUT_NONE;
vpfe_rsz->output = RESIZER_OUTPUT_NONE;
channel->type = IMP_RESIZER;
channel->config_state = STATE_NOT_CONFIGURED;
me->ops = &resizer_media_ops;
ret = media_entity_init(me, RESIZER_PADS_NUM, pads, 0);
if (ret)
return ret;
vpfe_rsz->video_in.type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
ret = vpfe_video_init(&vpfe_rsz->video_in, "RSZ");
if (ret) {
printk(KERN_ERR "failed to init RSZ video-in device\n");
return ret;
}
vpfe_rsz->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
ret = vpfe_video_init(&vpfe_rsz->video_out, "RSZ");
if (ret) {
printk(KERN_ERR "failed to init RSZ video-out device\n");
return ret;
}
return 0;
}
static int __init dm365_init_devices(void)
{
if (!cpu_is_davinci_dm365())
return 0;
davinci_cfg_reg(DM365_INT_EDMA_CC);
platform_device_register(&dm365_edma_device);
platform_device_register(&dm365_emac_device);
return 0;
}
/* For DM365, we need set tvp5146 reset line low for
* working with sensor. This API is used for this
* purpose state is 0 for reset low and 1 for high
*/
void tvp514x_hw_reset(int state)
{
u32 val1;
if (cpu_is_davinci_dm365()) {
val1 = cpld_read(DM365_CPLD_REGISTER19);
if (state)
val1 &= ~DM365_TVP5146_RST_MASK;
else
val1 |= 0x01010101;
cpld_write(val1, DM365_CPLD_REGISTER19);
}
}
struct tvp514x_evm_chan *tvp514x_get_evm_chan_config(unsigned char channel)
{
struct tvp514x_evm_chan *chan_cfg = NULL;
if (channel == 0) {
if (cpu_is_davinci_dm365())
chan_cfg =
&dm365_tvp514x_evm_chan_config.channels[channel];
else
chan_cfg =
&dmxxx_tvp514x_evm_chan_config.channels[channel];
}
return chan_cfg;
}
static irqreturn_t imp_common_isr(int irq, void *device_id,
struct pt_regs *regs)
{
u32 val;
if (cpu_is_davinci_dm365()) {
val = davinci_readl(0x1c7000c);
if (val & 0x8000) {
davinci_writel(0x8000, 0x1c7000c);
complete(&(imp_serializer_info.sem_isr));
}
} else
complete(&(imp_serializer_info.sem_isr));
return IRQ_HANDLED;
}
static int __init dm365_init_devices(void)
{
if (!cpu_is_davinci_dm365())
return 0;
davinci_cfg_reg(DM365_INT_EDMA_CC);
platform_device_register(&dm365_edma_device);
platform_device_register(&dm365_emac_device);
/* Add isif clock alias */
clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL);
platform_device_register(&dm365_vpss_device);
platform_device_register(&dm365_isif_dev);
platform_device_register(&vpfe_capture_dev);
return 0;
}
static int __init dm365_init_devices(void)
{
int ret = 0;
if (!cpu_is_davinci_dm365())
return 0;
davinci_cfg_reg(DM365_INT_EDMA_CC);
platform_device_register(&dm365_edma_device);
platform_device_register(&dm365_mdio_device);
platform_device_register(&dm365_emac_device);
ret = davinci_init_wdt();
if (ret)
pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
return ret;
}
void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
{
struct platform_device *pdev = NULL;
if (WARN_ON(cpu_is_davinci_dm646x()))
return;
/* REVISIT: update PINMUX, ARM_IRQMUX, and EDMA_EVTMUX here too;
* for example if MMCSD1 is used for SDIO, maybe DAT2 is unused.
*
* FIXME dm6441 (no MMC/SD), dm357 (one), and dm335 (two) are
* not handled right here ...
*/
switch (module) {
case 1:
if (cpu_is_davinci_dm355()) {
/* REVISIT we may not need all these pins if e.g. this
* is a hard-wired SDIO device...
*/
davinci_cfg_reg(DM355_SD1_CMD);
davinci_cfg_reg(DM355_SD1_CLK);
davinci_cfg_reg(DM355_SD1_DATA0);
davinci_cfg_reg(DM355_SD1_DATA1);
davinci_cfg_reg(DM355_SD1_DATA2);
davinci_cfg_reg(DM355_SD1_DATA3);
} else if (cpu_is_davinci_dm365()) {
/* Configure pull down control */
unsigned v;
v = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
__raw_writel(v & ~0xfc0,
DAVINCI_SYSMOD_VIRT(SYSMOD_PUPDCTL1));
mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
SZ_4K - 1;
mmcsd1_resources[2].start = IRQ_DM365_SDIOINT1;
davinci_mmcsd1_device.name = "da830-mmc";
} else
break;
pdev = &davinci_mmcsd1_device;
break;
case 0:
if (cpu_is_davinci_dm355()) {
mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0;
/* expose all 6 MMC0 signals: CLK, CMD, DATA[0..3] */
davinci_cfg_reg(DM355_MMCSD0);
/* enable RX EDMA */
davinci_cfg_reg(DM355_EVT26_MMC0_RX);
} else if (cpu_is_davinci_dm365()) {
mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
davinci_mmcsd0_device.name = "da830-mmc";
} else if (cpu_is_davinci_dm644x()) {
/* REVISIT: should this be in board-init code? */
/* Power-on 3.3V IO cells */
__raw_writel(0,
DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
/*Set up the pull regiter for MMC */
davinci_cfg_reg(DM644X_MSTK);
}
pdev = &davinci_mmcsd0_device;
break;
}
if (WARN_ON(!pdev))
return;
pdev->dev.platform_data = config;
platform_device_register(pdev);
}
int __init dma_init(void)
{
struct dma_init_info info;
info.edma_num_dmach = EDMA_DAVINCI_NUM_DMACH;
info.edma_num_tcc = EDMA_DAVINCI_NUM_TCC;
info.cc_reg0_int = IRQ_CCINT0;
info.cc_error_int = IRQ_CCERRINT;
if (cpu_is_davinci_dm6467()) {
info.edma_num_evtq = EDMA_DM646X_NUM_EVQUE;
info.edma_num_tc = EDMA_DM646X_NUM_TC;
info.edma_num_param = EDMA_DM646X_NUM_PARAMENTRY;
info.edma_chmap_exist = EDMA_DM646X_CHMAP_EXIST;
info.edmatc_base_addrs = dm646x_edmatc_base_addrs;
info.edma2event_map = dm646x_dma_ch_hw_event_map;
info.edma_channels_arm = dm646x_edma_channels_arm;
info.qdma_channels_arm = dm646x_qdma_channels_arm;
info.param_entry_arm = dm646x_param_entry_arm;
info.tcc_arm = dm646x_tcc_arm;
info.param_entry_reserved = dm646x_param_entry_reserved;
info.q_pri = dm646x_queue_priority_mapping;
info.q_tc = dm646x_queue_tc_mapping;
info.q_wm = dm646x_queue_watermark_level;
info.tc_error_int = dm646x_tc_error_int;
} else if (cpu_is_davinci_dm355()) {
info.edma_num_evtq = EDMA_DM355_NUM_EVQUE;
info.edma_num_tc = EDMA_DM355_NUM_TC;
info.edma_num_param = EDMA_DM355_NUM_PARAMENTRY;
info.edma_chmap_exist = EDMA_DM355_CHMAP_EXIST;
info.edmatc_base_addrs = dm355_edmatc_base_addrs;
info.edma2event_map = dm355_dma_ch_hw_event_map;
info.edma_channels_arm = dm355_edma_channels_arm;
info.qdma_channels_arm = dm355_qdma_channels_arm;
info.param_entry_arm = dm355_param_entry_arm;
info.tcc_arm = dm355_tcc_arm;
info.param_entry_reserved = dm355_param_entry_reserved;
info.q_pri = dm355_queue_priority_mapping;
info.q_tc = dm355_queue_tc_mapping;
info.q_wm = dm355_queue_watermark_level;
info.tc_error_int = dm355_tc_error_int;
} else if (cpu_is_davinci_dm365()) {
info.edma_num_evtq = EDMA_DM365_NUM_EVQUE;
info.edma_num_tc = EDMA_DM365_NUM_TC;
info.edma_num_param = EDMA_DM365_NUM_PARAMENTRY;
info.edma_chmap_exist = EDMA_DM365_CHMAP_EXIST;
info.edmatc_base_addrs = dm365_edmatc_base_addrs;
info.edma2event_map = dm365_dma_ch_hw_event_map;
info.edma_channels_arm = dm365_edma_channels_arm;
info.qdma_channels_arm = dm365_qdma_channels_arm;
info.param_entry_arm = dm365_param_entry_arm;
info.tcc_arm = dm365_tcc_arm;
info.param_entry_reserved = dm365_param_entry_reserved;
info.q_pri = dm365_queue_priority_mapping;
info.q_tc = dm365_queue_tc_mapping;
info.q_wm = dm365_queue_watermark_level;
info.tc_error_int = dm365_tc_error_int;
} else { /* Must be dm6446 or dm357 */
if (!cpu_is_davinci_dm644x() && !cpu_is_davinci_dm357())
BUG();
info.edma_num_evtq = EDMA_DM644X_NUM_EVQUE;
info.edma_num_tc = EDMA_DM644X_NUM_TC;
info.edma_num_param = EDMA_DM644X_NUM_PARAMENTRY;
info.edma_chmap_exist = EDMA_DM644X_CHMAP_EXIST;
info.edmatc_base_addrs = dm644x_edmatc_base_addrs;
info.edma2event_map = dm644x_dma_ch_hw_event_map;
info.edma_channels_arm = dm644x_edma_channels_arm;
info.qdma_channels_arm = dm644x_qdma_channels_arm;
info.param_entry_arm = dm644x_param_entry_arm;
info.tcc_arm = dm644x_tcc_arm;
info.param_entry_reserved = dm644x_param_entry_reserved;
info.q_pri = dm644x_queue_priority_mapping;
info.q_tc = dm644x_queue_tc_mapping;
info.q_wm = dm644x_queue_watermark_level;
info.tc_error_int = dm644x_tc_error_int;
}
return davinci_dma_init(&info);
}
void __init davinci_setup_mmc(int module, struct davinci_mmc_config *config)
{
struct platform_device *pdev = NULL;
if (WARN_ON(cpu_is_davinci_dm646x()))
return;
switch (module) {
case 1:
if (cpu_is_davinci_dm355()) {
davinci_cfg_reg(DM355_SD1_CMD);
davinci_cfg_reg(DM355_SD1_CLK);
davinci_cfg_reg(DM355_SD1_DATA0);
davinci_cfg_reg(DM355_SD1_DATA1);
davinci_cfg_reg(DM355_SD1_DATA2);
davinci_cfg_reg(DM355_SD1_DATA3);
} else if (cpu_is_davinci_dm365()) {
void __iomem *pupdctl1 =
IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE + 0x7c);
__raw_writel((__raw_readl(pupdctl1) & ~0x400),
pupdctl1);
mmcsd1_resources[0].start = DM365_MMCSD1_BASE;
mmcsd1_resources[0].end = DM365_MMCSD1_BASE +
SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM365_SDIOINT1;
} else
break;
pdev = &davinci_mmcsd1_device;
break;
case 0:
if (cpu_is_davinci_dm355()) {
mmcsd0_resources[0].start = DM355_MMCSD0_BASE;
mmcsd0_resources[0].end = DM355_MMCSD0_BASE + SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM355_SDIOINT0;
davinci_cfg_reg(DM355_MMCSD0);
davinci_cfg_reg(DM355_EVT26_MMC0_RX);
} else if (cpu_is_davinci_dm365()) {
mmcsd0_resources[0].start = DM365_MMCSD0_BASE;
mmcsd0_resources[0].end = DM365_MMCSD0_BASE +
SZ_4K - 1;
mmcsd0_resources[2].start = IRQ_DM365_SDIOINT0;
} else if (cpu_is_davinci_dm644x()) {
void __iomem *base =
IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
__raw_writel(0, base + DM64XX_VDD3P3V_PWDN);
davinci_cfg_reg(DM644X_MSTK);
}
pdev = &davinci_mmcsd0_device;
break;
}
if (WARN_ON(!pdev))
return;
pdev->dev.platform_data = config;
platform_device_register(pdev);
}
