void __init imx_src_init(void) { struct device_node *np; u32 val; np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src"); if (!np) return; src_base = of_iomap(np, 0); WARN_ON(!src_base); imx_reset_controller.of_node = np; if (IS_ENABLED(CONFIG_RESET_CONTROLLER)) reset_controller_register(&imx_reset_controller); /* * force warm reset sources to generate cold reset * for a more reliable restart */ spin_lock(&scr_lock); val = readl_relaxed(src_base + SRC_SCR); /* bit 4 is m4c_non_sclr_rst on i.MX6SX */ if (cpu_is_imx6sx() && ((val & (1 << BP_SRC_SCR_SW_OPEN_VG_RST)) == 0)) m4_is_enabled = true; else m4_is_enabled = false; val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); writel_relaxed(val, src_base + SRC_SCR); spin_unlock(&scr_lock); }
static int __init imx_amp_power_init(void) { int i; void __iomem *shared_mem_base; if (!(imx_src_is_m4_enabled() && cpu_is_imx6sx())) return 0; amp_power_mutex = imx_sema4_mutex_create(0, MCC_POWER_SHMEM_NUMBER); shared_mem_base = ioremap_nocache(shared_mem_paddr, shared_mem_size); if (!amp_power_mutex) { pr_err("Failed to create sema4 mutex!\n"); return 0; } shared_mem = (struct imx_shared_mem *)shared_mem_base; for (i = 0; i < ARRAY_SIZE(clks_shared); i++) { shared_mem->imx_clk[i].self = clks[clks_shared[i]]; shared_mem->imx_clk[i].ca9_enabled = 1; pr_debug("%d: name %s, addr 0x%x\n", i, __clk_get_name(shared_mem->imx_clk[i].self), (u32)&(shared_mem->imx_clk[i])); } /* enable amp power management */ shared_mem->ca9_valid = SHARED_MEM_MAGIC_NUMBER; pr_info("A9-M4 sema4 num %d, A9-M4 magic number 0x%x - 0x%x.\n", amp_power_mutex->gate_num, shared_mem->ca9_valid, shared_mem->cm4_valid); return 0; }
static void reduce_bus_freq(void) { if (cpu_is_imx6()) clk_prepare_enable(pll3); if (audio_bus_count && (low_bus_freq_mode || ultra_low_bus_freq_mode)) busfreq_notify(LOW_BUSFREQ_EXIT); else if (!audio_bus_count) busfreq_notify(LOW_BUSFREQ_ENTER); if (cpu_is_imx7d()) enter_lpm_imx7d(); else if (cpu_is_imx6sl()) enter_lpm_imx6sl(); else if (cpu_is_imx6sx() || cpu_is_imx6ul()) enter_lpm_imx6_up(); else { if (cpu_is_imx6dl()) /* Set axi to periph_clk */ imx_clk_set_parent(axi_sel_clk, periph_clk); if (audio_bus_count) { /* Need to ensure that PLL2_PFD_400M is kept ON. */ clk_prepare_enable(pll2_400); update_ddr_freq_imx_smp(LOW_AUDIO_CLK); /* Make sure periph clk's parent also got updated */ imx_clk_set_parent(periph_clk2_sel, pll3); imx_clk_set_parent(periph_pre_clk, pll2_200); imx_clk_set_parent(periph_clk, periph_pre_clk); audio_bus_freq_mode = 1; low_bus_freq_mode = 0; cur_bus_freq_mode = BUS_FREQ_AUDIO; } else { update_ddr_freq_imx_smp(LPAPM_CLK); /* Make sure periph clk's parent also got updated */ imx_clk_set_parent(periph_clk2_sel, osc_clk); /* Set periph_clk parent to OSC via periph_clk2_sel */ imx_clk_set_parent(periph_clk, periph_clk2); if (audio_bus_freq_mode) clk_disable_unprepare(pll2_400); low_bus_freq_mode = 1; audio_bus_freq_mode = 0; cur_bus_freq_mode = BUS_FREQ_LOW; } } if (cpu_is_imx6()) clk_disable_unprepare(pll3); med_bus_freq_mode = 0; high_bus_freq_mode = 0; if (audio_bus_freq_mode) dev_dbg(busfreq_dev, "Bus freq set to audio mode. Count:\ high %d, med %d, audio %d\n", high_bus_count, med_bus_count, audio_bus_count); if (low_bus_freq_mode) dev_dbg(busfreq_dev, "Bus freq set to low mode. Count:\ high %d, med %d, audio %d\n", high_bus_count, med_bus_count, audio_bus_count); }
/* * enter_lpm_imx6_up and exit_lpm_imx6_up is used by * i.MX6SX/i.MX6UL for entering and exiting lpm mode. */ static void enter_lpm_imx6_up(void) { if (cpu_is_imx6sx() && imx_src_is_m4_enabled()) if (!check_m4_sleep()) pr_err("M4 is NOT in sleep!!!\n"); /* set periph_clk2 to source from OSC for periph */ imx_clk_set_parent(periph_clk2_sel, osc_clk); imx_clk_set_parent(periph_clk, periph_clk2); /* set ahb/ocram to 24MHz */ imx_clk_set_rate(ahb_clk, LPAPM_CLK); imx_clk_set_rate(ocram_clk, LPAPM_CLK); if (audio_bus_count) { /* Need to ensure that PLL2_PFD_400M is kept ON. */ clk_prepare_enable(pll2_400); if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) update_ddr_freq_imx6_up(LOW_AUDIO_CLK); else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) update_lpddr2_freq(HIGH_AUDIO_CLK); imx_clk_set_parent(periph2_clk2_sel, pll3); imx_clk_set_parent(periph2_pre_clk, pll2_400); imx_clk_set_parent(periph2_clk, periph2_pre_clk); /* * As periph2_clk's parent is not changed from * high mode to audio mode, so clk framework * will not update its children's freq, but we * change the mmdc's podf in asm code, so here * need to update mmdc rate to make sure clk * tree is right, although it will not do any * change to hardware. */ if (high_bus_freq_mode) { if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) imx_clk_set_rate(mmdc_clk, LOW_AUDIO_CLK); else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) imx_clk_set_rate(mmdc_clk, HIGH_AUDIO_CLK); } audio_bus_freq_mode = 1; low_bus_freq_mode = 0; cur_bus_freq_mode = BUS_FREQ_AUDIO; } else { if (ddr_type == MMDC_MDMISC_DDR_TYPE_DDR3) update_ddr_freq_imx6_up(LPAPM_CLK); else if (ddr_type == MMDC_MDMISC_DDR_TYPE_LPDDR2) update_lpddr2_freq(LPAPM_CLK); imx_clk_set_parent(periph2_clk2_sel, osc_clk); imx_clk_set_parent(periph2_clk, periph2_clk2); if (audio_bus_freq_mode) clk_disable_unprepare(pll2_400); low_bus_freq_mode = 1; audio_bus_freq_mode = 0; cur_bus_freq_mode = BUS_FREQ_LOW; } }
static void __init _mxc_timer_init(int irq, struct clk *clk_per, struct clk *clk_ipg) { uint32_t tctl_val; if (IS_ERR(clk_per)) { pr_err("i.MX timer: unable to get clk\n"); return; } if (!IS_ERR(clk_ipg)) clk_prepare_enable(clk_ipg); clk_prepare_enable(clk_per); /* * Initialise to a known state (all timers off, and timing reset) */ __raw_writel(0, timer_base + MXC_TCTL); __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ if (timer_is_v2()) { tctl_val = V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; if (clk_get_rate(clk_per) == V2_TIMER_RATE_OSC_DIV8) { tctl_val |= V2_TCTL_CLK_OSC_DIV8; if (cpu_is_imx6dl() || cpu_is_imx6sll() || cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx7d()) { /* 24 / 8 = 3 MHz */ __raw_writel(7 << V2_TPRER_PRE24M, timer_base + MXC_TPRER); tctl_val |= V2_TCTL_24MEN; } } else { tctl_val |= V2_TCTL_CLK_PER; } } else { tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; } __raw_writel(tctl_val, timer_base + MXC_TCTL); /* init and register the timer to the framework */ mxc_clocksource_init(clk_per); mxc_clockevent_init(clk_per); /* Make irqs happen */ setup_irq(irq, &mxc_timer_irq); }
int init_mmdc_lpddr2_settings(struct platform_device *busfreq_pdev) { unsigned long ddr_code_size; busfreq_dev = &busfreq_pdev->dev; ddr_code_size = (&imx6_lpddr2_freq_change_end -&imx6_lpddr2_freq_change_start) *4; if (cpu_is_imx6sl()) mx6_change_lpddr2_freq = (void *)fncpy( (void *)ddr_freq_change_iram_base, &mx6_lpddr2_freq_change, ddr_code_size); else if (cpu_is_imx6sx() || cpu_is_imx6ul()) mx6_change_lpddr2_freq = (void *)fncpy( (void *)ddr_freq_change_iram_base, &imx6_up_lpddr2_freq_change, ddr_code_size); curr_ddr_rate = ddr_normal_rate; return 0; }
/* * Reset the system. It is called by machine_restart(). */ void mxc_restart(char mode, const char *cmd) { unsigned int wcr_enable; arch_reset_special_mode(mode, cmd); if (wdog_clk) clk_enable(wdog_clk); if (cpu_is_mx1()) wcr_enable = (1 << 0); /* * Some i.MX6 boards use WDOG2 to reset external pmic in bypass mode, * so do WDOG2 reset here. Do not set SRS, since we will * trigger external POR later. Use WDOG1 to reset in ldo-enable * mode. You can set it by "fsl,wdog-reset" in dts. * For i.MX6SX we have to trigger wdog-reset to reset QSPI-NOR flash to * workaround qspi-nor reboot issue whatever ldo-bypass or not. */ else if ((wdog_source == 2 && (cpu_is_imx6q() || cpu_is_imx6dl() || cpu_is_imx6sl())) || cpu_is_imx6sx()) wcr_enable = 0x14; else wcr_enable = (1 << 2); /* Assert SRS signal */ __raw_writew(wcr_enable, wdog_base); /* write twice to ensure the request will not get ignored */ __raw_writew(wcr_enable, wdog_base); /* wait for reset to assert... */ mdelay(500); pr_err("%s: Watchdog reset failed to assert reset\n", __func__); /* delay to allow the serial port to show the message */ mdelay(50); /* we'll take a jump through zero as a poor second */ soft_restart(0); }
/* * Set the DDR to either 528MHz or 400MHz for iMX6qd * or 400MHz for iMX6dl. */ static int set_high_bus_freq(int high_bus_freq) { struct clk *periph_clk_parent; if (bus_freq_scaling_initialized && bus_freq_scaling_is_active) cancel_delayed_work_sync(&low_bus_freq_handler); if (busfreq_suspended) return 0; if (cpu_is_imx6q()) periph_clk_parent = pll2_bus; else periph_clk_parent = pll2_400; if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active) return 0; if (high_bus_freq_mode) return 0; /* medium bus freq is only supported for MX6DQ */ if (med_bus_freq_mode && !high_bus_freq) return 0; if (low_bus_freq_mode || ultra_low_bus_freq_mode) busfreq_notify(LOW_BUSFREQ_EXIT); if (cpu_is_imx6()) clk_prepare_enable(pll3); if (cpu_is_imx7d()) exit_lpm_imx7d(); else if (cpu_is_imx6sl()) exit_lpm_imx6sl(); else if (cpu_is_imx6sx() || cpu_is_imx6ul()) exit_lpm_imx6_up(); else { if (high_bus_freq) { clk_prepare_enable(pll2_400); update_ddr_freq_imx_smp(ddr_normal_rate); /* Make sure periph clk's parent also got updated */ imx_clk_set_parent(periph_clk2_sel, pll3); imx_clk_set_parent(periph_pre_clk, periph_clk_parent); imx_clk_set_parent(periph_clk, periph_pre_clk); if (cpu_is_imx6dl()) { /* Set axi to pll3_pfd1_540m */ imx_clk_set_parent(axi_alt_sel_clk, pll3_pfd1_540m); imx_clk_set_parent(axi_sel_clk, axi_alt_sel_clk); } clk_disable_unprepare(pll2_400); } else { update_ddr_freq_imx_smp(ddr_med_rate); /* Make sure periph clk's parent also got updated */ imx_clk_set_parent(periph_clk2_sel, pll3); imx_clk_set_parent(periph_pre_clk, pll2_400); imx_clk_set_parent(periph_clk, periph_pre_clk); } if (audio_bus_freq_mode) clk_disable_unprepare(pll2_400); } high_bus_freq_mode = 1; med_bus_freq_mode = 0; low_bus_freq_mode = 0; audio_bus_freq_mode = 0; cur_bus_freq_mode = BUS_FREQ_HIGH; if (cpu_is_imx6()) clk_disable_unprepare(pll3); if (high_bus_freq_mode) dev_dbg(busfreq_dev, "Bus freq set to high mode. Count:\ high %d, med %d, audio %d\n", high_bus_count, med_bus_count, audio_bus_count); if (med_bus_freq_mode) dev_dbg(busfreq_dev, "Bus freq set to med mode. Count:\ high %d, med %d, audio %d\n", high_bus_count, med_bus_count, audio_bus_count); return 0; }