static int __init mxc_init_uart(void) { if (cpu_is_mx53() || cpu_is_mx50()) { mxc_uart_resources1[0].start -= 0x20000000; mxc_uart_resources1[0].end -= 0x20000000; mxc_uart_resources2[0].start -= 0x20000000; mxc_uart_resources2[0].end -= 0x20000000; mxc_uart_resources3[0].start -= 0x20000000; mxc_uart_resources3[0].end -= 0x20000000; mxc_uart_resources4[0].start -= 0x20000000; mxc_uart_resources4[0].end -= 0x20000000; mxc_uart_resources5[0].start -= 0x20000000; mxc_uart_resources5[0].end -= 0x20000000; } /* Register all the MXC UART platform device structures */ /* For Tequila, register only uart1, this will help PM */ platform_device_register(&mxc_uart_device1); if (!mx50_board_is(BOARD_ID_TEQUILA)) { platform_device_register(&mxc_uart_device2); platform_device_register(&mxc_uart_device3); platform_device_register(&mxc_uart_device4); if (cpu_is_mx53()) { platform_device_register(&mxc_uart_device5); } } return 0; }
static int fsl_usb_host_init_ext(struct platform_device *pdev) { int ret = 0; struct clk *usb_clk; usb_clk = clk_get(NULL, "usboh3_clk"); clk_enable(usb_clk); clk_put(usb_clk); /* on mx53, there is a hardware limitation that when switch the host2's clk mode * ,usb phy1 clk must be on, after finish switching this clk can be off */ if (cpu_is_mx53()) { usb_clk = clk_get(NULL, "usb_phy1_clk"); clk_enable(usb_clk); clk_put(usb_clk); } ret = fsl_usb_host_init(pdev); if (cpu_is_mx53()) { usb_clk = clk_get(NULL, "usb_phy1_clk"); clk_disable(usb_clk); clk_put(usb_clk); } /* setback USBH2_STP to be function */ mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2); return ret; }
static int __init post_cpu_init(void) { unsigned int reg; void __iomem *base; if (cpu_is_mx51() || cpu_is_mx53()) { if (cpu_is_mx51()) base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); else base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR); __raw_writel(0x0, base + 0x40); __raw_writel(0x0, base + 0x44); __raw_writel(0x0, base + 0x48); __raw_writel(0x0, base + 0x4C); reg = __raw_readl(base + 0x50) & 0x00FFFFFF; __raw_writel(reg, base + 0x50); if (cpu_is_mx51()) base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); else base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR); __raw_writel(0x0, base + 0x40); __raw_writel(0x0, base + 0x44); __raw_writel(0x0, base + 0x48); __raw_writel(0x0, base + 0x4C); reg = __raw_readl(base + 0x50) & 0x00FFFFFF; __raw_writel(reg, base + 0x50); } return 0; }
/* * set_mclk_rate * * @param p_mclk_freq mclk frequence * @param csi csi 0 or csi 1 * */ void set_mclk_rate(uint32_t *p_mclk_freq, uint32_t csi) { struct clk *clk; uint32_t freq = 0; char *mclk; if (cpu_is_mx53()) { if (csi == 0) mclk = "ssi_ext1_clk"; else { pr_err("invalid csi num %d\n", csi); return; } } else { if (csi == 0) { mclk = "csi_mclk1"; } else if (csi == 1) { mclk = "csi_mclk2"; } else { pr_err("invalid csi num %d\n", csi); return; } } clk = clk_get(NULL, mclk); freq = clk_round_rate(clk, *p_mclk_freq); clk_set_rate(clk, freq); *p_mclk_freq = freq; clk_put(clk); pr_debug("%s frequency = %d\n", mclk, *p_mclk_freq); }
void __init mx5_usbh2_init(void) { if (cpu_is_mx53() || cpu_is_mx50()) { mxc_usbh2_device.resource[0].start -= MX53_OFFSET; mxc_usbh2_device.resource[0].end -= MX53_OFFSET; } usbh2_config.wakeup_pdata = &usbh2_wakeup_config; mxc_register_device(&mxc_usbh2_device, &usbh2_config); mxc_register_device(&mxc_usbh2_wakeup_device, &usbh2_wakeup_config); }
/* * Returns: * the silicon revision of the cpu * -EINVAL - not a mx53 */ int mx53_revision(void) { if (!cpu_is_mx53()) return -EINVAL; if (cpu_silicon_rev == -1) cpu_silicon_rev = get_mx53_srev(); return cpu_silicon_rev; }
/* * Returns: * the silicon revision of the cpu * -EINVAL - not a mx53 */ int mx53_revision(void) { if (!cpu_is_mx53()) return -EINVAL; if (mx5_cpu_rev == -1) mx5_cpu_rev = get_mx53_srev(); return mx5_cpu_rev; }
static enum filetype imx_bbu_expected_filetype(void) { if (cpu_is_mx8mq() || cpu_is_mx7() || cpu_is_mx6() || cpu_is_vf610() || cpu_is_mx53()) return filetype_imx_image_v2; return filetype_imx_image_v1; }
/*! * This function initializes the memory map. It is called during the * system startup to create static physical to virtual memory map for * the IO modules. */ void __init mx5_map_io(void) { int i; /* Fixup the mappings for MX53 */ if (cpu_is_mx53()) { for (i = 0; i < ARRAY_SIZE(mx5_io_desc); i++) mx5_io_desc[i].pfn -= __phys_to_pfn(0x20000000); } iotable_init(mx5_io_desc, ARRAY_SIZE(mx5_io_desc)); }
static void usbh2_set_ulpi_xcvr(void) { u32 tmp; pr_debug("%s\n", __func__); UH2_USBCMD &= ~UCMD_RUN_STOP; while (UH2_USBCMD & UCMD_RUN_STOP) ; UH2_USBCMD |= UCMD_RESET; while (UH2_USBCMD & UCMD_RESET) USBCTRL_HOST2 &= ~(UCTRL_H2SIC_MASK | UCTRL_BPE); USBCTRL_HOST2 &= ~UCTRL_H2WIE; /* wakeup intr enable */ USBCTRL_HOST2 &= ~UCTRL_H2UIE; /* ULPI intr enable */ USB_CTRL_1 |= USB_CTRL_UH2_EXT_CLK_EN; if (cpu_is_mx53()) USB_CTRL_1 |= USB_CTRL_UH2_CLK_FROM_ULPI_PHY; if (cpu_is_mx51())/* not tested */ USBCTRL_HOST2 |= (1 << 12); /* must set ULPI phy before turning off clock */ tmp = UH2_PORTSC1 & ~PORTSC_PTS_MASK; tmp |= PORTSC_PTS_ULPI; UH2_PORTSC1 = tmp; if (cpu_is_mx53()) { /* turn off the internal 60MHZ clk */ USB_CLKONOFF_CTRL |= (1 << 21); } UH2_USBCMD |= UCMD_RESET; /* reset the controller */ /* allow controller to reset, and leave time for * the ULPI transceiver to reset too. */ msleep(100); /* Turn off the usbpll for ulpi tranceivers */ clk_disable(usb_clk); }
/*! * This function initializes the memory map. It is called during the * system startup to create static physical to virtual memory map for * the IO modules. */ void __init mx5_map_io(void) { int i; // mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR)); /* Fixup the mappings for MX53 */ if (cpu_is_mx53() || cpu_is_mx50()) { for (i = 0; i < ARRAY_SIZE(mx5_io_desc); i++) mx5_io_desc[i].pfn -= __phys_to_pfn(0x20000000); } iotable_init(mx5_io_desc, ARRAY_SIZE(mx5_io_desc)); mxc_arch_reset_init(IO_ADDRESS(WDOG1_BASE_ADDR)); }
static int fsl_usb_host_init_ext(struct platform_device *pdev) { iomux_v3_cfg_t usbh1stp_func = MX51_PAD_USBH1_STP__USBH1_STP; int ret; struct clk *usb_clk; /* the usb_ahb_clk will be enabled in usb_otg_init */ usb_ahb_clk = clk_get(NULL, "usb_ahb_clk"); if (cpu_is_mx53()) { usb_clk = clk_get(NULL, "usboh3_clk"); clk_enable(usb_clk); usb_oh3_clk = usb_clk; usb_clk = clk_get(NULL, "usb_phy2_clk"); clk_enable(usb_clk); usb_phy2_clk = usb_clk; } else if (cpu_is_mx50()) { usb_clk = clk_get(NULL, "usb_phy2_clk"); clk_enable(usb_clk); usb_phy2_clk = usb_clk; } else if (cpu_is_mx51()) { usb_clk = clk_get(NULL, "usboh3_clk"); clk_enable(usb_clk); usb_oh3_clk = usb_clk; } ret = fsl_usb_host_init(pdev); if (ret) return ret; if (cpu_is_mx51()) { /* setback USBH1_STP to be function */ #if 0 /* Jasper: Need to do... */ mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW); gpio_free(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP)); #endif mxc_iomux_v3_setup_pad(usbh1stp_func); gpio_free(MX5X_USBH1_STP); } /* disable remote wakeup irq */ USBCTRL &= ~UCTRL_H1WIE; return 0; }
static void pmic_pdev_register(struct device *dev) { platform_device_register(&adc_ldm); if (!cpu_is_mx53()) platform_device_register(&battery_ldm); platform_device_register(&rtc_ldm); platform_device_register(&power_ldm); platform_device_register(&light_ldm); platform_device_register(&rleds_ldm); platform_device_register(&gleds_ldm); platform_device_register(&bleds_ldm); }
void __init mx5_usbh1_init(void) { if (cpu_is_mx51()) { usbh1_config.phy_mode = FSL_USB2_PHY_ULPI; usbh1_config.transceiver = "isp1504"; usbh1_config.gpio_usb_active = gpio_usbh1_active; usbh1_config.gpio_usb_inactive = gpio_usbh1_inactive; } if (cpu_is_mx53() || cpu_is_mx50()) { mxc_usbh1_device.resource[0].start -= MX53_OFFSET; mxc_usbh1_device.resource[0].end -= MX53_OFFSET; } mxc_register_device(&mxc_usbh1_device, &usbh1_config); usbh1_config.wakeup_pdata = &usbh1_wakeup_config; mxc_register_device(&mxc_usbh1_wakeup_device, &usbh1_wakeup_config); }
static int fsl_usb_host_init_ext(struct platform_device *pdev) { int ret; struct clk *usb_clk; if (cpu_is_mx53()) { usb_clk = clk_get(NULL, "usboh3_clk"); clk_enable(usb_clk); clk_put(usb_clk); usb_clk = clk_get(&pdev->dev, "usb_phy2_clk"); clk_enable(usb_clk); clk_put(usb_clk); /*derive clock from oscillator */ usb_clk = clk_get(NULL, "usb_utmi_clk"); clk_disable(usb_clk); clk_put(usb_clk); } else if (cpu_is_mx50()) { usb_clk = clk_get(&pdev->dev, "usb_phy2_clk"); clk_enable(usb_clk); clk_put(usb_clk); } ret = fsl_usb_host_init(pdev); if (ret) return ret; if (cpu_is_mx51()) { /* setback USBH1_STP to be function */ mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW); gpio_free(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP)); } /* disable remote wakeup irq */ USBCTRL &= ~UCTRL_H1WIE; return 0; }
static void fsl_usb_host_uninit_ext(struct fsl_usb2_platform_data *pdata) { struct clk *usb_clk; if (cpu_is_mx53()) { usb_clk = clk_get(NULL, "usboh3_clk"); clk_disable(usb_clk); clk_put(usb_clk); usb_clk = clk_get(&pdata->pdev->dev, "usb_phy2_clk"); clk_disable(usb_clk); clk_put(usb_clk); } else if (cpu_is_mx50()) { usb_clk = clk_get(&pdata->pdev->dev, "usb_phy2_clk"); clk_disable(usb_clk); clk_put(usb_clk); } fsl_usb_host_uninit(pdata); }
static void fsl_usb_host_uninit_ext(struct fsl_usb2_platform_data *pdata) { if (cpu_is_mx53()) { clk_disable(usb_oh3_clk); clk_put(usb_oh3_clk); clk_disable(usb_phy2_clk); clk_put(usb_phy2_clk); } else if (cpu_is_mx50()) { clk_disable(usb_phy2_clk); clk_put(usb_phy2_clk); } else if (cpu_is_mx51()) { clk_disable(usb_oh3_clk); clk_put(usb_oh3_clk); } fsl_usb_host_uninit(pdata); /* usb_ahb_clk will be disabled at usb_common.c */ clk_put(usb_ahb_clk); }
static int __init mxc_init_uart(void) { if (cpu_is_mx53() || cpu_is_mx50()) { mxc_uart_resources1[0].start -= 0x20000000; mxc_uart_resources1[0].end -= 0x20000000; mxc_uart_resources2[0].start -= 0x20000000; mxc_uart_resources2[0].end -= 0x20000000; mxc_uart_resources3[0].start -= 0x20000000; mxc_uart_resources3[0].end -= 0x20000000; mxc_uart_resources4[0].start -= 0x20000000; mxc_uart_resources4[0].end -= 0x20000000; mxc_uart_resources5[0].start -= 0x20000000; mxc_uart_resources5[0].end -= 0x20000000; } /* Register all the MXC UART platform device structures */ /* For Tequila, register only uart1, this will help PM */ platform_device_register(&mxc_uart_device1); return 0; }
static int utp_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) { int cpu_id = 0; switch (cmd) { case UTP_GET_CPU_ID: /* Currently, it only supports below SoC for manufacture tool * The naming rule * 1. The numberic for SoC string * 2. If there is next SoC version, and the corresponding utp * operation will be differ, then, need to add '1' next to SoC * name. Such as the next 50 SoC version is: cpu_is = 501 */ #ifdef CONFIG_ARCH_MXS if (cpu_is_mx23()) cpu_id = 23; else if (cpu_is_mx28()) cpu_id = 28; #endif #ifdef CONFIG_ARCH_MXC if (cpu_is_mx25()) cpu_id = 25; else if (cpu_is_mx35()) cpu_id = 35; else if (cpu_is_mx51()) cpu_id = 51; else if (cpu_is_mx53()) cpu_id = 53; else if (cpu_is_mx50()) cpu_id = 50; #endif return put_user(cpu_id, (int __user *)arg); default: return -ENOIOCTLCMD; } }
/* * Reset the system. It is called by machine_restart(). */ void arch_reset(char mode, const char *cmd) { unsigned int wcr_enable; arch_reset_special_mode(mode, cmd); #ifdef CONFIG_ARCH_MX6 /* wait for reset to assert... */ if (enable_ldo_mode == LDO_MODE_BYPASSED && !(machine_is_mx6sl_evk() || machine_is_mx6sl_arm2())) { /*On Sabresd board use WDOG2 to reset external PMIC, so here do * more WDOG2 reset.*/ wcr_enable = 0x04;//rudolph add for reboot. 0x14 --> 0x04 20150302 __raw_writew(wcr_enable, IO_ADDRESS(MX6Q_WDOG2_BASE_ADDR)); __raw_writew(wcr_enable, IO_ADDRESS(MX6Q_WDOG2_BASE_ADDR)); } else { wcr_enable = (1 << 2); __raw_writew(wcr_enable, wdog_base); /* errata TKT039676, SRS bit may be missed when SRC sample it, need to write the wdog controller twice to avoid it */ __raw_writew(wcr_enable, wdog_base); } /* wait for reset to assert... */ mdelay(500); printk(KERN_ERR "Watchdog reset failed to assert reset\n"); return; #endif #ifdef CONFIG_MACH_MX51_EFIKAMX if (machine_is_mx51_efikamx()) { mx51_efikamx_reset(); return; } #endif #ifdef CONFIG_ARCH_MX51 /* Workaround to reset NFC_CONFIG3 register * due to the chip warm reset does not reset it */ if (cpu_is_mx53()) __raw_writel(0x20600, MX53_IO_ADDRESS(MX53_NFC_BASE_ADDR)+0x28); if (cpu_is_mx51()) __raw_writel(0x20600, MX51_IO_ADDRESS(MX51_NFC_BASE_ADDR)+0x28); #endif #ifdef CONFIG_ARCH_MX5 /* Stop DVFS-CORE before reboot. */ if (dvfs_core_is_active) stop_dvfs(); #endif if (cpu_is_mx1()) { wcr_enable = (1 << 0); } else { struct clk *clk; clk = clk_get_sys("imx2-wdt.0", NULL); if (!IS_ERR(clk)) clk_enable(clk); wcr_enable = (1 << 2); } /* Assert SRS signal */ __raw_writew(wcr_enable, wdog_base); /* wait for reset to assert... */ mdelay(500); printk(KERN_ERR "Watchdog reset failed to assert reset\n"); /* delay to allow the serial port to show the message */ mdelay(50); /* we'll take a jump through zero as a poor second */ cpu_reset(0); }
static int __init w1_setup(char *__unused) { enable_w1 = 1; return cpu_is_mx53(); }
static void otg_set_utmi_xcvr(void) { u32 tmp; /* Stop then Reset */ UOG_USBCMD &= ~UCMD_RUN_STOP; while (UOG_USBCMD & UCMD_RUN_STOP) ; UOG_USBCMD |= UCMD_RESET; while ((UOG_USBCMD) & (UCMD_RESET)) ; if (cpu_is_mx53()) USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS; if (cpu_is_mx51()) { if (machine_is_mx51_3ds()) { /* OTG Polarity of Overcurrent is Low active */ USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_POL; /* Enable OTG Overcurrent Event */ USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_OC_DIS; } else { /* BBG is not using OC */ USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS; } } else if (cpu_is_mx25()) { USBCTRL |= UCTRL_OCPOL; USBCTRL &= ~UCTRL_PP; } else if (cpu_is_mx50()) { USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS; } else { /* USBOTG_PWR low active */ USBCTRL &= ~UCTRL_PP; /* OverCurrent Polarity is Low Active */ USBCTRL &= ~UCTRL_OCPOL; if (cpu_is_mx35() && (imx_cpu_ver() < IMX_CHIP_REVISION_2_0)) /* OTG Lock Disable */ USBCTRL |= UCTRL_OLOCKD; } if (cpu_is_mx51()) USBCTRL &= ~UCTRL_OPM; /* OTG Power Mask */ USBCTRL &= ~UCTRL_OWIE; /* OTG Wakeup Intr Disable */ /* set UTMI xcvr */ tmp = UOG_PORTSC1 & ~PORTSC_PTS_MASK; tmp |= PORTSC_PTS_UTMI; UOG_PORTSC1 = tmp; if (cpu_is_mx51()) { /* Set the PHY clock to 19.2MHz */ USB_PHY_CTR_FUNC2 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK; USB_PHY_CTR_FUNC2 |= 0x01; } /* Workaround an IC issue for ehci driver: * when turn off root hub port power, EHCI set * PORTSC reserved bits to be 0, but PTW with 0 * means 8 bits tranceiver width, here change * it back to be 16 bits and do PHY diable and * then enable. */ UOG_PORTSC1 |= PORTSC_PTW; if (cpu_is_mx35() || cpu_is_mx25()) { /* Enable UTMI interface in PHY control Reg */ USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_UTMI_ENABLE; USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_UTMI_ENABLE; } /* need to reset the controller here so that the ID pin * is correctly detected. */ /* Stop then Reset */ UOG_USBCMD &= ~UCMD_RUN_STOP; while (UOG_USBCMD & UCMD_RUN_STOP) ; UOG_USBCMD |= UCMD_RESET; while ((UOG_USBCMD) & (UCMD_RESET)) ; /* allow controller to reset, and leave time for * the ULPI transceiver to reset too. */ msleep(100); if (cpu_is_mx37()) { /* fix USB PHY Power Gating leakage issue for i.MX37 */ USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETON; USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CHGRDETEN; } /* Turn off the usbpll for UTMI tranceivers */ clk_disable(usb_clk); }
/* * SSI DAI format configuration. * Should only be called when port is inactive (i.e. SSIEN = 0). * Note: We don't use the I2S modes but instead manually configure the * SSI for I2S. */ static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) { struct imx_ssi *priv = (struct imx_ssi *)cpu_dai->private_data; void __iomem *ioaddr = priv->ioaddr; u32 stcr = 0, srcr = 0, scr; scr = __raw_readl(ioaddr + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET); if (scr & SSI_SCR_SSIEN) return 0; /* DAI mode */ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { case SND_SOC_DAIFMT_I2S: /* data on rising edge of bclk, frame low 1clk before data */ stcr |= SSI_STCR_TFSI | SSI_STCR_TEFS | SSI_STCR_TXBIT0; srcr |= SSI_SRCR_RFSI | SSI_SRCR_REFS | SSI_SRCR_RXBIT0; break; case SND_SOC_DAIFMT_LEFT_J: /* data on rising edge of bclk, frame high with data */ stcr |= SSI_STCR_TXBIT0; srcr |= SSI_SRCR_RXBIT0; break; case SND_SOC_DAIFMT_DSP_B: /* data on rising edge of bclk, frame high with data */ stcr |= SSI_STCR_TFSL; srcr |= SSI_SRCR_RFSL; break; case SND_SOC_DAIFMT_DSP_A: /* data on rising edge of bclk, frame high 1clk before data */ stcr |= SSI_STCR_TFSL | SSI_STCR_TEFS; srcr |= SSI_SRCR_RFSL | SSI_SRCR_REFS; break; } /* DAI clock inversion */ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { case SND_SOC_DAIFMT_IB_IF: stcr &= ~(SSI_STCR_TSCKP | SSI_STCR_TFSI); srcr &= ~(SSI_SRCR_RSCKP | SSI_SRCR_RFSI); break; case SND_SOC_DAIFMT_IB_NF: stcr |= SSI_STCR_TFSI; stcr &= ~SSI_STCR_TSCKP; srcr |= SSI_SRCR_RFSI; srcr &= ~SSI_SRCR_RSCKP; break; case SND_SOC_DAIFMT_NB_IF: stcr &= ~SSI_STCR_TFSI; stcr |= SSI_STCR_TSCKP; srcr &= ~SSI_SRCR_RFSI; srcr |= SSI_SRCR_RSCKP; break; case SND_SOC_DAIFMT_NB_NF: stcr |= SSI_STCR_TFSI | SSI_STCR_TSCKP; srcr |= SSI_SRCR_RFSI | SSI_SRCR_RSCKP; break; } /* DAI clock master masks */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBS_CFS: stcr |= SSI_STCR_TFDIR | SSI_STCR_TXDIR; if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S) && priv->network_mode) { scr &= ~SSI_SCR_I2S_MODE_MASK; scr |= SSI_SCR_I2S_MODE_MSTR; } break; case SND_SOC_DAIFMT_CBM_CFS: stcr |= SSI_STCR_TFDIR; srcr |= SSI_SRCR_RFDIR; break; case SND_SOC_DAIFMT_CBS_CFM: stcr |= SSI_STCR_TXDIR; srcr |= SSI_SRCR_RXDIR; break; case SND_SOC_DAIFMT_CBM_CFM: if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S) && priv->network_mode) { scr &= ~SSI_SCR_I2S_MODE_MASK; scr |= SSI_SCR_I2S_MODE_SLAVE; } break; } /* sync */ if (priv->sync_mode) scr |= SSI_SCR_SYN; /* tdm - only for stereo atm */ if (priv->network_mode) scr |= SSI_SCR_NET; #ifdef CONFIG_MXC_SSI_DUAL_FIFO if (cpu_is_mx51() || cpu_is_mx53()) { stcr |= SSI_STCR_TFEN1; srcr |= SSI_SRCR_RFEN1; scr |= SSI_SCR_TCH_EN; } #endif __raw_writel(stcr, ioaddr + SSI_STCR); __raw_writel(srcr, ioaddr + SSI_SRCR); __raw_writel(scr, ioaddr + SSI_SCR); SSI_DUMP(); return 0; }
static int imx_3stack_surround_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; struct snd_soc_dai *codec_dai = rtd->codec_dai; unsigned int rate = params_rate(params); u32 dai_format; unsigned int lrclk_ratio = 0; if (hw_state.hw) return 0; hw_state.hw = 1; if (cpu_is_mx53()) { switch (rate) { case 32000: lrclk_ratio = 3; break; case 48000: lrclk_ratio = 3; break; case 64000: lrclk_ratio = 1; break; case 96000: lrclk_ratio = 1; break; case 128000: lrclk_ratio = 1; break; case 44100: lrclk_ratio = 3; break; case 88200: lrclk_ratio = 1; break; case 176400: lrclk_ratio = 0; break; case 192000: lrclk_ratio = 0; break; default: pr_info("Rate not support.\n"); return -EINVAL;; } } else if (cpu_is_mx6q()) { switch (rate) { case 32000: lrclk_ratio = 5; break; case 48000: lrclk_ratio = 5; break; case 64000: lrclk_ratio = 2; break; case 96000: lrclk_ratio = 2; break; case 128000: lrclk_ratio = 2; break; case 44100: lrclk_ratio = 5; break; case 88200: lrclk_ratio = 2; break; case 176400: lrclk_ratio = 0; break; case 192000: lrclk_ratio = 0; break; default: pr_info("Rate not support.\n"); return -EINVAL;; } } dai_format = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS; /* set cpu DAI configuration */ snd_soc_dai_set_fmt(cpu_dai, dai_format); /* set i.MX active slot mask */ snd_soc_dai_set_tdm_slot(cpu_dai, 0x3, 0x3, 2, 32); /* set the ESAI system clock as output */ if (cpu_is_mx53()) { snd_soc_dai_set_sysclk(cpu_dai, ESAI_CLK_EXTAL, mclk_freq, SND_SOC_CLOCK_OUT); } else if (cpu_is_mx6q()) { snd_soc_dai_set_sysclk(cpu_dai, ESAI_CLK_EXTAL_DIV, mclk_freq, SND_SOC_CLOCK_OUT); } /* set the ratio */ snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_PSR, 1); if (cpu_is_mx53()) snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_PM, 0); else if (cpu_is_mx6q()) snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_PM, 2); snd_soc_dai_set_clkdiv(cpu_dai, ESAI_TX_DIV_FP, lrclk_ratio); snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_PSR, 1); if (cpu_is_mx53()) snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_PM, 0); else if (cpu_is_mx6q()) snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_PM, 2); snd_soc_dai_set_clkdiv(cpu_dai, ESAI_RX_DIV_FP, lrclk_ratio); /* set codec DAI configuration */ snd_soc_dai_set_fmt(codec_dai, dai_format); /* set codec Master clock */ snd_soc_dai_set_sysclk(codec_dai, 0, mclk_freq, SND_SOC_CLOCK_IN); return 0; }
/* set cpu low power mode before WFI instruction */ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) { u32 plat_lpc, arm_srpgcr, ccm_clpcr; u32 empgc0 = 0; u32 empgc1 = 0; int stop_mode = 0; /* always allow platform to issue a deep sleep mode request */ plat_lpc = __raw_readl(arm_plat_base + MXC_CORTEXA8_PLAT_LPC) & ~(MXC_CORTEXA8_PLAT_LPC_DSM); ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); if (!cpu_is_mx53()) { empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); } switch (mode) { case WAIT_CLOCKED: break; case WAIT_UNCLOCKED: ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET); break; case WAIT_UNCLOCKED_POWER_OFF: case STOP_POWER_OFF: plat_lpc |= MXC_CORTEXA8_PLAT_LPC_DSM | MXC_CORTEXA8_PLAT_LPC_DBG_DSM; if (mode == WAIT_UNCLOCKED_POWER_OFF) { ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET); ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; stop_mode = 0; } else { ccm_clpcr |= (0x2 << MXC_CCM_CLPCR_LPM_OFFSET); ccm_clpcr |= (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET); ccm_clpcr |= MXC_CCM_CLPCR_VSTBY; ccm_clpcr |= MXC_CCM_CLPCR_SBYOS; stop_mode = 1; } arm_srpgcr |= MXC_SRPGCR_PCR; if (stop_mode && !cpu_is_mx53()) { empgc0 |= MXC_SRPGCR_PCR; empgc1 |= MXC_SRPGCR_PCR; } if (tzic_enable_wake(1) != 0) return; break; case STOP_POWER_ON: ccm_clpcr |= (0x2 << MXC_CCM_CLPCR_LPM_OFFSET); break; default: printk(KERN_WARNING "UNKNOWN cpu power mode: %d\n", mode); return; } __raw_writel(plat_lpc, arm_plat_base + MXC_CORTEXA8_PLAT_LPC); __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); if (cpu_is_mx51() || (mx53_revision() >= IMX_CHIP_REVISION_2_0) || (mx50_revision() >= IMX_CHIP_REVISION_1_1)) __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); /* Enable NEON SRPG for all but MX50TO1.0. */ if (!(mx50_revision() == IMX_CHIP_REVISION_1_0)) __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); if (stop_mode && !cpu_is_mx53()) { __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR); __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); } }
/*! * This function puts the CPU into idle mode. It is called by default_idle() * in process.c file. */ void arch_idle(void) { if (likely(!mxc_jtag_enabled)) { if (ddr_clk == NULL) ddr_clk = clk_get(NULL, "ddr_clk"); if (gpc_dvfs_clk == NULL) gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk"); /* gpc clock is needed for SRPG */ clk_enable(gpc_dvfs_clk); mxc_cpu_lp_set(arch_idle_mode); if (cpu_is_mx50() && (clk_get_usecount(ddr_clk) == 0)) { if (sys_clk == NULL) sys_clk = clk_get(NULL, "sys_clk"); if (low_bus_freq_mode) { u32 reg, cpu_podf; reg = __raw_readl(apll_base + 0x50); reg = 0x120490; __raw_writel(reg, apll_base + 0x50); reg = __raw_readl(apll_base + 0x80); reg |= 1; __raw_writel(reg, apll_base + 0x80); if (mx50_ddr_type != MX50_DDR2) { /* Move ARM to be sourced from 24MHz XTAL. * when ARM is in WFI. */ if (pll1_sw_clk == NULL) pll1_sw_clk = clk_get(NULL, "pll1_sw_clk"); if (osc == NULL) osc = clk_get(NULL, "lp_apm"); if (pll1_main_clk == NULL) pll1_main_clk = clk_get(NULL, "pll1_main_clk"); clk_set_parent(pll1_sw_clk, osc); /* Set the ARM-PODF divider to 1. */ cpu_podf = __raw_readl(MXC_CCM_CACRR); __raw_writel(0x01, MXC_CCM_CACRR); while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_ARM_PODF_BUSY) ; } wait_in_iram(ccm_base, databahn_base, clk_get_usecount(sys_clk)); if (mx50_ddr_type != MX50_DDR2) { /* Set the ARM-POD divider back * to the original. */ __raw_writel(cpu_podf, MXC_CCM_CACRR); while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_ARM_PODF_BUSY) ; clk_set_parent(pll1_sw_clk, pll1_main_clk); } } else wait_in_iram(ccm_base, databahn_base, clk_get_usecount(sys_clk)); } else if (cpu_is_mx53() && (clk_get_usecount(ddr_clk) == 0) && low_bus_freq_mode) { suspend_in_iram(suspend_param1, NULL, NULL); } else cpu_do_idle(); clk_disable(gpc_dvfs_clk); clk_put(ddr_clk); } }
static int __init ard_vga_setup(char *__unused) { enable_ard_vga = 1; printk(KERN_INFO "Enable MX53 ARD VGA\n"); return cpu_is_mx53(); }
static int __init post_cpu_init(void) { void __iomem *base; unsigned int reg; struct clk *gpcclk = clk_get(NULL, "gpc_dvfs_clk"); int iram_size = IRAM_SIZE; if (!cpu_is_mx5()) return 0; if (cpu_is_mx51()) { mipi_hsc_disable(); #if defined(CONFIG_MXC_SECURITY_SCC) || defined(CONFIG_MXC_SECURITY_SCC_MODULE) iram_size -= SCC_RAM_SIZE; #endif iram_init(MX51_IRAM_BASE_ADDR, iram_size); } else { iram_init(MX53_IRAM_BASE_ADDR, iram_size); } gpc_base = ioremap(MX53_BASE_ADDR(GPC_BASE_ADDR), SZ_4K); ccm_base = ioremap(MX53_BASE_ADDR(CCM_BASE_ADDR), SZ_4K); clk_enable(gpcclk); /* Setup the number of clock cycles to wait for SRPG * power up and power down requests. */ __raw_writel(0x010F0201, gpc_base + SRPG_ARM_PUPSCR); __raw_writel(0x010F0201, gpc_base + SRPG_NEON_PUPSCR); __raw_writel(0x00000008, gpc_base + SRPG_EMPGC0_PUPSCR); __raw_writel(0x00000008, gpc_base + SRPG_EMPGC1_PUPSCR); __raw_writel(0x01010101, gpc_base + SRPG_ARM_PDNSCR); __raw_writel(0x01010101, gpc_base + SRPG_NEON_PDNSCR); __raw_writel(0x00000018, gpc_base + SRPG_EMPGC0_PDNSCR); __raw_writel(0x00000018, gpc_base + SRPG_EMPGC1_PDNSCR); clk_disable(gpcclk); clk_put(gpcclk); /* Set ALP bits to 000. Set ALP_EN bit in Arm Memory Controller reg. */ arm_plat_base = ioremap(MX53_BASE_ADDR(ARM_BASE_ADDR), SZ_4K); reg = 0x8; __raw_writel(reg, arm_plat_base + CORTEXA8_PLAT_AMC); base = ioremap(MX53_BASE_ADDR(AIPS1_BASE_ADDR), SZ_4K); __raw_writel(0x0, base + 0x40); __raw_writel(0x0, base + 0x44); __raw_writel(0x0, base + 0x48); __raw_writel(0x0, base + 0x4C); reg = __raw_readl(base + 0x50) & 0x00FFFFFF; __raw_writel(reg, base + 0x50); iounmap(base); base = ioremap(MX53_BASE_ADDR(AIPS2_BASE_ADDR), SZ_4K); __raw_writel(0x0, base + 0x40); __raw_writel(0x0, base + 0x44); __raw_writel(0x0, base + 0x48); __raw_writel(0x0, base + 0x4C); reg = __raw_readl(base + 0x50) & 0x00FFFFFF; __raw_writel(reg, base + 0x50); iounmap(base); if (cpu_is_mx51() || cpu_is_mx53()) { /*Allow for automatic gating of the EMI internal clock. * If this is done, emi_intr CCGR bits should be set to 11. */ base = ioremap(MX53_BASE_ADDR(M4IF_BASE_ADDR), SZ_4K); reg = __raw_readl(base + 0x8c); reg &= ~0x1; __raw_writel(reg, base + 0x8c); iounmap(base); } if (cpu_is_mx50()) init_ddr_settings(); return 0; }
/*! * Returns pc of SDMA script according to peripheral and transfer type * * @param peripheral_type peripheral type * @param transfer_type transfer type * * @return PC of SDMA script */ static unsigned short sdma_get_pc(sdma_periphT peripheral_type, sdma_transferT transfer_type) { int res = 0; if (peripheral_type == MEMORY) { switch (transfer_type) { case emi_2_int: res = sdma_script_addrs.mxc_sdma_ap_2_ap_addr; break; case emi_2_emi: res = sdma_script_addrs.mxc_sdma_ap_2_ap_addr; break; case int_2_emi: res = sdma_script_addrs.mxc_sdma_ap_2_ap_addr; break; default: res = -EINVAL; } } else if (peripheral_type == DSP) { switch (transfer_type) { case emi_2_dsp: res = sdma_script_addrs.mxc_sdma_ap_2_bp_addr; break; case dsp_2_emi: res = sdma_script_addrs.mxc_sdma_bp_2_ap_addr; break; case dsp_2_emi_loop: res = sdma_script_addrs. mxc_sdma_loopback_on_dsp_side_addr; break; case emi_2_dsp_loop: res = sdma_script_addrs.mxc_sdma_mcu_interrupt_only_addr; break; default: res = -EINVAL; } } else if (peripheral_type == FIRI) { switch (transfer_type) { case per_2_int: res = sdma_script_addrs.mxc_sdma_firi_2_per_addr; break; case per_2_emi: res = sdma_script_addrs.mxc_sdma_firi_2_mcu_addr; break; case int_2_per: res = sdma_script_addrs.mxc_sdma_per_2_firi_addr; break; case emi_2_per: res = sdma_script_addrs.mxc_sdma_mcu_2_firi_addr; break; default: res = -EINVAL; } } else if (peripheral_type == UART) { switch (transfer_type) { case per_2_int: res = sdma_script_addrs.mxc_sdma_uart_2_per_addr; break; case per_2_emi: res = sdma_script_addrs.mxc_sdma_uart_2_mcu_addr; break; case int_2_per: res = sdma_script_addrs.mxc_sdma_per_2_app_addr; break; case emi_2_per: res = sdma_script_addrs.mxc_sdma_mcu_2_app_addr; break; default: res = -EINVAL; } } else if (peripheral_type == UART_SP) { switch (transfer_type) { case per_2_int: res = sdma_script_addrs.mxc_sdma_uartsh_2_per_addr; break; case per_2_emi: res = sdma_script_addrs.mxc_sdma_uartsh_2_mcu_addr; break; case int_2_per: res = sdma_script_addrs.mxc_sdma_per_2_shp_addr; break; case emi_2_per: res = sdma_script_addrs.mxc_sdma_mcu_2_shp_addr; break; default: res = -EINVAL; } } else if (peripheral_type == ATA) { switch (transfer_type) { case per_2_emi: res = sdma_script_addrs.mxc_sdma_ata_2_mcu_addr; break; case emi_2_per: res = sdma_script_addrs.mxc_sdma_mcu_2_ata_addr; break; default: res = -EINVAL; } #ifdef CONFIG_MXC_SSI_DUAL_FIFO } else if (peripheral_type == CSPI || peripheral_type == EXT || (peripheral_type == SSI && !(cpu_is_mx51() || cpu_is_mx53()))) { #else } else if (peripheral_type == CSPI || peripheral_type == EXT || peripheral_type == SSI) { #endif switch (transfer_type) { case per_2_int: res = sdma_script_addrs.mxc_sdma_app_2_per_addr; break; case per_2_emi: res = sdma_script_addrs.mxc_sdma_app_2_mcu_addr; break; case int_2_per: res = sdma_script_addrs.mxc_sdma_per_2_app_addr; break; case emi_2_per: res = sdma_script_addrs.mxc_sdma_mcu_2_app_addr; break; default: res = -EINVAL; } #ifdef CONFIG_MXC_SSI_DUAL_FIFO } else if (peripheral_type == MMC || peripheral_type == SDHC || peripheral_type == CSPI_SP || peripheral_type == ESAI || peripheral_type == MSHC_SP || (peripheral_type == SSI_SP && !(cpu_is_mx51() || cpu_is_mx53()))) { #else } else if (peripheral_type == SSI_SP || peripheral_type == MMC || peripheral_type == SDHC || peripheral_type == CSPI_SP || peripheral_type == ESAI || peripheral_type == MSHC_SP) { #endif switch (transfer_type) { case per_2_int: res = sdma_script_addrs.mxc_sdma_shp_2_per_addr; break; case per_2_emi: res = sdma_script_addrs.mxc_sdma_shp_2_mcu_addr; break; case int_2_per: res = sdma_script_addrs.mxc_sdma_per_2_shp_addr; break; case emi_2_per: res = sdma_script_addrs.mxc_sdma_mcu_2_shp_addr; break; default: res = -EINVAL; } } else if (peripheral_type == ASRC) { switch (transfer_type) { case per_2_emi: res = sdma_script_addrs.mxc_sdma_shp_2_mcu_addr; break; case emi_2_per: res = sdma_script_addrs.mxc_sdma_mcu_2_shp_addr; break; case per_2_per: res = sdma_script_addrs.mxc_sdma_per_2_per_addr; break; default: res = -EINVAL; } } else if (peripheral_type == MSHC) { switch (transfer_type) { case per_2_emi: res = sdma_script_addrs.mxc_sdma_mshc_2_mcu_addr; break; case emi_2_per: res = sdma_script_addrs.mxc_sdma_mcu_2_mshc_addr; break; default: res = -EINVAL; } } else if (peripheral_type == CCM) { switch (transfer_type) { case per_2_emi: res = sdma_script_addrs.mxc_sdma_dptc_dvfs_addr; break; default: res = -EINVAL; } } else if (peripheral_type == FIFO_MEMORY) { res = sdma_script_addrs.mxc_sdma_ap_2_ap_fixed_addr; } else if (peripheral_type == SPDIF) { switch (transfer_type) { case per_2_emi: res = sdma_script_addrs.mxc_sdma_spdif_2_mcu_addr; break; case emi_2_per: res = sdma_script_addrs.mxc_sdma_mcu_2_spdif_addr; break; default: res = -EINVAL; } } else if (peripheral_type == IPU_MEMORY) { if (transfer_type == emi_2_per) { res = sdma_script_addrs.mxc_sdma_ext_mem_2_ipu_addr; } else { res = -EINVAL; } #ifdef CONFIG_MXC_SSI_DUAL_FIFO } else if (peripheral_type == SSI) { switch (transfer_type) { case per_2_int: res = sdma_script_addrs.mxc_sdma_ssiapp_2_mcu_addr; break; case per_2_emi: res = sdma_script_addrs.mxc_sdma_ssiapp_2_mcu_addr; break; case int_2_per: res = sdma_script_addrs.mxc_sdma_mcu_2_ssiapp_addr; break; case emi_2_per: res = sdma_script_addrs.mxc_sdma_mcu_2_ssiapp_addr; break; default: res = -EINVAL; } } else if (peripheral_type == SSI_SP) { switch (transfer_type) { case per_2_int: res = sdma_script_addrs.mxc_sdma_ssish_2_mcu_addr; break; case int_2_per: res = sdma_script_addrs.mxc_sdma_mcu_2_ssish_addr; break; case per_2_emi: res = sdma_script_addrs.mxc_sdma_ssish_2_mcu_addr; break; case emi_2_per: res = sdma_script_addrs.mxc_sdma_mcu_2_ssish_addr; break; default: res = -EINVAL; } #endif } if (res < 0) { printk(KERN_ERR "SDMA script not found\n"); } return res; }