void __init usb_musb_init(struct omap_musb_board_data *board_data)
{
struct omap_hwmod *oh;
struct omap_device *od;
struct platform_device *pdev;
struct device *dev;
int bus_id = -1;
const char *oh_name, *name;
if (cpu_is_omap3517() || cpu_is_omap3505()) {
} else if (cpu_is_omap44xx()) {
usb_musb_mux_init(board_data);
}
/*
* REVISIT: This line can be removed once all the platforms using
* musb_core.c have been converted to use use clkdev.
*/
musb_plat.clock = "ick";
musb_plat.board_data = board_data;
musb_plat.power = board_data->power >> 1;
musb_plat.mode = board_data->mode;
musb_plat.extvbus = board_data->extvbus;
if (cpu_is_omap44xx())
omap4430_phy_init(dev);
if (cpu_is_omap3517() || cpu_is_omap3505()) {
oh_name = "am35x_otg_hs";
name = "musb-am35x";
} else {
oh_name = "usb_otg_hs";
name = "musb-omap2430";
}
oh = omap_hwmod_lookup(oh_name);
if (!oh) {
pr_err("Could not look up %s\n", oh_name);
return;
}
od = omap_device_build(name, bus_id, oh, &musb_plat,
sizeof(musb_plat), omap_musb_latency,
ARRAY_SIZE(omap_musb_latency), false);
if (IS_ERR(od)) {
pr_err("Could not build omap_device for %s %s\n",
name, oh_name);
return;
}
pdev = &od->pdev;
dev = &pdev->dev;
get_device(dev);
dev->dma_mask = &musb_dmamask;
dev->coherent_dma_mask = musb_dmamask;
put_device(dev);
}
void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1,
struct omap_opp *mpu_opps,
struct omap_opp *dsp_opps,
struct omap_opp *l3_opps)
{
struct omap_hwmod **hwmods = NULL;
if (cpu_is_omap2420())
hwmods = omap2420_hwmods;
else if (cpu_is_omap2430())
hwmods = omap2430_hwmods;
else if (cpu_is_omap34xx())
hwmods = omap34xx_hwmods;
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
/* The OPP tables have to be registered before a clk init */
omap_hwmod_init(hwmods);
omap2_mux_init();
omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
pwrdm_init(powerdomains_omap);
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
#endif
omap2_clk_init();
omap_serial_early_init();
#ifndef CONFIG_ARCH_OMAP4
omap_hwmod_late_init();
omap_pm_if_init();
if (!cpu_is_omap3505() && !cpu_is_omap3517()) {
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
_omap2_init_reprogram_sdrc();
}
#endif
gpmc_init();
}
void __init omap3xxx_voltagedomains_init(void)
{
struct voltagedomain *voltdm;
struct voltagedomain **voltdms;
int i;
/*
* XXX Will depend on the process, validation, and binning
* for the currently-running IC
*/
if (cpu_is_omap3630()) {
omap3_voltdm_mpu.volt_data = omap36xx_vddmpu_volt_data;
omap3_voltdm_core.volt_data = omap36xx_vddcore_volt_data;
} else {
omap3_voltdm_mpu.volt_data = omap34xx_vddmpu_volt_data;
omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data;
}
if (cpu_is_omap3517() || cpu_is_omap3505())
voltdms = voltagedomains_am35xx;
else
voltdms = voltagedomains_omap3;
for (i = 0; voltdm = voltdms[i], voltdm; i++)
voltdm->sys_clk.name = sys_clk_name;
voltdm_init(voltdms);
};
void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
struct device *dev;
int bus_id = -1;
const char *oh_name, *name;
struct omap_musb_board_data *board_data;
if (musb_board_data)
board_data = musb_board_data;
else
board_data = &musb_default_board_data;
/*
*/
musb_plat.clock = "ick";
musb_plat.board_data = board_data;
musb_plat.power = board_data->power >> 1;
musb_plat.mode = board_data->mode;
musb_plat.extvbus = board_data->extvbus;
if (cpu_is_omap3517() || cpu_is_omap3505()) {
oh_name = "am35x_otg_hs";
name = "musb-am35x";
} else if (cpu_is_ti81xx()) {
oh_name = "usb_otg_hs";
name = "musb-ti81xx";
} else {
oh_name = "usb_otg_hs";
name = "musb-omap2430";
}
oh = omap_hwmod_lookup(oh_name);
if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
__func__, oh_name))
return;
pdev = omap_device_build(name, bus_id, oh, &musb_plat,
sizeof(musb_plat), NULL, 0, false);
if (IS_ERR(pdev)) {
pr_err("Could not build omap_device for %s %s\n",
name, oh_name);
return;
}
dev = &pdev->dev;
get_device(dev);
dev->dma_mask = &musb_dmamask;
dev->coherent_dma_mask = musb_dmamask;
put_device(dev);
if (cpu_is_omap44xx())
omap4430_phy_init(dev);
}
/*
* Build omap_devices for processors and bus.
*/
static void omap2_init_processor_devices(void)
{
_init_omap_device("mpu");
if (omap3_has_iva() && !cpu_is_omap3517())
_init_omap_device("iva");
if (cpu_is_omap44xx()) {
_init_omap_device("l3_main_1");
_init_omap_device("dsp");
_init_omap_device("iva");
} else {
_init_omap_device("l3_main");
}
}
int __init omap3_twl_init(void)
{
struct voltagedomain *voltdm;
if (!cpu_is_omap34xx())
return -ENODEV;
/*
* In case of AM3517/AM3505 we should not be going down
* further, since SR is not applicable there.
*/
if (cpu_is_omap3505() || cpu_is_omap3517())
return -ENODEV;
if (cpu_is_omap3630()) {
omap3_mpu_volt_info.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
omap3_mpu_volt_info.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
omap3_core_volt_info.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
}
/*
* The smartreflex bit on twl4030 needs to be enabled by
* default irrespective of whether smartreflex module is
* enabled on the OMAP side or not. This is because without
* this bit enabled the voltage scaling through
* vp forceupdate does not function properly on OMAP3.
*/
if (twl_sr_enable)
omap3_twl_set_sr_bit(1);
voltdm = omap_voltage_domain_lookup("mpu");
omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
voltdm = omap_voltage_domain_lookup("core");
omap_voltage_register_pmic(voltdm, &omap3_core_volt_info);
return 0;
}
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
struct omap2_hsmmc_info *c;
int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
int i;
u32 reg;
if (!cpu_is_omap44xx()) {
if (cpu_is_omap2430()) {
control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
} else {
control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
}
} else {
control_pbias_offset =
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
reg = omap4_ctrl_pad_readl(control_mmc1);
reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
omap4_ctrl_pad_writel(reg, control_mmc1);
}
for (c = controllers; c->mmc; c++) {
struct hsmmc_controller *hc = hsmmc + c->mmc - 1;
struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
if (!c->mmc || c->mmc > nr_hsmmc) {
pr_debug("MMC%d: no such controller\n", c->mmc);
continue;
}
if (mmc) {
pr_debug("MMC%d: already configured\n", c->mmc);
continue;
}
mmc = kzalloc(sizeof(struct omap_mmc_platform_data),
GFP_KERNEL);
if (!mmc) {
pr_err("Cannot allocate memory for mmc device!\n");
goto done;
}
if (cpu_is_ti816x())
mmc->version = MMC_CTRL_VERSION_2;
if (c->name)
strncpy(hc->name, c->name, HSMMC_NAME_LEN);
else
snprintf(hc->name, ARRAY_SIZE(hc->name),
"mmc%islot%i", c->mmc, 1);
mmc->slots[0].name = hc->name;
mmc->nr_slots = 1;
mmc->slots[0].caps = c->caps;
mmc->slots[0].internal_clock = !c->ext_clock;
mmc->dma_mask = 0xffffffff;
if (cpu_is_omap44xx())
mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
else
mmc->reg_offset = 0;
mmc->get_context_loss_count = hsmmc_get_context_loss;
mmc->slots[0].switch_pin = c->gpio_cd;
mmc->slots[0].gpio_wp = c->gpio_wp;
mmc->slots[0].remux = c->remux;
mmc->slots[0].init_card = c->init_card;
if (c->cover_only)
mmc->slots[0].cover = 1;
if (c->nonremovable)
mmc->slots[0].nonremovable = 1;
if (c->power_saving)
mmc->slots[0].power_saving = 1;
if (c->no_off)
mmc->slots[0].no_off = 1;
if (c->vcc_aux_disable_is_sleep)
mmc->slots[0].vcc_aux_disable_is_sleep = 1;
/* NOTE: MMC slots should have a Vcc regulator set up.
* This may be from a TWL4030-family chip, another
* controllable regulator, or a fixed supply.
*
* temporary HACK: ocr_mask instead of fixed supply
*/
if (cpu_is_omap3505() || cpu_is_omap3517())
mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
MMC_VDD_26_27 |
MMC_VDD_27_28 |
MMC_VDD_29_30 |
MMC_VDD_30_31 |
MMC_VDD_31_32;
else
mmc->slots[0].ocr_mask = c->ocr_mask;
if (cpu_is_omap3517() || cpu_is_omap3505() || cpu_is_ti81xx())
mmc->slots[0].set_power = nop_mmc_set_power;
else
mmc->slots[0].features |= HSMMC_HAS_PBIAS;
if ((cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) ||
cpu_is_ti814x())
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
switch (c->mmc) {
case 1:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* on-chip level shifting via PBIAS0/PBIAS1 */
if (cpu_is_omap44xx()) {
mmc->slots[0].before_set_reg =
omap4_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap4_hsmmc1_after_set_reg;
} else {
mmc->slots[0].before_set_reg =
omap_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap_hsmmc1_after_set_reg;
}
}
/* Omap3630 HSMMC1 supports only 4-bit */
if (cpu_is_omap3630() &&
(c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
mmc->slots[0].caps = c->caps;
}
break;
case 2:
if (c->ext_clock)
c->transceiver = 1;
if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
}
/* FALLTHROUGH */
case 3:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* off-chip level shifting, or none */
mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
mmc->slots[0].after_set_reg = NULL;
}
break;
default:
pr_err("MMC%d configuration not supported!\n", c->mmc);
kfree(mmc);
continue;
}
hsmmc_data[c->mmc - 1] = mmc;
}
if (!cpu_is_ti81xx())
omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
else
omap2_init_mmc(hsmmc_data, TI81XX_NR_MMC);
/* pass the device nodes back to board setup code */
for (c = controllers; c->mmc; c++) {
struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
if (!c->mmc || c->mmc > nr_hsmmc)
continue;
c->dev = mmc->dev;
}
done:
for (i = 0; i < nr_hsmmc; i++)
kfree(hsmmc_data[i]);
}
static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
struct omap_mmc_platform_data *mmc)
{
char *hc_name;
hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
if (!hc_name) {
pr_err("Cannot allocate memory for controller slot name\n");
kfree(hc_name);
return -ENOMEM;
}
if (c->name)
strncpy(hc_name, c->name, HSMMC_NAME_LEN);
else
snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
c->mmc, 1);
mmc->slots[0].name = hc_name;
mmc->nr_slots = 1;
mmc->slots[0].caps = c->caps;
mmc->slots[0].internal_clock = !c->ext_clock;
mmc->dma_mask = 0xffffffff;
if (cpu_is_omap44xx())
mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
else
mmc->reg_offset = 0;
mmc->slots[0].switch_pin = c->gpio_cd;
mmc->slots[0].gpio_wp = c->gpio_wp;
mmc->slots[0].remux = c->remux;
mmc->slots[0].init_card = c->init_card;
if (c->cover_only)
mmc->slots[0].cover = 1;
if (c->nonremovable)
mmc->slots[0].nonremovable = 1;
if (c->power_saving)
mmc->slots[0].power_saving = 1;
if (c->no_off)
mmc->slots[0].no_off = 1;
if (c->no_off_init)
mmc->slots[0].no_regulator_off_init = c->no_off_init;
if (c->vcc_aux_disable_is_sleep)
mmc->slots[0].vcc_aux_disable_is_sleep = 1;
if (cpu_is_omap44xx()) {
if (omap_rev() > OMAP4430_REV_ES1_0)
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
if (c->mmc >= 3 && c->mmc <= 5)
mmc->slots[0].features |= HSMMC_HAS_48MHZ_MASTER_CLK;
}
if (c->mmc_data) {
memcpy(&mmc->slots[0].mmc_data, c->mmc_data,
sizeof(struct mmc_platform_data));
mmc->slots[0].card_detect =
(mmc_card_detect_func)c->mmc_data->status;
}
/*
* NOTE: MMC slots should have a Vcc regulator set up.
* This may be from a TWL4030-family chip, another
* controllable regulator, or a fixed supply.
*
* temporary HACK: ocr_mask instead of fixed supply
*/
mmc->slots[0].ocr_mask = c->ocr_mask;
if (cpu_is_omap3517() || cpu_is_omap3505())
mmc->slots[0].set_power = nop_mmc_set_power;
else
mmc->slots[0].features |= HSMMC_HAS_PBIAS;
if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
switch (c->mmc) {
case 1:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* on-chip level shifting via PBIAS0/PBIAS1 */
if (cpu_is_omap44xx()) {
mmc->slots[0].before_set_reg =
omap4_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap4_hsmmc1_after_set_reg;
} else {
mmc->slots[0].before_set_reg =
omap_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap_hsmmc1_after_set_reg;
}
}
/* OMAP3630 HSMMC1 supports only 4-bit */
if (cpu_is_omap3630() &&
(c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
mmc->slots[0].caps = c->caps;
}
break;
case 2:
if (c->ext_clock)
c->transceiver = 1;
if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
}
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* off-chip level shifting, or none */
mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
mmc->slots[0].after_set_reg = NULL;
}
break;
case 3:
case 4:
case 5:
mmc->slots[0].before_set_reg = NULL;
mmc->slots[0].after_set_reg = NULL;
break;
default:
pr_err("MMC%d configuration not supported!\n", c->mmc);
kfree(hc_name);
return -ENODEV;
}
return 0;
}
void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
{
struct omap2_hsmmc_info *c;
int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
int i;
u32 reg;
int controller_cnt = 0;
printk(">>> omap2_hsmmc_init\n");
if (!cpu_is_omap44xx()) {
if (cpu_is_omap2430()) {
control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
}
else {
control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
}
}
else {
control_pbias_offset = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
reg = omap4_ctrl_pad_readl(control_mmc1);
reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
omap4_ctrl_pad_writel(reg, control_mmc1);
}
for (c = controllers; c->mmc; c++) {
struct hsmmc_controller *hc = hsmmc + controller_cnt;
struct omap_mmc_platform_data *mmc = hsmmc_data[controller_cnt];
if (!c->mmc || c->mmc > nr_hsmmc) {
printk("MMC%d: no such controller\n", c->mmc);
continue;
}
if (mmc) {
printk("MMC%d: already configured\n", c->mmc);
continue;
}
mmc = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
if (!mmc) {
pr_err("Cannot allocate memory for mmc device!\n");
goto done;
}
if (c->name)
strncpy(hc->name, c->name, HSMMC_NAME_LEN);
else
snprintf(hc->name, ARRAY_SIZE(hc->name),
"mmc%islot%i", c->mmc, 1);
#ifdef CONFIG_TIWLAN_SDIO
if (c->mmc == CONFIG_TIWLAN_MMC_CONTROLLER) {
mmc->slots[0].embedded_sdio = &omap_wifi_emb_data;
mmc->slots[0].register_status_notify = &omap_wifi_status_register;
mmc->slots[0].card_detect = &omap_wifi_status;
}
#endif
mmc->slots[0].name = hc->name;
mmc->nr_slots = 1;
mmc->slots[0].caps = c->caps;
mmc->slots[0].internal_clock = !c->ext_clock;
mmc->dma_mask = 0xffffffff;
/* Register offset Mapping */
if (cpu_is_omap44xx())
mmc->regs_map = (u16 *) omap4_mmc_reg_map;
else
mmc->regs_map = (u16 *) omap3_mmc_reg_map;
if (!cpu_is_omap44xx())
mmc->get_context_loss_count = hsmmc_get_context_loss;
//&*&*&*SJ1_20110607, Add SIM card detection.
#if defined (CONFIG_SIM_CARD_DETECTION) && defined (CONFIG_CHANGE_INAND_MMC_SCAN_INDEX)
mmc->slots[0].sim_switch_pin = c->gpio_sim_cd;
#endif
//&*&*&*SJ2_20110607, Add SIM card detection.
mmc->slots[0].switch_pin = c->gpio_cd;
mmc->slots[0].cd_active_high = c->cd_active_high;
mmc->slots[0].gpio_wp = c->gpio_wp;
mmc->slots[0].remux = c->remux;
if (c->cover_only)
mmc->slots[0].cover = 1;
if (c->nonremovable)
mmc->slots[0].nonremovable = 1;
if (c->power_saving)
mmc->slots[0].power_saving = 1;
if (c->no_off)
mmc->slots[0].no_off = 1;
if (c->vcc_aux_disable_is_sleep)
mmc->slots[0].vcc_aux_disable_is_sleep = 1;
/* NOTE: MMC slots should have a Vcc regulator set up.
* This may be from a TWL4030-family chip, another
* controllable regulator, or a fixed supply.
*
* temporary HACK: ocr_mask instead of fixed supply
*/
mmc->slots[0].ocr_mask = c->ocr_mask;
if (cpu_is_omap3517() || cpu_is_omap3505())
mmc->slots[0].set_power = nop_mmc_set_power;
else
mmc->slots[0].features |= HSMMC_HAS_PBIAS;
if (cpu_is_omap44xx()) {
if (omap_rev() > OMAP4430_REV_ES1_0)
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
mmc->slots[0].features |= HSMMC_DVFS_24MHZ_CONST;
if (c->mmc >= 3 && c->mmc <= 5) {
mmc->slots[0].features |= HSMMC_HAS_48MHZ_MASTER_CLK;
mmc->get_context_loss_count =
hsmmc_get_context_loss;
}
}
switch (c->mmc) {
case 1:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* on-chip level shifting via PBIAS0/PBIAS1 */
if (cpu_is_omap44xx()) {
mmc->slots[0].before_set_reg =
omap4_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap4_hsmmc1_after_set_reg;
}
else {
mmc->slots[0].before_set_reg =
omap_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap_hsmmc1_after_set_reg;
}
}
/* Omap3630 HSMMC1 supports only 4-bit */
if (cpu_is_omap3630() && (c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
mmc->slots[0].caps = c->caps;
}
break;
case 2:
if (c->ext_clock)
c->transceiver = 1;
if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
}
/* FALLTHROUGH */
case 3:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* off-chip level shifting, or none */
mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
mmc->slots[0].after_set_reg = NULL;
}
#ifdef CONFIG_TIWLAN_SDIO
mmc->slots[0].ocr_mask = MMC_VDD_165_195;
#endif
break;
case 4:
case 5:
/* TODO Update required */
mmc->slots[0].before_set_reg = NULL;
mmc->slots[0].after_set_reg = NULL;
#ifdef CONFIG_TIWLAN_SDIO
mmc->slots[0].ocr_mask = MMC_VDD_165_195;
#endif
break;
default:
pr_err("MMC%d configuration not supported!\n", c->mmc);
kfree(mmc);
continue;
}
hsmmc_data[controller_cnt] = mmc;
omap2_init_mmc(hsmmc_data[controller_cnt], c->mmc);
controller_cnt++;
}
/* pass the device nodes back to board setup code */
controller_cnt = 0;
for (c = controllers; c->mmc; c++) {
struct omap_mmc_platform_data *mmc = hsmmc_data[controller_cnt];
if (!c->mmc || c->mmc > nr_hsmmc)
continue;
c->dev = mmc->dev;
controller_cnt++;
}
done:
for (i = 0; i < controller_cnt; i++)
kfree(hsmmc_data[i]);
printk("<<< omap2_hsmmc_init\n");
}
static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
struct omap_mmc_platform_data *mmc)
{
char *hc_name;
hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
if (!hc_name) {
pr_err("Cannot allocate memory for controller slot name\n");
kfree(hc_name);
return -ENOMEM;
}
if (c->name)
strncpy(hc_name, c->name, HSMMC_NAME_LEN);
else
snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
c->mmc, 1);
//add mike.ma for wifi
#ifdef CONFIG_TIWLAN_SDIO
if (c->mmc == CONFIG_TIWLAN_MMC_CONTROLLER) {
mmc->slots[0].embedded_sdio = &omap_wifi_emb_data;
mmc->slots[0].register_status_notify = &omap_wifi_status_register;
mmc->slots[0].card_detect = &omap_wifi_status;
}
#endif
//
mmc->slots[0].name = hc_name;
mmc->nr_slots = 1;
mmc->slots[0].caps = c->caps;
mmc->slots[0].internal_clock = !c->ext_clock;
mmc->dma_mask = 0xffffffff;
if (cpu_is_omap44xx())
mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
else
mmc->reg_offset = 0;
//&*&*&*SJ1_20110607, Add SIM card detection.
#if defined (CONFIG_SIM_CARD_DETECTION) && defined (CONFIG_CHANGE_INAND_MMC_SCAN_INDEX)
mmc->slots[0].sim_switch_pin = c->gpio_sim_cd;
#endif
//&*&*&*SJ2_20110607, Add SIM card detection.
mmc->slots[0].switch_pin = c->gpio_cd;
mmc->slots[0].cd_active_high = c->cd_active_high;
mmc->slots[0].gpio_wp = c->gpio_wp;
mmc->slots[0].remux = c->remux;
mmc->slots[0].init_card = c->init_card;
if (c->cover_only)
mmc->slots[0].cover = 1;
if (c->nonremovable)
mmc->slots[0].nonremovable = 1;
if (c->power_saving)
mmc->slots[0].power_saving = 1;
if (c->no_off)
mmc->slots[0].no_off = 1;
if (c->no_off_init)
mmc->slots[0].no_regulator_off_init = c->no_off_init;
if (c->vcc_aux_disable_is_sleep)
mmc->slots[0].vcc_aux_disable_is_sleep = 1;
if (cpu_is_omap44xx()) {
if (omap_rev() > OMAP4430_REV_ES1_0)
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
if (c->mmc >= 3 && c->mmc <= 5)
mmc->slots[0].features |= HSMMC_HAS_48MHZ_MASTER_CLK;
}
if (c->mmc_data) {
memcpy(&mmc->slots[0].mmc_data, c->mmc_data,
sizeof(struct mmc_platform_data));
mmc->slots[0].card_detect =
(mmc_card_detect_func)c->mmc_data->status;
}
/*
* NOTE: MMC slots should have a Vcc regulator set up.
* This may be from a TWL4030-family chip, another
* controllable regulator, or a fixed supply.
*
* temporary HACK: ocr_mask instead of fixed supply
*/
mmc->slots[0].ocr_mask = c->ocr_mask;
if (cpu_is_omap3517() || cpu_is_omap3505())
mmc->slots[0].set_power = nop_mmc_set_power;
else
mmc->slots[0].features |= HSMMC_HAS_PBIAS;
if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
switch (c->mmc) {
case 1:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* on-chip level shifting via PBIAS0/PBIAS1 */
if (cpu_is_omap44xx()) {
mmc->slots[0].before_set_reg =
omap4_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap4_hsmmc1_after_set_reg;
} else {
mmc->slots[0].before_set_reg =
omap_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap_hsmmc1_after_set_reg;
}
}
/* OMAP3630 HSMMC1 supports only 4-bit */
if (cpu_is_omap3630() &&
(c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
mmc->slots[0].caps = c->caps;
}
break;
case 2:
if (c->ext_clock)
c->transceiver = 1;
if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
}
/* FALLTHROUGH */
case 3:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* off-chip level shifting, or none */
mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
mmc->slots[0].after_set_reg = NULL;
}
//add mike.ma
#ifdef CONFIG_TIWLAN_SDIO
mmc->slots[0].ocr_mask = MMC_VDD_165_195|MMC_VDD_20_21;
#endif
break;
case 4:
case 5:
mmc->slots[0].before_set_reg = NULL;
mmc->slots[0].after_set_reg = NULL;
//add mike.ma
#ifdef CONFIG_TIWLAN_SDIO
mmc->slots[0].ocr_mask = MMC_VDD_165_195;
#endif
break;
default:
pr_err("MMC%d configuration not supported!\n", c->mmc);
kfree(hc_name);
return -ENODEV;
}
return 0;
}
/* omap_start_ehc
* - Start the TI USBHOST controller
*/
static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
{
unsigned long timeout = jiffies + msecs_to_jiffies(1000);
u8 tll_ch_mask = 0;
unsigned reg = 0;
int ret = 0;
dev_dbg(omap->dev, "starting TI EHCI USB Controller\n");
/* Enable Clocks for USBHOST */
omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick");
if (IS_ERR(omap->usbhost_ick)) {
ret = PTR_ERR(omap->usbhost_ick);
goto err_host_ick;
}
clk_enable(omap->usbhost_ick);
omap->usbhost2_120m_fck = clk_get(omap->dev, "usbhost_120m_fck");
if (IS_ERR(omap->usbhost2_120m_fck)) {
ret = PTR_ERR(omap->usbhost2_120m_fck);
goto err_host_120m_fck;
}
clk_enable(omap->usbhost2_120m_fck);
omap->usbhost1_48m_fck = clk_get(omap->dev, "usbhost_48m_fck");
if (IS_ERR(omap->usbhost1_48m_fck)) {
ret = PTR_ERR(omap->usbhost1_48m_fck);
goto err_host_48m_fck;
}
clk_enable(omap->usbhost1_48m_fck);
if (omap->phy_reset) {
/* Refer: ISSUE1 */
if (gpio_is_valid(omap->reset_gpio_port[0])) {
gpio_request(omap->reset_gpio_port[0],
"USB1 PHY reset");
gpio_direction_output(omap->reset_gpio_port[0], 0);
}
if (gpio_is_valid(omap->reset_gpio_port[1])) {
gpio_request(omap->reset_gpio_port[1],
"USB2 PHY reset");
gpio_direction_output(omap->reset_gpio_port[1], 0);
}
/* Hold the PHY in RESET for enough time till DIR is high */
udelay(10);
}
/* Configure TLL for 60Mhz clk for ULPI */
omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck");
if (IS_ERR(omap->usbtll_fck)) {
ret = PTR_ERR(omap->usbtll_fck);
goto err_tll_fck;
}
clk_enable(omap->usbtll_fck);
omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick");
if (IS_ERR(omap->usbtll_ick)) {
ret = PTR_ERR(omap->usbtll_ick);
goto err_tll_ick;
}
clk_enable(omap->usbtll_ick);
/* perform TLL soft reset, and wait until reset is complete */
ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
OMAP_USBTLL_SYSCONFIG_SOFTRESET);
/* Wait for TLL reset to complete */
while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
& OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
cpu_relax();
if (time_after(jiffies, timeout)) {
dev_dbg(omap->dev, "operation timed out\n");
ret = -EINVAL;
goto err_sys_status;
}
}
dev_dbg(omap->dev, "TLL RESET DONE\n");
/* Enable smart-idle, wakeup */
reg = OMAP_USBTLL_SYSCONFIG_CACTIVITY
| OMAP_USBTLL_SYSCONFIG_AUTOIDLE
| OMAP_USBTLL_SYSCONFIG_ENAWAKEUP
| OMAP_USBTLL_SYSCONFIG_S_SMART_IDLE;
ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, reg);
/* Put UHH in smart Idle/Standby mode */
reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
reg |= OMAP_UHH_SYSCONFIG_CACTIVITY
| OMAP_UHH_SYSCONFIG_AUTOIDLE
| OMAP_UHH_SYSCONFIG_ENAWAKEUP;
reg &= ~(OMAP_UHH_SYSCONFIG_SIDLEMASK | OMAP_UHH_SYSCONFIG_MIDLEMASK);
reg |= OMAP_UHH_SYSCONFIG_S_SMART_IDLE
| OMAP_UHH_SYSCONFIG_M_SMART_STDBY;
ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
/* setup ULPI bypass and burst configurations */
reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
| OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
| OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
/* Bypass the TLL module for PHY mode operation */
if (!cpu_is_omap3517() && !cpu_is_omap3505() &&
(omap_rev() <= OMAP3430_REV_ES2_1)) {
dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1 \n");
if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) ||
(omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) ||
(omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY))
reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
else
reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
} else {
dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n");
if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY)
reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
else if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY)
reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
else if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY)
reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
else if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
}
ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) ||
(omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) ||
(omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) {
if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK;
if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK;
if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK;
/* Enable UTMI mode for required TLL channels */
omap_usb_utmi_init(omap, tll_ch_mask);
}
if (omap->phy_reset) {
/* Refer ISSUE1:
* Hold the PHY in RESET for enough time till
* PHY is settled and ready
*/
udelay(10);
if (gpio_is_valid(omap->reset_gpio_port[0]))
gpio_set_value(omap->reset_gpio_port[0], 1);
if (gpio_is_valid(omap->reset_gpio_port[1]))
gpio_set_value(omap->reset_gpio_port[1], 1);
}
return 0;
err_sys_status:
clk_disable(omap->usbtll_ick);
clk_put(omap->usbtll_ick);
err_tll_ick:
clk_disable(omap->usbtll_fck);
clk_put(omap->usbtll_fck);
err_tll_fck:
clk_disable(omap->usbhost1_48m_fck);
clk_put(omap->usbhost1_48m_fck);
if (omap->phy_reset) {
if (gpio_is_valid(omap->reset_gpio_port[0]))
gpio_free(omap->reset_gpio_port[0]);
if (gpio_is_valid(omap->reset_gpio_port[1]))
gpio_free(omap->reset_gpio_port[1]);
}
err_host_48m_fck:
clk_disable(omap->usbhost2_120m_fck);
clk_put(omap->usbhost2_120m_fck);
err_host_120m_fck:
clk_disable(omap->usbhost_ick);
clk_put(omap->usbhost_ick);
err_host_ick:
return ret;
}
void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
{
struct omap_hwmod *oh;
struct platform_device *pdev;
struct device *dev;
int bus_id = -1;
const char *oh_name, *name;
struct omap_musb_board_data *board_data;
if (musb_board_data)
board_data = musb_board_data;
else
board_data = &musb_default_board_data;
/*
* REVISIT: This line can be removed once all the platforms using
* musb_core.c have been converted to use use clkdev.
*/
musb_plat[0].clock = "ick";
musb_plat[0].board_data = board_data;
musb_plat[0].power = board_data->power >> 1;
musb_plat[0].mode = board_data->mode;
musb_plat[0].extvbus = board_data->extvbus;
/*
* OMAP3630/AM35x platform has MUSB RTL-1.8 which has the fix for the
* issue restricting active endpoints to use first 8K of FIFO space.
* This issue restricts OMAP35x platform to use fifo_mode '5'.
*/
if (cpu_is_omap3430())
musb_config.fifo_mode = 5;
if (cpu_is_omap3517() || cpu_is_omap3505()) {
oh_name = "am35x_otg_hs";
name = "musb-am35x";
} else if (cpu_is_ti81xx() || cpu_is_am33xx()) {
board_data->set_phy_power = ti81xx_musb_phy_power;
oh_name = "usb_otg_hs";
name = "musb-ti81xx";
} else {
oh_name = "usb_otg_hs";
name = "musb-omap2430";
}
oh = omap_hwmod_lookup(oh_name);
if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
__func__, oh_name))
return;
pdev = omap_device_build(name, bus_id, oh, &musb_plat,
sizeof(musb_plat), NULL, 0, false);
if (IS_ERR(pdev)) {
pr_err("Could not build omap_device for %s %s\n",
name, oh_name);
return;
}
dev = &pdev->dev;
get_device(dev);
dev->dma_mask = &musb_dmamask;
dev->coherent_dma_mask = musb_dmamask;
put_device(dev);
if (cpu_is_omap44xx())
omap4430_phy_init(dev);
}
static int omap_init_uhh_registers(struct ehci_hcd_omap *omap, struct usb_hcd *hcd)
{
unsigned long timeout = jiffies + msecs_to_jiffies(1000);
u8 tll_ch_mask = 0;
unsigned reg = 0;
/* perform TLL soft reset, and wait until reset is complete */
ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG,
OMAP_USBTLL_SYSCONFIG_SOFTRESET);
/* Wait for TLL reset to complete */
while (!(ehci_omap_readl(omap->tll_base, OMAP_USBTLL_SYSSTATUS)
& OMAP_USBTLL_SYSSTATUS_RESETDONE)) {
cpu_relax();
if (time_after(jiffies, timeout)) {
dev_dbg(omap->dev, "operation timed out\n");
return -EINVAL;
}
}
dev_dbg(omap->dev, "TLL RESET DONE\n");
/* Enable smart-idle, wakeup */
reg = OMAP_USBTLL_SYSCONFIG_CACTIVITY
| OMAP_USBTLL_SYSCONFIG_AUTOIDLE
| OMAP_USBTLL_SYSCONFIG_ENAWAKEUP
| OMAP_USBTLL_SYSCONFIG_SMARTIDLE;
ehci_omap_writel(omap->tll_base, OMAP_USBTLL_SYSCONFIG, reg);
/* Put UHH in NoIdle/NoStandby mode */
reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG);
reg |= OMAP_UHH_SYSCONFIG_CACTIVITY
| OMAP_UHH_SYSCONFIG_AUTOIDLE
| OMAP_UHH_SYSCONFIG_ENAWAKEUP;
reg &= ~(OMAP_UHH_SYSCONFIG_SIDLEMASK | OMAP_UHH_SYSCONFIG_MIDLEMASK);
reg |= OMAP_UHH_SYSCONFIG_NOIDLE
| OMAP_UHH_SYSCONFIG_NOSTDBY;
ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg);
reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG);
/* setup ULPI bypass and burst configurations */
reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN
| OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN
| OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN);
reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN;
if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN)
reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS;
if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN)
reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS;
if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN)
reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS;
/* Bypass the TLL module for PHY mode operation */
if (!cpu_is_omap3517() && !cpu_is_omap3505() &&
(omap_rev() <= OMAP3430_REV_ES2_1)) {
dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1 \n");
if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) ||
(omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) ||
(omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY))
reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
else
reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS;
} else {
dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n");
if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY)
reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
else if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS;
if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY)
reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
else if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS;
if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY)
reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
else if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS;
}
ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg);
dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg);
/*
* An undocumented "feature" in the OMAP3 EHCI controller,
* causes suspended ports to be taken out of suspend when
* the USBCMD.Run/Stop bit is cleared (for example when
* we do ehci_bus_suspend).
* This breaks suspend-resume if the root-hub is allowed
* to suspend. Writing 1 to this undocumented register bit
* disables this feature and restores normal behavior.
*/
ehci_omap_writel(omap->ehci_base, EHCI_INSNREG04,
EHCI_INSNREG04_DISABLE_UNSUSPEND);
if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) ||
(omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) ||
(omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)) {
if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL)
tll_ch_mask |= OMAP_TLL_CHANNEL_1_EN_MASK;
if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL)
tll_ch_mask |= OMAP_TLL_CHANNEL_2_EN_MASK;
if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL)
tll_ch_mask |= OMAP_TLL_CHANNEL_3_EN_MASK;
/* Enable UTMI mode for required TLL channels */
omap_usb_utmi_init(omap, tll_ch_mask);
}
if (omap->phy_reset) {
/* Refer ISSUE1:
* Hold the PHY in RESET for enough time till
* PHY is settled and ready
*/
udelay(10);
if (gpio_is_valid(omap->reset_gpio_port[0]))
gpio_set_value(omap->reset_gpio_port[0], 1);
if (gpio_is_valid(omap->reset_gpio_port[1]))
gpio_set_value(omap->reset_gpio_port[1], 1);
}
return 0;
}
static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
struct omap_mmc_platform_data *mmc)
{
char *hc_name;
hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
if (!hc_name) {
pr_err("Cannot allocate memory for controller slot name\n");
kfree(hc_name);
return -ENOMEM;
}
if (c->name)
strncpy(hc_name, c->name, HSMMC_NAME_LEN);
else
snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
c->mmc, 1);
mmc->slots[0].name = hc_name;
mmc->nr_slots = 1;
mmc->slots[0].caps = c->caps;
mmc->slots[0].pm_caps = c->pm_caps;
mmc->slots[0].internal_clock = !c->ext_clock;
mmc->dma_mask = 0xffffffff;
mmc->max_freq = c->max_freq;
if (cpu_is_omap44xx())
mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
else
mmc->reg_offset = 0;
mmc->get_context_loss_count = hsmmc_get_context_loss;
mmc->slots[0].switch_pin = c->gpio_cd;
mmc->slots[0].gpio_wp = c->gpio_wp;
mmc->slots[0].remux = c->remux;
mmc->slots[0].init_card = c->init_card;
if (c->cover_only)
mmc->slots[0].cover = 1;
if (c->nonremovable)
mmc->slots[0].nonremovable = 1;
if (c->power_saving)
mmc->slots[0].power_saving = 1;
if (c->no_off)
mmc->slots[0].no_off = 1;
if (c->no_off_init)
mmc->slots[0].no_regulator_off_init = c->no_off_init;
if (c->vcc_aux_disable_is_sleep)
mmc->slots[0].vcc_aux_disable_is_sleep = 1;
if (cpu_is_omap3505() || cpu_is_omap3517())
mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
MMC_VDD_26_27 |
MMC_VDD_27_28 |
MMC_VDD_29_30 |
MMC_VDD_30_31 |
MMC_VDD_31_32;
else
mmc->slots[0].ocr_mask = c->ocr_mask;
if (!cpu_is_omap3517() && !cpu_is_omap3505())
mmc->slots[0].features |= HSMMC_HAS_PBIAS;
if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
switch (c->mmc) {
case 1:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
if (cpu_is_omap44xx()) {
mmc->slots[0].before_set_reg =
omap4_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap4_hsmmc1_after_set_reg;
} else {
mmc->slots[0].before_set_reg =
omap_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap_hsmmc1_after_set_reg;
}
}
if (cpu_is_omap3517() || cpu_is_omap3505())
mmc->slots[0].set_power = nop_mmc_set_power;
if (cpu_is_omap3630() &&
(c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
mmc->slots[0].caps = c->caps;
}
break;
case 2:
if (cpu_is_omap3517() || cpu_is_omap3505())
mmc->slots[0].set_power = am35x_hsmmc2_set_power;
if (c->ext_clock)
c->transceiver = 1;
if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
}
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
mmc->slots[0].after_set_reg = NULL;
}
break;
case 3:
case 4:
case 5:
mmc->slots[0].before_set_reg = NULL;
mmc->slots[0].after_set_reg = NULL;
break;
default:
pr_err("MMC%d configuration not supported!\n", c->mmc);
kfree(hc_name);
return -ENODEV;
}
return 0;
}
static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
struct omap_mmc_platform_data *mmc)
{
char *hc_name;
unsigned long max_freq, min_freq;
hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
if (!hc_name) {
pr_err("Cannot allocate memory for controller slot name\n");
kfree(hc_name);
return -ENOMEM;
}
if (c->name)
strncpy(hc_name, c->name, HSMMC_NAME_LEN);
else
snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
c->mmc, 1);
mmc->slots[0].name = hc_name;
mmc->nr_slots = 1;
mmc->slots[0].caps = c->caps;
mmc->slots[0].caps |= omap_hsmmc_si_spec_caps(c);
mmc->slots[0].caps2 |= omap_hsmmc_si_spec_caps2(c);
mmc->slots[0].pm_caps = c->pm_caps;
mmc->slots[0].internal_clock = !c->ext_clock;
mmc->dma_mask = 0xffffffff;
mmc->set_clk_src = omap_hsmmc_set_clks_src;
if (omap_hsmmc_max_min(c->mmc - 1, &max_freq, &min_freq)) {
pr_err("Invalid mmc slot");
kfree(hc_name);
return -EINVAL;
}
if (c->max_freq > 0)
mmc->max_freq = min(c->max_freq, max_freq);
else
mmc->max_freq = max_freq;
mmc->max_si_freq = max_freq;
mmc->min_freq = min_freq;
if ((c->mmc <= 2) && (cpu_is_omap54xx())) {
mmc->opp_scale_init = omap_hsmmc_opp_scale_init;
mmc->opp_scale = omap_hsmmc_opp_scale;
mmc->opp_relax = omap_hsmmc_opp_relax;
}
if (cpu_is_omap44xx() || cpu_is_omap54xx())
mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
else
mmc->reg_offset = 0;
mmc->get_context_loss_count = hsmmc_get_context_loss;
mmc->slots[0].switch_pin = c->gpio_cd;
mmc->slots[0].gpio_wp = c->gpio_wp;
mmc->slots[0].remux = c->remux;
mmc->slots[0].init_card = c->init_card;
if (c->cover_only)
mmc->slots[0].cover = 1;
if (c->nonremovable)
mmc->slots[0].nonremovable = 1;
if (c->power_saving)
mmc->slots[0].power_saving = 1;
if (c->no_off)
mmc->slots[0].no_off = 1;
if (c->no_off_init)
mmc->slots[0].no_regulator_off_init = c->no_off_init;
if (c->vcc_aux_disable_is_sleep)
mmc->slots[0].vcc_aux_disable_is_sleep = 1;
/*
* NOTE: MMC slots should have a Vcc regulator set up.
* This may be from a TWL4030-family chip, another
* controllable regulator, or a fixed supply.
*
* temporary HACK: ocr_mask instead of fixed supply
*/
if (cpu_is_omap3505() || cpu_is_omap3517())
mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
MMC_VDD_26_27 |
MMC_VDD_27_28 |
MMC_VDD_29_30 |
MMC_VDD_30_31 |
MMC_VDD_31_32;
else
mmc->slots[0].ocr_mask = c->ocr_mask;
mmc->slots[0].built_in = c->built_in;
if (!cpu_is_omap3517() && !cpu_is_omap3505())
mmc->slots[0].features |= HSMMC_HAS_PBIAS;
if ((cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) ||
cpu_is_omap54xx())
mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
switch (c->mmc) {
case 1:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* on-chip level shifting via PBIAS0/PBIAS1 */
if (cpu_is_omap54xx()) {
mmc->slots[0].before_set_reg =
omap5_es2_before_set_reg;
mmc->slots[0].after_set_reg =
omap5_es2_after_set_reg;
omap_mux_get_by_name("sdcard_clk",
&mmc->slots[0].p_mmc_clk,
&mmc->slots[0].mux_mmc_clk);
mmc->slots[0].clk_pull_up = omap5_clk_pull_up;
} else if (cpu_is_omap44xx()) {
mmc->slots[0].before_set_reg =
omap4_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap4_hsmmc1_after_set_reg;
} else {
mmc->slots[0].before_set_reg =
omap_hsmmc1_before_set_reg;
mmc->slots[0].after_set_reg =
omap_hsmmc1_after_set_reg;
}
}
if (cpu_is_omap3517() || cpu_is_omap3505())
mmc->slots[0].set_power = nop_mmc_set_power;
/* OMAP3630 HSMMC1 supports only 4-bit */
if (cpu_is_omap3630() &&
(c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
mmc->slots[0].caps = c->caps;
}
break;
case 2:
if (cpu_is_omap3517() || cpu_is_omap3505())
mmc->slots[0].set_power = am35x_hsmmc2_set_power;
if (c->ext_clock)
c->transceiver = 1;
if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
}
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* off-chip level shifting, or none */
mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
mmc->slots[0].after_set_reg = NULL;
}
break;
case 3:
case 4:
case 5:
mmc->slots[0].before_set_reg = NULL;
mmc->slots[0].after_set_reg = NULL;
break;
default:
pr_err("MMC%d configuration not supported!\n", c->mmc);
kfree(hc_name);
return -ENODEV;
}
return 0;
}
