bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97) { unsigned long gsr; #ifdef CONFIG_PXA25x if (cpu_is_pxa25x()) pxa_ac97_warm_pxa25x(); else #endif #ifdef CONFIG_PXA27x if (cpu_is_pxa27x()) pxa_ac97_warm_pxa27x(); else #endif #ifdef CONFIG_PXA3xx if (cpu_is_pxa3xx()) pxa_ac97_warm_pxa3xx(); else #endif BUG(); gsr = GSR | gsr_bits; if (!(gsr & (GSR_PCR | GSR_SCR))) { printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n", __func__, gsr); return false; } return true; }
static void __init pxa_timer_init(void) { unsigned long clock_tick_rate; OIER = 0; OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; if (cpu_is_pxa21x() || cpu_is_pxa25x()) clock_tick_rate = 3686400; else if (machine_is_mainstone()) clock_tick_rate = 3249600; else clock_tick_rate = 3250000; set_oscr2ns_scale(clock_tick_rate); ckevt_pxa_osmr0.mult = div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); ckevt_pxa_osmr0.max_delta_ns = clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); ckevt_pxa_osmr0.min_delta_ns = clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1; cksrc_pxa_oscr0.mult = clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift); setup_irq(IRQ_OST0, &pxa_ost0_irq); clocksource_register(&cksrc_pxa_oscr0); clockevents_register_device(&ckevt_pxa_osmr0); }
bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97) { #ifdef CONFIG_PXA25x if (cpu_is_pxa25x()) pxa_ac97_cold_pxa25x(); else #endif #ifdef CONFIG_PXA27x if (cpu_is_pxa27x()) pxa_ac97_cold_pxa27x(); else #endif #ifdef CONFIG_PXA3xx if (cpu_is_pxa3xx()) pxa_ac97_cold_pxa3xx(); else #endif BUG(); if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) { printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n", __func__, gsr_bits); return false; } return true; }
static void __exit cmx2xx_pcmcia_exit(void) { if (machine_is_armcore() && cpu_is_pxa25x()) cmx255_pcmcia_exit(); else if (machine_is_armcore() && cpu_is_pxa27x()) cmx270_pcmcia_exit(); }
static int __init pxa25x_init(void) { int ret = 0; if (cpu_is_pxa25x()) { reset_status = RCSR; if ((ret = pxa_init_dma(IRQ_DMA, 16))) return ret; pxa25x_init_pm(); register_syscore_ops(&pxa_irq_syscore_ops); register_syscore_ops(&pxa2xx_mfp_syscore_ops); pxa2xx_set_dmac_info(16); pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info); ret = platform_add_devices(pxa25x_devices, ARRAY_SIZE(pxa25x_devices)); if (ret) return ret; } return ret; }
static void __init cmx2xx_map_io(void) { if (cpu_is_pxa25x()) pxa25x_map_io(); if (cpu_is_pxa27x()) pxa27x_map_io(); }
/* * Return the current memory clock frequency in units of 10kHz * Only pxa2xx_pcmcia device needs this API. */ unsigned int get_memclk_frequency_10khz(void) { if (cpu_is_pxa25x()) return pxa25x_get_memclk_frequency_10khz(); else if (cpu_is_pxa27x()) return pxa27x_get_memclk_frequency_10khz(); return 0; }
static void __init cmx2xx_init_dm9000(void) { if (cpu_is_pxa25x()) cmx2xx_dm9000_device.resource = cmx255_dm9000_resource; else cmx2xx_dm9000_device.resource = cmx270_dm9000_resource; platform_device_register(&cmx2xx_dm9000_device); }
/** * pxa_ssp_get_clkdiv - get SSP clock divider */ static u32 pxa_ssp_get_scr(struct ssp_device *ssp) { u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); u32 div; if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) div = ((sscr0 >> 8) & 0xff) * 2 + 2; else
unsigned int get_clk_frequency_khz(int info) { if (cpu_is_pxa25x()) return pxa25x_get_clk_frequency_khz(info); else if (cpu_is_pxa27x()) return pxa27x_get_clk_frequency_khz(info); return 0; }
/* * For non device-tree builds, keep legacy timer init */ void __init pxa_timer_init(void) { if (cpu_is_pxa25x()) pxa25x_clocks_init(); if (cpu_is_pxa27x()) pxa27x_clocks_init(); if (cpu_is_pxa3xx()) pxa3xx_clocks_init(); pxa_timer_nodt_init(IRQ_OST0, io_p2v(0x40a00000)); }
static void __init cmx2xx_init_irq(void) { if (cpu_is_pxa25x()) { pxa25x_init_irq(); cmx2xx_pci_init_irq(CMX255_GPIO_IT8152_IRQ); } else { pxa27x_init_irq(); cmx2xx_pci_init_irq(CMX270_GPIO_IT8152_IRQ); } }
static int __init cmx2xx_pcmcia_init(void) { int ret = -ENODEV; if (machine_is_armcore() && cpu_is_pxa25x()) ret = cmx255_pcmcia_init(); else if (machine_is_armcore() && cpu_is_pxa27x()) ret = cmx270_pcmcia_init(); return ret; }
static void __init cmx2xx_init_leds(void) { if (cpu_is_pxa25x()) { cmx2xx_leds[0].gpio = CMX255_GPIO_RED; cmx2xx_leds[1].gpio = CMX255_GPIO_GREEN; } else { cmx2xx_leds[0].gpio = CMX270_GPIO_RED; cmx2xx_leds[1].gpio = CMX270_GPIO_GREEN; } platform_device_register(&cmx2xx_led_device); }
static void __init cmx2xx_map_io(void) { if (cpu_is_pxa25x()) pxa25x_map_io(); if (cpu_is_pxa27x()) pxa27x_map_io(); iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc)); it8152_base_address = CMX2XX_IT8152_VIRT; }
int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev) { int ret; if (cpu_is_pxa25x() || cpu_is_pxa27x()) { pxa_gpio_mode(GPIO31_SYNC_AC97_MD); pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); } if (cpu_is_pxa27x()) { /* Use GPIO 113 as AC97 Reset on Bulverde */ pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK"); if (IS_ERR(ac97conf_clk)) { ret = PTR_ERR(ac97conf_clk); ac97conf_clk = NULL; goto err_conf; } } ac97_clk = clk_get(&dev->dev, "AC97CLK"); if (IS_ERR(ac97_clk)) { ret = PTR_ERR(ac97_clk); ac97_clk = NULL; goto err_clk; } ret = clk_enable(ac97_clk); if (ret) goto err_clk2; ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL); if (ret < 0) goto err_irq; return 0; err_irq: GCR |= GCR_ACLINK_OFF; err_clk2: clk_put(ac97_clk); ac97_clk = NULL; err_clk: if (ac97conf_clk) { clk_put(ac97conf_clk); ac97conf_clk = NULL; } err_conf: return ret; }
/** * ssp_set_clkdiv - set SSP clock divider * @div: serial clock rate divider */ static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div) { u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0); if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) { sscr0 &= ~0x0000ff00; sscr0 |= ((div - 2)/2) << 8; /* 2..512 */ } else { sscr0 &= ~0x000fff00; sscr0 |= (div - 1) << 8; /* 1..4096 */ } pxa_ssp_write_reg(ssp, SSCR0, sscr0); }
unsigned long get_clock_tick_rate(void) { unsigned long clock_tick_rate; if (cpu_is_pxa25x()) clock_tick_rate = 3686400; else if (machine_is_mainstone()) clock_tick_rate = 3249600; else clock_tick_rate = 3250000; return clock_tick_rate; }
int pxa2xx_ac97_hw_resume(void) { if (cpu_is_pxa25x() || cpu_is_pxa27x()) { pxa_gpio_mode(GPIO31_SYNC_AC97_MD); pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); } if (cpu_is_pxa27x()) { /* Use GPIO 113 or 95 as AC97 Reset on Bulverde */ set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC); } clk_enable(ac97_clk); return 0; }
int pxa2xx_ac97_hw_resume(void) { if (cpu_is_pxa25x() || cpu_is_pxa27x()) { pxa_gpio_mode(GPIO31_SYNC_AC97_MD); pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); } if (cpu_is_pxa27x()) { /* Use GPIO 113 as AC97 Reset on Bulverde */ pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT); } clk_enable(ac97_clk); return 0; }
static void __init cmx2xx_init(void) { cmx2xx_pm_init(); if (cpu_is_pxa25x()) cmx255_init(); else cmx270_init(); cmx2xx_init_dm9000(); cmx2xx_init_display(); cmx2xx_init_ac97(); cmx2xx_init_touchscreen(); cmx2xx_init_leds(); }
static int __init pxa25x_mfp_init(void) { int i; if (cpu_is_pxa25x()) { for (i = 0; i <= 84; i++) gpio_desc[i].valid = 1; for (i = 0; i <= 15; i++) { gpio_desc[i].can_wakeup = 1; gpio_desc[i].mask = GPIO_bit(i); } } return 0; }
static void __init cmx2xx_init(void) { pxa_set_ffuart_info(NULL); pxa_set_btuart_info(NULL); pxa_set_stuart_info(NULL); cmx2xx_pm_init(); if (cpu_is_pxa25x()) cmx255_init(); else cmx270_init(); cmx2xx_init_dm9000(); cmx2xx_init_display(); cmx2xx_init_ac97(); cmx2xx_init_touchscreen(); cmx2xx_init_leds(); }
static int __init pxa2xx_mfp_init(void) { int i; if (!cpu_is_pxa2xx()) return 0; if (cpu_is_pxa25x()) pxa25x_mfp_init(); if (cpu_is_pxa27x()) pxa27x_mfp_init(); PSSR = PSSR_RDH; for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) gpdr_lpm[i] = GPDR(i * 32); return 0; }
static int __init pxa2xx_mfp_init(void) { int i; if (!cpu_is_pxa2xx()) return 0; if (cpu_is_pxa25x()) pxa25x_mfp_init(); if (cpu_is_pxa27x()) pxa27x_mfp_init(); /* clear RDH bit to enable GPIO receivers after reset/sleep exit */ PSSR = PSSR_RDH; /* initialize gafr_run[], pgsr_lpm[] from existing values */ for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) gpdr_lpm[i] = GPDR(i * 32); return 0; }
unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg) { unsigned short val = -1; volatile u32 *reg_addr; mutex_lock(&car_mutex); /* set up primary or secondary codec space */ if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS) reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; else reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; reg_addr += (reg >> 1); /* start read access across the ac97 link */ GSR = GSR_CDONE | GSR_SDONE; gsr_bits = 0; val = *reg_addr; if (reg == AC97_GPIO_STATUS) goto out; if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 && !((GSR | gsr_bits) & GSR_SDONE)) { printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n", __func__, reg, GSR | gsr_bits); val = -1; goto out; } /* valid data now */ GSR = GSR_CDONE | GSR_SDONE; gsr_bits = 0; val = *reg_addr; /* but we've just started another cycle... */ wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1); out: mutex_unlock(&car_mutex); return val; }
void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val) { volatile u32 *reg_addr; mutex_lock(&car_mutex); /* set up primary or secondary codec space */ if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS) reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE; else reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE; reg_addr += (reg >> 1); GSR = GSR_CDONE | GSR_SDONE; gsr_bits = 0; *reg_addr = val; if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 && !((GSR | gsr_bits) & GSR_CDONE)) printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n", __func__, reg, GSR | gsr_bits); mutex_unlock(&car_mutex); }
int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev) { int ret; struct pxa2xx_ac97_platform_data *pdata = dev->dev.platform_data; if (pdata) { switch (pdata->reset_gpio) { case 95: case 113: reset_gpio = pdata->reset_gpio; break; case 0: reset_gpio = 113; break; case -1: break; default: dev_err(&dev->dev, "Invalid reset GPIO %d\n", pdata->reset_gpio); } } else { if (cpu_is_pxa27x()) reset_gpio = 113; } if (cpu_is_pxa25x() || cpu_is_pxa27x()) { pxa_gpio_mode(GPIO31_SYNC_AC97_MD); pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD); pxa_gpio_mode(GPIO28_BITCLK_AC97_MD); pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD); } if (cpu_is_pxa27x()) { /* Use GPIO 113 as AC97 Reset on Bulverde */ set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC); ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK"); if (IS_ERR(ac97conf_clk)) { ret = PTR_ERR(ac97conf_clk); ac97conf_clk = NULL; goto err_conf; } } ac97_clk = clk_get(&dev->dev, "AC97CLK"); if (IS_ERR(ac97_clk)) { ret = PTR_ERR(ac97_clk); ac97_clk = NULL; goto err_clk; } ret = clk_enable(ac97_clk); if (ret) goto err_clk2; ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL); if (ret < 0) goto err_irq; return 0; err_irq: GCR |= GCR_ACLINK_OFF; err_clk2: clk_put(ac97_clk); ac97_clk = NULL; err_clk: if (ac97conf_clk) { clk_put(ac97conf_clk); ac97conf_clk = NULL; } err_conf: return ret; }
static inline int cpu_has_ipr(void) { return !cpu_is_pxa25x(); }