static int identify_omap(void) { unsigned int id_code; if (mem_read(ID_CODE, &id_code) != 0) return OMAPCONF_ERR_REG_ACCESS; dprintf("%s(): ID_CODE = 0x%08X\n", __func__, id_code); switch (id_code) { case OMAP5432_ES_2_0_ID_CODE: cpu_set(OMAP_5432); cpu_revision_set(REV_ES2_0); break; case OMAP5432_ES_1_0_ID_CODE: cpu_set(OMAP_5432); cpu_revision_set(REV_ES1_0); break; case OMAP5430_ES_2_0_ID_CODE: cpu_set(OMAP_5430); cpu_revision_set(REV_ES2_0); break; case OMAP5430_ES_1_0_ID_CODE: case 0x0000002F: /* Zebu */ cpu_set(OMAP_5430); cpu_revision_set(REV_ES1_0); break; case OMAP4470_ES_1_0_ID_CODE: cpu_set(OMAP_4470); cpu_revision_set(REV_ES1_0); break; case OMAP4460_ES_1_1_ID_CODE: cpu_set(OMAP_4460); cpu_revision_set(REV_ES1_1); break; case OMAP4460_ES_1_0_ID_CODE: cpu_set(OMAP_4460); cpu_revision_set(REV_ES1_0); break; case OMAP4430_ES_2_3_ID_CODE: cpu_set(OMAP_4430); cpu_revision_set(REV_ES2_3); break; case OMAP4430_ES_2_2_ID_CODE: cpu_set(OMAP_4430); cpu_revision_set(REV_ES2_2); break; case OMAP4430_ES_2_1_ID_CODE: cpu_set(OMAP_4430); cpu_revision_set(REV_ES2_1); break; case OMAP4430_ES_2_0_ID_CODE: case OMAP4430_ES_1_0_ID_CODE: /* * Due to fusing issue between ES1.0 and ES2.0 (same code...), * revision cannot be correctly detected. * Workaround is to use Cortex-A9 own revision code, which did * changed, but it is not accessible from user space... * Only way is to use /proc/cpuinfo. */ cpu_set(OMAP_4430); cpu_rev_get_from_cpuinfo(&cpu_rev); switch (cpu_rev) { case REV_ES2_0: cpu_revision_set(REV_ES2_0); break; case REV_ES1_0: cpu_revision_set(REV_ES1_0); break; default: dprintf("%s(): unknown ARM Cortex-A9!\n", __func__); return OMAPCONF_ERR_UNEXPECTED; } break; default: /* Retrieve DRA7 chip & ES in default case */ if (mem_read(DRA7_ID_CODE, &id_code) != 0) return OMAPCONF_ERR_REG_ACCESS; dprintf("%s(): ID_CODE = 0x%08X\n", __func__, id_code); switch (id_code) { case DRA72X_ES_1_0_ID_CODE: cpu_set(DRA_72X); cpu_revision_set(REV_ES1_0); break; case DRA74X_ES_1_1_ID_CODE: cpu_set(DRA_75X); cpu_revision_set(REV_ES1_1); break; case DRA74X_ES_1_0_ID_CODE: cpu_set(DRA_75X); cpu_revision_set(REV_ES1_0); break; case DRA74X_ES_2_0_ID_CODE: cpu_set(DRA_75X); cpu_revision_set(REV_ES2_0); break; default: dprintf("%s(): OMAP ID CODE not recognized! (0x%08X)\n", __func__, id_code); return OMAPCONF_ERR_CPU; } } return 0; }
/* ------------------------------------------------------------------------*//** * @FUNCTION cpu_detect * @BRIEF Detect cpu and set internal global variables accordingly * @RETURNS 0 on success * OMAPCONF_ERR_UNEXPECTED * OMAPCONF_ERR_CPU if cpu not recognized * OMAPCONF_ERR_REG_ACCESS * @param[in] none * @DESCRIPTION Detect cpu and set internal global variables accordingly *//*------------------------------------------------------------------------ */ int cpu_detect(void) { unsigned int id_code; unsigned int status; unsigned int prod_id_1; #ifdef CPUID_DEBUG char s[CPU_FULL_NAME_MAX_LENGTH]; char rev_s[CPU_REVISION_MAX_NAME_LENGTH]; char dev_type_s[CPU_DEVICE_TYPE_MAX_NAME_LENGTH]; #endif /* Init variables */ cpu_init(); /* Retrieve OMAP chip & ES */ if (mem_read(ID_CODE, &id_code) != 0) return OMAPCONF_ERR_REG_ACCESS; dprintf("%s(): ID_CODE = 0x%08X\n", __func__, id_code); switch (id_code) { case OMAP5432_ES_1_0_ID_CODE: cpu_set(OMAP_5432); cpu_revision_set(REV_ES1_0); break; case OMAP5430_ES_1_0_ID_CODE: case 0x0000002F: /* Zebu */ cpu_set(OMAP_5430); cpu_revision_set(REV_ES1_0); break; case OMAP4470_ES_1_0_ID_CODE: cpu_set(OMAP_4470); cpu_revision_set(REV_ES1_0); break; case OMAP4460_ES_1_1_ID_CODE: cpu_set(OMAP_4460); cpu_revision_set(REV_ES1_1); break; case OMAP4460_ES_1_0_ID_CODE: cpu_set(OMAP_4460); cpu_revision_set(REV_ES1_0); break; case OMAP4430_ES_2_3_ID_CODE: cpu_set(OMAP_4430); cpu_revision_set(REV_ES2_3); break; case OMAP4430_ES_2_2_ID_CODE: cpu_set(OMAP_4430); cpu_revision_set(REV_ES2_2); break; case OMAP4430_ES_2_1_ID_CODE: cpu_set(OMAP_4430); cpu_revision_set(REV_ES2_1); break; case OMAP4430_ES_2_0_ID_CODE: case OMAP4430_ES_1_0_ID_CODE: /* * Due to fusing issue between ES1.0 and ES2.0 (same code...), * revision cannot be correctly detected. * Workaround is to use Cortex-A9 own revision code, which did * changed, but it is not accessible from user space... * Only way is to use /proc/cpuinfo. */ cpu_set(OMAP_4430); cpu_rev_get_from_cpuinfo(&cpu_rev); switch (cpu_rev) { case REV_ES2_0: cpu_revision_set(REV_ES2_0); break; case REV_ES1_0: cpu_revision_set(REV_ES1_0); break; default: dprintf("%s(): unknown ARM Cortex-A9!\n", __func__); return OMAPCONF_ERR_UNEXPECTED; } break; default: dprintf("%s(): OMAP ID CODE not recognized! (0x%08X)\n", __func__, id_code); return OMAPCONF_ERR_CPU; } dprintf("%s(): Chip is %s ES%s\n", __func__, cpu_gets(s), cpu_revision_gets(rev_s)); /* Retrieve device type */ if (mem_read(OMAP44XX_STATUS, &status) != 0) return OMAPCONF_ERR_REG_ACCESS; dprintf("%s(): OMAP44XX_STATUS = 0x%08X\n", __func__, status); switch (extract_bitfield(status, 8, 2)) { case 3: cpu_device_type_set(DEV_GP); break; case 2: cpu_device_type_set(DEV_HS); break; case 1: cpu_device_type_set(DEV_EMU); break; default: cpu_device_type_set(DEV_TEST); } dprintf("%s(): Device Type is %s\n", __func__, cpu_device_type_gets(dev_type_s)); /* Retrieve silicon performance type from EFuse */ if (mem_read(CONTROL_STD_FUSE_PROD_ID_1, &prod_id_1) != 0) { fprintf(stderr, "omapconf (%s()): could not read CONTROL_STD_FUSE_PROD_ID_1 register!\n", __func__); return OMAPCONF_ERR_REG_ACCESS; } dprintf("%s(): CONTROL_STD_FUSE_PROD_ID_1 = 0x%08X\n", __func__, prod_id_1); si_type = (silicon_type) extract_bitfield(prod_id_1, 16, 2); dprintf("%s(): Silicon performance type is %s (%uMHz)\n", __func__, cpu_silicon_type_gets(s), cpu_silicon_max_speed_get()); /* Set CPU full name */ cpu_full_name_set(); dprintf("%s(): CPU full name is %s\n", __func__, cpu_full_name); return 0; }