static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup)
{
	u32 validatedStep=step;
	int err;
	
	if (mali_step_lock > -1 && step != mali_step_lock) {
		step = mali_step_lock;
	}

#ifdef CONFIG_REGULATOR
	if (mali_regulator_get_usecount() == 0) {
		MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n"));
		return MALI_FALSE;
	}
#endif

	if (boostup) {
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
	} else {
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
	}

#ifdef EXYNOS4_ASV_ENABLED
#ifndef CONFIG_ABB_CONTROL
	if (samsung_rev() < EXYNOS4412_REV_2_0) {
		if (mali_dvfs[step].clock == 160)
			exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V);
		else
			exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V);
	}
#else
	abb_target(ABB_G3D, mali_dvfs[step].clock*1000);
#endif
#endif


	set_mali_dvfs_current_step(validatedStep);
	/*for future use*/
	maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep];

#if CPUFREQ_LOCK_DURING_440
	/* lock/unlock CPU freq by Mali */
	if (mali_dvfs[step].clock == 440)
		err = cpufreq_lock_by_mali(1200);
	else
		cpufreq_unlock_by_mali();
#endif

	return MALI_TRUE;
}
示例#2
0
int change_dvfs_tableset(int change_clk, int change_step)
{
	int err;

	if (change_clk < mali_dvfs_all[1].clock) {
		mali_dvfs[change_step].clock = mali_dvfs_all[0].clock;
	} else if (change_clk < mali_dvfs_all[2].clock && change_clk >= mali_dvfs_all[1].clock) {
		mali_dvfs[change_step].clock = mali_dvfs_all[1].clock;
	} else if (change_clk < mali_dvfs_all[3].clock && change_clk >= mali_dvfs_all[2].clock) {
		mali_dvfs[change_step].clock = mali_dvfs_all[2].clock;
	} else {
		mali_dvfs[change_step].clock = mali_dvfs_all[3].clock;
	}

	MALI_PRINT((":::mali dvfs step %d clock and voltage = %d Mhz, %d V\n",change_step, mali_dvfs[change_step].clock, mali_dvfs[change_step].vol));

	if (maliDvfsStatus.currentStep == change_step) {
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[change_step].vol, mali_dvfs[change_step].vol);
#endif
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[change_step].clock, mali_dvfs[change_step].freq);

#if CPUFREQ_LOCK_DURING_440
		/* lock/unlock CPU freq by Mali */
		if (mali_dvfs[change_step].clock == 440)
			err = cpufreq_lock_by_mali(1200);
		else
			cpufreq_unlock_by_mali();
#endif
	}

	return mali_dvfs[change_step].clock;
}
示例#3
0
static _mali_osk_errcode_t disable_mali_clocks(void)
{
	clk_disable(mali_clock);
	MALI_DEBUG_PRINT(3,("disable_mali_clocks mali_clock %p \n", mali_clock));
	
	cpufreq_unlock_by_mali();
	MALI_SUCCESS;
}
示例#4
0
static _mali_osk_errcode_t disable_mali_clocks(void)
{
	clk_disable(mali_clock);
	MALI_DEBUG_PRINT(3,("disable_mali_clocks mali_clock %p \n", mali_clock));

#if MALI_DVFS_ENABLED && CPUFREQ_LOCK_DURING_440
	/* lock/unlock CPU freq by Mali */
	cpufreq_unlock_by_mali();
#endif
	MALI_SUCCESS;
}
static _mali_osk_errcode_t disable_mali_clocks(void)
{
	clk_disable(mali_clock);
	MALI_DEBUG_PRINT(3,("disable_mali_clocks mali_clock %p \n", mali_clock));

	/* to reflect the gpu clock off status */
	mali_gpu_clk_on = mali_gpu_clk;
	mali_gpu_clk = 0;
#if MALI_DVFS_ENABLED
	/* lock/unlock CPU freq by Mali */
	cpufreq_unlock_by_mali();
#endif
	MALI_SUCCESS;
}
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup)
{
	u32 validatedStep=step;
	int err;

#ifdef CONFIG_REGULATOR
	if (mali_regulator_get_usecount() == 0) {
		MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n"));
		return MALI_FALSE;
	}
#endif

	if (boostup) {
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
	} else {
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
	}

#ifdef EXYNOS4_ASV_ENABLED
	if (mali_dvfs[step].clock == 160)
		exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V);
	else
		exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V);
#endif


	set_mali_dvfs_current_step(validatedStep);
	/*for future use*/
	maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep];

	/* lock/unlock CPU freq by Mali */
	if (mali_dvfs[step].clock >= 533)
		err = cpufreq_lock_by_mali(1400);
	else if (mali_dvfs[step].clock == 440)
		err = cpufreq_lock_by_mali(1200);
	else
		cpufreq_unlock_by_mali();

	return MALI_TRUE;
}
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup)
{
	u32 validatedStep=step;
	int err;

#ifdef CONFIG_REGULATOR
	if (mali_regulator_get_usecount() == 0) {
		MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n"));
		return MALI_FALSE;
	}
#endif

	if (boostup) {
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
	} else {
		/*change the clock*/
		mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
#ifdef CONFIG_REGULATOR
		/*change the voltage*/
		mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
	}

	set_mali_dvfs_current_step(validatedStep);
	/*for future use*/
	maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep];

#if CPUFREQ_LOCK_DURING_440
	/* lock/unlock CPU freq by Mali */
	if (mali_dvfs[step].clock >= 533)
		err = cpufreq_lock_by_mali(1200);
	else if (mali_dvfs[step].clock == 440)
		err = cpufreq_lock_by_mali(1000);
	else
		cpufreq_unlock_by_mali();
#endif

	return MALI_TRUE;
}
示例#8
0
static unsigned int decideNextStatus(unsigned int utilization)
{
    static unsigned int level = 0; // 0:stay, 1:up

    if (mali_runtime_resumed >= 0) {
        level = mali_runtime_resumed;
        mali_runtime_resumed = -1;
        return level;
    }

    if (mali_dvfs_threshold[maliDvfsStatus.currentStep].upthreshold
            <= mali_dvfs_threshold[maliDvfsStatus.currentStep].downthreshold) {
        MALI_PRINT(("upthreadshold is smaller than downthreshold: %d < %d\n",
                    mali_dvfs_threshold[maliDvfsStatus.currentStep].upthreshold,
                    mali_dvfs_threshold[maliDvfsStatus.currentStep].downthreshold));
        return level;
    }

    if (utilization > (int)(255 * mali_dvfs_threshold[maliDvfsStatus.currentStep].upthreshold / 100) &&
            level < MALI_DVFS_STEPS - 1) {
        level++;
    }
    if (utilization < (int)(255 * mali_dvfs_threshold[maliDvfsStatus.currentStep].downthreshold / 100) &&
            level > 0) {
        level--;
    }

    if (_mali_osk_atomic_read(&bottomlock_status) > 0) {
        if (level < bottom_lock_step)
            level = bottom_lock_step;
    }
    /* lock/unlock CPU freq by Mali */
    if (mali_dvfs[level].clock >= 300)
        cpufreq_lock_by_mali(800);
    else {
        cpufreq_unlock_by_mali();
    }
    return level;
}
static int mali_devfreq_target(struct device *dev, unsigned long *freq, u32 flags)
{
	unsigned int nextStatus = (unsigned int)*freq;
	unsigned int curStatus = 0;

	curStatus = maliDvfsStatus.currentStep;

	MALI_DEBUG_PRINT(4, ("= curStatus %d, nextStatus %d, maliDvfsStatus.currentStep %d\n", curStatus, nextStatus, maliDvfsStatus.currentStep));

	/*if next status is same with current status, don't change anything*/
	if (curStatus != nextStatus) {
#if MALI_DVFS_CLK_DEBUG
		unsigned int *pRegMaliClkDiv;
		unsigned int *pRegMaliMpll;
#endif
		if (nextStatus > curStatus) {
#ifdef CONFIG_MALI_DVFS
			update_time_in_state(curStatus);
#endif
#ifdef CONFIG_REGULATOR
			/*change the voltage*/
			mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
			exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
#endif
			/*change the clock*/
			mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq);
		} else if (nextStatus < curStatus) {
#ifdef CONFIG_MALI_DVFS
			update_time_in_state(curStatus);
#endif
			/*change the clock*/
			mali_clk_set_rate(mali_dvfs[nextStatus].clock, mali_dvfs[nextStatus].freq);
#ifdef CONFIG_REGULATOR
			/*change the voltage*/
			mali_regulator_set_voltage(get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT), get_match_volt(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
			exynos_set_abb(ID_G3D, get_match_abb(ID_G3D, mali_dvfs[nextStatus].clock * GPU_ASV_VOLT));
#endif
		} else
			return 0;

#if defined(CONFIG_MALI400_PROFILING)
		_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE|
				MALI_PROFILING_EVENT_CHANNEL_GPU|
				MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE,
				mali_gpu_clk, mali_gpu_vol/1000, 0, 0, 0);
#endif
		mali_clk_put(MALI_FALSE);

#if MALI_DVFS_CLK_DEBUG
		pRegMaliClkDiv = ioremap(0x1003c52c, 32);
		pRegMaliMpll = ioremap(0x1003c22c, 32);
		MALI_PRINT(("Mali MPLL reg:%d, CLK DIV: %d \n", *pRegMaliMpll, *pRegMaliClkDiv));
#endif
		set_mali_dvfs_current_step(nextStatus);
		/*for future use*/
		maliDvfsStatus.pCurrentDvfs = &mali_dvfs[nextStatus];

#if CPUFREQ_LOCK_DURING_440
		/* lock/unlock CPU freq by Mali */
		if (mali_dvfs[nextStatus].clock >= 440)
			cpufreq_lock_by_mali(400);
		else
			cpufreq_unlock_by_mali();
#endif
		/*wait until clock and voltage is stablized*/
		mali_platform_wating(MALI_DVFS_WATING); /*msec*/
	}

	return 0;
}