static MACHINE_RESET( kinst ) { /* set the fastest DRC options */ cpunum_set_info_int(0, CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS); /* configure fast RAM regions for DRC */ cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_START, 0x08000000); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_END, 0x087fffff); cpunum_set_info_ptr(0, CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase2); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_END, 0x0007ffff); cpunum_set_info_ptr(0, CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_SELECT, 2); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff); cpunum_set_info_ptr(0, CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1); /* keep the DCS held in reset at startup */ dcs_reset_w(1); /* reset the IDE controller */ ide_controller_reset(0); /* set a safe base location for video */ video_base = &rambase[0x30000/4]; }
static MACHINE_INIT( blockhl ) { unsigned char *RAM = memory_region(REGION_CPU1); cpunum_set_info_ptr(0, CPUINFO_PTR_KONAMI_SETLINES_CALLBACK, (void *)blockhl_banking); paletteram = &RAM[0x18000]; }
static MACHINE_INIT( crimfght ) { unsigned char *RAM = memory_region(REGION_CPU1); cpunum_set_info_ptr(0, CPUINFO_PTR_KONAMI_SETLINES_CALLBACK, (void *)crimfght_banking); /* init the default bank */ cpu_setbank( 2, &RAM[0x10000] ); }
static MACHINE_INIT( parodius ) { unsigned char *RAM = memory_region(REGION_CPU1); cpunum_set_info_ptr(0, CPUINFO_PTR_KONAMI_SETLINES_CALLBACK, (void *)parodius_banking); paletteram = &memory_region(REGION_CPU1)[0x48000]; videobank = 0; /* init the default bank */ cpu_setbank(1,&RAM[0x10000]); }