static int tmu_timer_init(void)
{
unsigned long interval;
setup_irq(TIMER_IRQ, &tmu_irq);
tmu0_clk.parent = clk_get("module_clk");
/* Start TMU0 */
ctrl_outb(0, TMU_TSTR);
#if !defined(CONFIG_CPU_SUBTYPE_SH7300) && !defined(CONFIG_CPU_SUBTYPE_SH7760)
ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
#endif
clk_register(&tmu0_clk);
clk_enable(&tmu0_clk);
interval = (clk_get_rate(&tmu0_clk) + HZ / 2) / HZ;
printk(KERN_INFO "Interval = %ld\n", interval);
ctrl_outl(interval, TMU0_TCOR);
ctrl_outl(interval, TMU0_TCNT);
ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
return 0;
}
static int set_rtc_mmss(unsigned long nowtime)
{
int retval = 0;
int real_seconds, real_minutes, cmos_minutes;
int i;
/* gets recalled with irq locally disabled */
spin_lock(&rtc_lock);
for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */
if (!(ctrl_inb(RTC_CTL) & RTC_BUSY))
break;
cmos_minutes = (ctrl_inb(RTC_MIN1) & 0xf) + (ctrl_inb(RTC_MIN10) & 0xf) * 10;
real_seconds = nowtime % 60;
real_minutes = nowtime / 60;
if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
real_minutes += 30; /* correct for half hour time zone */
real_minutes %= 60;
if (abs(real_minutes - cmos_minutes) < 30) {
BIN_TO_BCD(real_seconds);
BIN_TO_BCD(real_minutes);
ctrl_outb(real_seconds % 10, RTC_SEC1);
ctrl_outb(real_seconds / 10, RTC_SEC10);
ctrl_outb(real_minutes % 10, RTC_MIN1);
ctrl_outb(real_minutes / 10, RTC_MIN10);
} else {
printk(KERN_WARNING
"set_rtc_mmss: can't update from %d to %d\n",
cmos_minutes, real_minutes);
retval = -1;
}
spin_unlock(&rtc_lock);
return retval;
}
static void ec3104_keyb_interrupt(int irq, void *data, struct pt_regs *regs)
{
struct e5_struct *k = &ec3104_keyb;
u8 msr, lsr;
msr = ctrl_inb(EC3104_SER4_MSR);
if ((msr & MSR_CTS) && !(k->last_msr & MSR_CTS)) {
if (k->cached_mcr & MCR_RTS)
printk("confused: RTS already high\n");
/* CTS went high. Send RTS. */
k->cached_mcr |= MCR_RTS;
ctrl_outb(k->cached_mcr, EC3104_SER4_MCR);
} else if ((!(msr & MSR_CTS)) && (k->last_msr & MSR_CTS)) {
/* CTS went low. */
if (!(k->cached_mcr & MCR_RTS))
printk("confused: RTS already low\n");
k->cached_mcr &= ~MCR_RTS;
ctrl_outb(k->cached_mcr, EC3104_SER4_MCR);
}
k->last_msr = msr;
lsr = ctrl_inb(EC3104_SER4_LSR);
if (lsr & LSR_DR)
e5_receive(k);
}
static int hp620_japanese_scan_kbd(unsigned char *s)
{
int i;
unsigned char matrix_switch[] = {
0xfd, 0xff, /* PTD1 */
0xdf, 0xff, /* PTD5 */
0x7f, 0xff, /* PTD7 */
0xff, 0xfe, /* PTE0 */
0xff, 0xfd, /* PTE1 */
0xff, 0xf7, /* PTE3 */
0xff, 0xbf, /* PTE6 */
0xff, 0x7f, /* PTE7 */
}, *t=matrix_switch;
for(i=0; i<8; i++) {
ctrl_outb(*t++, PDDR);
ctrl_outb(*t++, PEDR);
udelay(50);
*s++=ctrl_inb(PCDR);
*s++=ctrl_inb(PFDR);
}
ctrl_outb(0xff, PDDR);
ctrl_outb(0xff, PEDR);
*s++=ctrl_inb(PGDR);
*s++=ctrl_inb(PHDR);
return 0;
}
static void setup_fast_timer()
{
unsigned long interval;
#ifdef FAST_POLL_INTR
interval = (current_cpu_data.module_clock/4 + FAST_POLL/2) / FAST_POLL;
make_ipr_irq(FASTTIMER_IRQ, FASTTIMER_IPR_ADDR, FASTTIMER_IPR_POS,
FASTTIMER_PRIORITY);
printk("SnapGear: %dHz fast timer on IRQ %d\n",FAST_POLL,FASTTIMER_IRQ);
if (request_irq(FASTTIMER_IRQ, fast_timer_irq, 0, "SnapGear fast timer",
NULL) != 0)
printk("%s(%d): request_irq() failed?\n", __FILE__, __LINE__);
#else
printk("SnapGear: fast timer running\n",FAST_POLL,FASTTIMER_IRQ);
interval = 0xffffffff;
#endif
ctrl_outb(ctrl_inb(TMU_TSTR) & ~0x2, TMU_TSTR); /* disable timer 1 */
ctrl_outw(TMU1_TCR_INIT, TMU1_TCR);
ctrl_outl(interval, TMU1_TCOR);
ctrl_outl(interval, TMU1_TCNT);
ctrl_outb(ctrl_inb(TMU_TSTR) | 0x2, TMU_TSTR); /* enable timer 1 */
printk("Timer count 1 = 0x%x\n", fast_timer_count());
udelay(1000);
printk("Timer count 2 = 0x%x\n", fast_timer_count());
}
void __init platform_timer_setup(irqreturn_t (*timer_int)(int, void *, struct pt_regs *))
{
/* setup 8bit timer ch2 */
ctrl_outb(H8300_TIMER_FREQ / HZ, TCORA2); /* set interval */
ctrl_outb(0x00, _8TCSR2); /* no output */
request_irq(40, timer_int, 0, "timer", 0);
ctrl_outb(CMIEA|CCLR_CMA|CLK_DIV8192, _8TCR2); /* start count */
}
void titan_outb(u8 value, unsigned long port)
{
if (PXSEG(port))
ctrl_outb(value, port);
else if (is_pci_ioaddr(port))
ctrl_outb(value, pci_ioaddr(port));
else
ctrl_outw(value, port2adr(port));
}
void landisk_outb_p(u8 value, unsigned long port)
{
if (PXSEG(port))
ctrl_outb(value, port);
else if (is_pci_ioaddr(port))
ctrl_outb(value, pci_ioaddr(port));
else
ctrl_outw(value, port2adr(port));
ctrl_delay();
}
void __init platform_timer_setup(irqreturn_t (*timer_int)(int, void *, struct pt_regs *))
{
/* 8bit timer module enabled */
ctrl_outb(ctrl_inb(MSTPCRL) & ~0x01, MSTPCRL);
/* setup 8bit timer ch1 */
ctrl_outb(H8300_TIMER_FREQ / HZ, _8TCORA1); /* set interval */
ctrl_outb(0x00, _8TCSR1); /* no output */
request_irq(76, timer_int, 0, "timer" ,0);
ctrl_outb(CMIEA|CCLR_CMA|CLK_DIV8192, _8TCR1); /* start count */
}
void __init sh7290_setup(void)
{
printk(KERN_INFO "Hitachi SH7290 processor support.\n");
ctrl_outb(0x00, STBCR);
ctrl_outb(0x00, STBCR2);
ctrl_outb(0x00, STBCR3);
ctrl_outb(0x00, STBCR4);
ctrl_outb(0x00, STBCR5);
}
void hs7751rvoip_outb(unsigned char value, unsigned long port)
{
if (PXSEG(port))
ctrl_outb(value, port);
else if (codec_port(port))
ctrl_outb(value, CODEC_IOMAP(port));
else if (is_pci_ioaddr(port) || shifted_port(port))
ctrl_outb(value, pci_ioaddr(port));
else
ctrl_outb(value, port2adr(port));
}
/*
* Hah! We'll see if this works (switching from usecs to nsecs).
*/
static unsigned long tmu_timer_get_frequency(void)
{
u32 freq;
struct timespec ts1, ts2;
unsigned long diff_nsec;
unsigned long factor;
/* Setup the timer: We don't want to generate interrupts, just
* have it count down at its natural rate.
*/
ctrl_outb(0, TMU_TSTR);
#if !defined(CONFIG_CPU_SUBTYPE_SH7300) && !defined(CONFIG_CPU_SUBTYPE_SH7760)
ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
#endif
ctrl_outw(TMU0_TCR_CALIB, TMU0_TCR);
ctrl_outl(0xffffffff, TMU0_TCOR);
ctrl_outl(0xffffffff, TMU0_TCNT);
rtc_get_time(&ts2);
do {
rtc_get_time(&ts1);
} while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
/* actually start the timer */
ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
do {
rtc_get_time(&ts2);
} while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
freq = 0xffffffff - ctrl_inl(TMU0_TCNT);
if (ts2.tv_nsec < ts1.tv_nsec) {
ts2.tv_nsec += 1000000000;
ts2.tv_sec--;
}
diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec);
/* this should work well if the RTC has a precision of n Hz, where
* n is an integer. I don't think we have to worry about the other
* cases. */
factor = (1000000000 + diff_nsec/2) / diff_nsec;
if (factor * diff_nsec > 1100000000 ||
factor * diff_nsec < 900000000)
panic("weird RTC (diff_nsec %ld)", diff_nsec);
return freq * factor;
}
static int hp6x0_pm_enter(suspend_state_t state)
{
u8 stbcr, stbcr2;
#ifdef CONFIG_HD64461_ENABLER
u8 scr;
u16 hd64461_stbcr;
#endif
if (state != PM_SUSPEND_MEM)
return -EINVAL;
#ifdef CONFIG_HD64461_ENABLER
outb(0, HD64461_PCC1CSCIER);
scr = inb(HD64461_PCC1SCR);
scr |= HD64461_PCCSCR_VCC1;
outb(scr, HD64461_PCC1SCR);
hd64461_stbcr = inw(HD64461_STBCR);
hd64461_stbcr |= HD64461_STBCR_SPC1ST;
outw(hd64461_stbcr, HD64461_STBCR);
#endif
ctrl_outb(0x1f, DACR);
stbcr = ctrl_inb(STBCR);
ctrl_outb(0x01, STBCR);
stbcr2 = ctrl_inb(STBCR2);
ctrl_outb(0x7f , STBCR2);
outw(0xf07f, HD64461_SCPUCR);
pm_enter();
outw(0, HD64461_SCPUCR);
ctrl_outb(stbcr, STBCR);
ctrl_outb(stbcr2, STBCR2);
#ifdef CONFIG_HD64461_ENABLER
hd64461_stbcr = inw(HD64461_STBCR);
hd64461_stbcr &= ~HD64461_STBCR_SPC1ST;
outw(hd64461_stbcr, HD64461_STBCR);
outb(0x4c, HD64461_PCC1CSCIER);
outb(0x00, HD64461_PCC1CSCR);
#endif
return 0;
}
/* For SH7707, SH7709, SH7709A, SH7729, SH7300*/
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
{
unsigned int fcr_val = 0;
#if !defined(CONFIG_CPU_SUBTYPE_SH7300) /* SH7300 doesn't use RTS/CTS */
{
unsigned short data;
/* We need to set SCPCR to enable RTS/CTS */
data = ctrl_inw(SCPCR);
/* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
ctrl_outw(data&0x0fcf, SCPCR);
}
if (cflag & CRTSCTS)
fcr_val |= SCFCR_MCE;
else {
unsigned short data;
/* We need to set SCPCR to enable RTS/CTS */
data = ctrl_inw(SCPCR);
/* Clear out SCP7MD1,0, SCP4MD1,0,
Set SCP6MD1,0 = {01} (output) */
ctrl_outw((data&0x0fcf)|0x1000, SCPCR);
data = ctrl_inb(SCPDR);
/* Set /RTS2 (bit6) = 0 */
ctrl_outb(data&0xbf, SCPDR);
}
#endif
sci_out(port, SCFCR, fcr_val);
}
void __init h8300_timer_setup(void)
{
unsigned int div;
unsigned int cnt;
calc_param(cnt, div, divide_rate, 0x10000);
setup_irq(ITUIRQ, &itu_irq);
/* initalize timer */
ctrl_outb(0, TSTR);
ctrl_outb(CCLR0 | div, ITUBASE + TCR);
ctrl_outb(0x01, ITUBASE + TIER);
ctrl_outw(cnt, ITUBASE + GRA);
ctrl_bset(CONFIG_H8300_ITU_CH, TSTR);
}
void __init h8300_timer_setup(void)
{
unsigned int div;
unsigned int cnt;
calc_param(cnt, div, divide_rate, 0x10000);
setup_irq(_16IRQ, &timer16_irq);
/* initalize timer */
ctrl_outb(0, TSTR);
ctrl_outb(CCLR0 | div, _16BASE + TCR);
ctrl_outw(cnt, _16BASE + GRA);
ctrl_bset(4 + CONFIG_H8300_TIMER16_CH, TISRA);
ctrl_bset(CONFIG_H8300_TIMER16_CH, TSTR);
}
/* For SH7707, SH7709, SH7709A, SH7729 */
static void sci_init_pins_scif(struct sci_port* port, unsigned int cflag)
{
unsigned int fcr_val = 0;
{
unsigned short data;
/* We need to set SCPCR to enable RTS/CTS */
data = ctrl_inw(SCPCR);
/* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
ctrl_outw(data&0x0fcf, SCPCR);
}
if (cflag & CRTSCTS)
fcr_val |= SCFCR_MCE;
else {
unsigned short data;
/* We need to set SCPCR to enable RTS/CTS */
data = ctrl_inw(SCPCR);
/* Clear out SCP7MD1,0, SCP4MD1,0,
Set SCP6MD1,0 = {01} (output) */
ctrl_outw((data&0x0fcf)|0x1000, SCPCR);
data = ctrl_inb(SCPDR);
/* Set /RTS2 (bit6) = 0 */
ctrl_outb(data&0xbf, SCPDR);
}
sci_out(port, SCFCR, fcr_val);
}
static int __init h8300h_intc_of_init(struct device_node *intc,
struct device_node *parent)
{
struct irq_domain *domain;
intc_baseaddr = of_iomap(intc, 0);
BUG_ON(!intc_baseaddr);
/* All interrupt priority low */
ctrl_outb(0x00, IPR + 0);
ctrl_outb(0x00, IPR + 1);
domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL);
BUG_ON(!domain);
irq_set_default_host(domain);
return 0;
}
static int __init cf_init_se(void)
{
if ((ctrl_inw(MRSHPC_CSR) & 0x000c) != 0)
return 0; /* Not detected */
if ((ctrl_inw(MRSHPC_CSR) & 0x0080) == 0) {
ctrl_outw(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */
} else {
ctrl_outw(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */
}
/*
* PC-Card window open
* flag == COMMON/ATTRIBUTE/IO
*/
/* common window open */
ctrl_outw(0x8a84, MRSHPC_MW0CR1);/* window 0xb8400000 */
if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
/* common mode & bus width 16bit SWAP = 1*/
ctrl_outw(0x0b00, MRSHPC_MW0CR2);
else
/* common mode & bus width 16bit SWAP = 0*/
ctrl_outw(0x0300, MRSHPC_MW0CR2);
/* attribute window open */
ctrl_outw(0x8a85, MRSHPC_MW1CR1);/* window 0xb8500000 */
if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
/* attribute mode & bus width 16bit SWAP = 1*/
ctrl_outw(0x0a00, MRSHPC_MW1CR2);
else
/* attribute mode & bus width 16bit SWAP = 0*/
ctrl_outw(0x0200, MRSHPC_MW1CR2);
/* I/O window open */
ctrl_outw(0x8a86, MRSHPC_IOWCR1);/* I/O window 0xb8600000 */
ctrl_outw(0x0008, MRSHPC_CDCR); /* I/O card mode */
if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0)
ctrl_outw(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/
else
ctrl_outw(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/
ctrl_outw(0x2000, MRSHPC_ICR);
ctrl_outb(0x00, PA_MRSHPC_MW2 + 0x206);
ctrl_outb(0x42, PA_MRSHPC_MW2 + 0x200);
return 0;
}
void titan_outb_p(u8 value, unsigned long port)
{
if (PXSEG(port))
ctrl_outb(value, port);
else
ctrl_outw(value, port2adr(port));
ctrl_delay();
}
static void __init landisk_setup(char **cmdline_p)
{
/* LED ON */
ctrl_outb(ctrl_inb(PA_LED) | 0x03, PA_LED);
printk(KERN_INFO "I-O DATA DEVICE, INC. \"LANDISK Series\" support.\n");
pm_power_off = landisk_power_off;
}
static void dac_audio_stop_timer(void)
{
u8 tstr;
tstr = ctrl_inb(TMU_TSTR);
tstr &= ~TMU1_TSTR_INIT;
ctrl_outb(tstr, TMU_TSTR);
}
void rts7751r2d_writeb(u8 b, void __iomem *addr)
{
unsigned long tmp = (unsigned long __force)addr;
if (is_ide_ioaddr(tmp))
ctrl_outw((u16)b, tmp);
else
ctrl_outb(b, tmp);
}
void debug_led_disp(void)
{
unsigned short value;
value = (unsigned char)debug_counter++;
ctrl_outb((0xf0|value), PA_OUTPORTR);
if (value == 0x0f)
debug_counter = 0;
}
static void hp690_japanese_scan_kbd(unsigned char *s)
{
int i;
unsigned const char *t=hp690_switch;
for(i=0; i<9; i++) {
ctrl_outb(*t++, PDDR);
ctrl_outb(*t++, PEDR);
*s++=ctrl_inb(PCDR);
*s++=ctrl_inb(PFDR);
}
ctrl_outb(0xff, PDDR);
ctrl_outb(0xff, PEDR);
*s++=ctrl_inb(PGDR);
*s++=ctrl_inb(PHDR);
}
int pci_fixup_pcic(void)
{
ctrl_outl(0x00000001, SH7780_PCI_VCR2);
/* Enable all interrupts, so we know what to fix */
pci_write_reg(0x0000C3FF, SH7780_PCIIMR);
pci_write_reg(0x0000380F, SH7780_PCIAINTM);
/* Set up standard PCI config registers */
ctrl_outw(0xFB00, PCI_REG(SH7780_PCISTATUS));
ctrl_outw(0x0047, PCI_REG(SH7780_PCICMD));
ctrl_outb( 0x00, PCI_REG(SH7780_PCIPIF));
ctrl_outb( 0x00, PCI_REG(SH7780_PCISUB));
ctrl_outb( 0x06, PCI_REG(SH7780_PCIBCC));
ctrl_outw(0x1912, PCI_REG(SH7780_PCISVID));
ctrl_outw(0x0001, PCI_REG(SH7780_PCISID));
pci_write_reg(0x08000000, SH7780_PCIMBAR0); /* PCI */
pci_write_reg(0x08000000, SH7780_PCILAR0); /* SHwy */
pci_write_reg(0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
pci_write_reg(0x00000000, SH7780_PCIMBAR1);
pci_write_reg(0x00000000, SH7780_PCILAR1);
pci_write_reg(0x00000000, SH7780_PCILSR1);
pci_write_reg(0xAB000801, SH7780_PCIIBAR);
/*
* Set the MBR so PCI address is one-to-one with window,
* meaning all calls go straight through... use ifdef to
* catch erroneous assumption.
*/
pci_write_reg(0xFD000000 , SH7780_PCIMBR0);
pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
/* Set IOBR for window containing area specified in pci.h */
pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR);
pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR);
pci_write_reg(0xA5000C01, SH7780_PCICR);
return 0;
}
static void ec3104_keyb_clear_state(void)
{
struct e5_struct *k = &ec3104_keyb;
u8 msr, lsr;
/* we want CTS to be low */
k->last_msr = 0;
for (;;) {
msleep(100);
msr = ctrl_inb(EC3104_SER4_MSR);
lsr = ctrl_inb(EC3104_SER4_LSR);
if (lsr & LSR_DR) {
e5_receive(k);
continue;
}
if ((msr & MSR_CTS) && !(k->last_msr & MSR_CTS)) {
if (k->cached_mcr & MCR_RTS)
printk("confused: RTS already high\n");
/* CTS went high. Send RTS. */
k->cached_mcr |= MCR_RTS;
ctrl_outb(k->cached_mcr, EC3104_SER4_MCR);
} else if ((!(msr & MSR_CTS)) && (k->last_msr & MSR_CTS)) {
/* CTS went low. */
if (!(k->cached_mcr & MCR_RTS))
printk("confused: RTS already low\n");
k->cached_mcr &= ~MCR_RTS;
ctrl_outb(k->cached_mcr, EC3104_SER4_MCR);
} else
break;
k->last_msr = msr;
continue;
}
}
static void do_softint(struct work_struct *work)
{
int absx = 0, absy = 0;
u8 scpdr;
int touched = 0;
if (ctrl_inb(PHDR) & PHDR_TS_PEN_DOWN) {
scpdr = ctrl_inb(SCPDR);
scpdr |= SCPDR_TS_SCAN_ENABLE;
scpdr &= ~SCPDR_TS_SCAN_Y;
ctrl_outb(scpdr, SCPDR);
udelay(30);
absy = adc_single(ADC_CHANNEL_TS_Y);
scpdr = ctrl_inb(SCPDR);
scpdr |= SCPDR_TS_SCAN_Y;
scpdr &= ~SCPDR_TS_SCAN_X;
ctrl_outb(scpdr, SCPDR);
udelay(30);
absx = adc_single(ADC_CHANNEL_TS_X);
scpdr = ctrl_inb(SCPDR);
scpdr |= SCPDR_TS_SCAN_X;
scpdr &= ~SCPDR_TS_SCAN_ENABLE;
ctrl_outb(scpdr, SCPDR);
udelay(100);
touched = ctrl_inb(PHDR) & PHDR_TS_PEN_DOWN;
}
if (touched) {
input_report_key(hp680_ts_dev, BTN_TOUCH, 1);
input_report_abs(hp680_ts_dev, ABS_X, absx);
input_report_abs(hp680_ts_dev, ABS_Y, absy);
} else {
input_report_key(hp680_ts_dev, BTN_TOUCH, 0);
}
input_sync(hp680_ts_dev);
enable_irq(HP680_TS_IRQ);
}
void __init h8300_timer_setup(void)
{
unsigned int cnt;
unsigned int div;
calc_param(cnt, div, divide_rate, 0x10000);
setup_irq(TPUIRQ, &tpu_irq);
/* TPU module enabled */
ctrl_bclr(3, MSTPCRH);
ctrl_outb(0, TSTR);
ctrl_outb(CCLR0 | div, TPUBASE + _TCR);
ctrl_outb(0, TPUBASE + _TMDR);
ctrl_outw(0, TPUBASE + _TIOR);
ctrl_outb(0x01, TPUBASE + _TIER);
ctrl_outw(cnt, TPUBASE + _GRA);
ctrl_bset(CONFIG_H8300_TPU_CH, TSTR);
}
static int pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
int pll;
unsigned char val;
unsigned long flags;
struct pll_clock *pll_clock = to_pll_clock(hw);
pll = ((rate / parent_rate) / 2) & 0x03;
spin_lock_irqsave(&clklock, flags);
val = ctrl_inb((unsigned long)pll_clock->sckcr);
val |= 0x08;
ctrl_outb(val, (unsigned long)pll_clock->sckcr);
val = ctrl_inb((unsigned long)pll_clock->pllcr);
val &= ~0x03;
val |= pll;
ctrl_outb(val, (unsigned long)pll_clock->pllcr);
spin_unlock_irqrestore(&clklock, flags);
return 0;
}
