static int epu_debug_irq(struct cx18 *cx, struct cx18_epu_work_order *order) { u32 str_offset; char *str = order->str; str[0] = '\0'; str_offset = order->mb.args[1]; if (str_offset) { cx18_setup_page(cx, str_offset); cx18_memcpy_fromio(cx, str, cx->enc_mem + str_offset, 252); str[252] = '\0'; cx18_setup_page(cx, SCB_OFFSET); } if ((order->flags & CX18_F_EWO_MB_STALE) == 0) mb_ack_irq(cx, order); return str_offset ? 1 : 0; }
static int load_cpu_fw_direct(const char *fn, u8 __iomem *mem, struct cx18 *cx) { const struct firmware *fw = NULL; int i, j; unsigned size; u32 __iomem *dst = (u32 __iomem *)mem; const u32 *src; if (request_firmware(&fw, fn, &cx->pci_dev->dev)) { CX18_ERR("Unable to open firmware %s\n", fn); CX18_ERR("Did you put the firmware in the hotplug firmware directory?\n"); return -ENOMEM; } src = (const u32 *)fw->data; for (i = 0; i < fw->size; i += 4096) { cx18_setup_page(cx, i); for (j = i; j < fw->size && j < i + 4096; j += 4) { /* no need for endianness conversion on the ppc */ cx18_raw_writel(cx, *src, dst); if (cx18_raw_readl(cx, dst) != *src) { CX18_ERR("Mismatch at offset %x\n", i); release_firmware(fw); cx18_setup_page(cx, 0); return -EIO; } dst++; src++; } } if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags)) CX18_INFO("loaded %s firmware (%zd bytes)\n", fn, fw->size); size = fw->size; release_firmware(fw); cx18_setup_page(cx, SCB_OFFSET); return size; }
long cx18_mb_ack(struct cx18 *cx, const struct cx18_mailbox *mb) { const struct cx18_api_info *info = find_api_info(mb->cmd); struct cx18_mailbox __iomem *ack_mb; u32 ack_irq; u8 rpu = CPU; if (info == NULL && mb->cmd) { CX18_WARN("Cannot ack unknown command %x\n", mb->cmd); return -EINVAL; } if (info) rpu = info->rpu; switch (rpu) { case HPU: ack_irq = IRQ_EPU_TO_HPU_ACK; ack_mb = &cx->scb->hpu2epu_mb; break; case APU: ack_irq = IRQ_EPU_TO_APU_ACK; ack_mb = &cx->scb->apu2epu_mb; break; case CPU: ack_irq = IRQ_EPU_TO_CPU_ACK; ack_mb = &cx->scb->cpu2epu_mb; break; default: CX18_WARN("Unknown RPU for command %x\n", mb->cmd); return -EINVAL; } cx18_setup_page(cx, SCB_OFFSET); cx18_write_sync(cx, mb->request, &ack_mb->ack); cx18_write_reg(cx, ack_irq, SW2_INT_SET); return 0; }
static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[]) { const struct cx18_api_info *info = find_api_info(cmd); u32 state = 0, irq = 0, req, oldreq, err; struct cx18_mailbox __iomem *mb; wait_queue_head_t *waitq; int timeout = 100; int cnt = 0; int sig = 0; int i; if (info == NULL) { CX18_WARN("unknown cmd %x\n", cmd); return -EINVAL; } if (cmd == CX18_CPU_DE_SET_MDL) CX18_DEBUG_HI_API("%s\n", info->name); else CX18_DEBUG_API("%s\n", info->name); cx18_setup_page(cx, SCB_OFFSET); mb = cx18_mb_is_complete(cx, info->rpu, &state, &irq, &req); if (mb == NULL) { CX18_ERR("mb %s busy\n", info->name); return -EBUSY; } oldreq = req - 1; cx18_writel(cx, cmd, &mb->cmd); for (i = 0; i < args; i++) cx18_writel(cx, data[i], &mb->args[i]); cx18_writel(cx, 0, &mb->error); cx18_writel(cx, req, &mb->request); switch (info->rpu) { case APU: waitq = &cx->mb_apu_waitq; break; case CPU: waitq = &cx->mb_cpu_waitq; break; case EPU: waitq = &cx->mb_epu_waitq; break; case HPU: waitq = &cx->mb_hpu_waitq; break; default: return -EINVAL; } if (info->flags & API_FAST) timeout /= 2; cx18_write_reg(cx, irq, SW1_INT_SET); while (!sig && cx18_readl(cx, &mb->ack) != cx18_readl(cx, &mb->request) && cnt < 660) { if (cnt > 200 && !in_atomic()) sig = cx18_msleep_timeout(10, 1); cnt++; } if (sig) return -EINTR; if (cnt == 660) { cx18_writel(cx, oldreq, &mb->request); CX18_ERR("mb %s failed\n", info->name); return -EINVAL; } for (i = 0; i < MAX_MB_ARGUMENTS; i++) data[i] = cx18_readl(cx, &mb->args[i]); err = cx18_readl(cx, &mb->error); if (!in_atomic() && (info->flags & API_SLOW)) cx18_msleep_timeout(300, 0); if (err) CX18_DEBUG_API("mailbox error %08x for command %s\n", err, info->name); return err ? -EIO : 0; }
static int load_apu_fw_direct(const char *fn, u8 __iomem *dst, struct cx18 *cx, u32 *entry_addr) { const struct firmware *fw = NULL; int i, j; unsigned size; const u32 *src; struct cx18_apu_rom_seghdr seghdr; const u8 *vers; u32 offset = 0; u32 apu_version = 0; int sz; if (request_firmware(&fw, fn, &cx->pci_dev->dev)) { CX18_ERR("unable to open firmware %s\n", fn); CX18_ERR("did you put the firmware in the hotplug firmware directory?\n"); cx18_setup_page(cx, 0); return -ENOMEM; } *entry_addr = 0; src = (const u32 *)fw->data; vers = fw->data + sizeof(seghdr); sz = fw->size; apu_version = (vers[0] << 24) | (vers[4] << 16) | vers[32]; while (offset + sizeof(seghdr) < fw->size) { /* TODO: byteswapping */ memcpy(&seghdr, src + offset / 4, sizeof(seghdr)); offset += sizeof(seghdr); if (seghdr.sync1 != APU_ROM_SYNC1 || seghdr.sync2 != APU_ROM_SYNC2) { offset += seghdr.size; continue; } CX18_DEBUG_INFO("load segment %x-%x\n", seghdr.addr, seghdr.addr + seghdr.size - 1); if (*entry_addr == 0) *entry_addr = seghdr.addr; if (offset + seghdr.size > sz) break; for (i = 0; i < seghdr.size; i += 4096) { cx18_setup_page(cx, seghdr.addr + i); for (j = i; j < seghdr.size && j < i + 4096; j += 4) { /* no need for endianness conversion on the ppc */ cx18_raw_writel(cx, src[(offset + j) / 4], dst + seghdr.addr + j); if (cx18_raw_readl(cx, dst + seghdr.addr + j) != src[(offset + j) / 4]) { CX18_ERR("Mismatch at offset %x\n", offset + j); release_firmware(fw); cx18_setup_page(cx, 0); return -EIO; } } } offset += seghdr.size; } if (!test_bit(CX18_F_I_LOADED_FW, &cx->i_flags)) CX18_INFO("loaded %s firmware V%08x (%zd bytes)\n", fn, apu_version, fw->size); size = fw->size; release_firmware(fw); cx18_setup_page(cx, 0); return size; }
void cx18_init_scb(struct cx18 *cx) { cx18_setup_page(cx, SCB_OFFSET); cx18_memset_io(cx, cx->scb, 0, 0x10000); cx18_writel(cx, IRQ_APU_TO_CPU, &cx->scb->apu2cpu_irq); cx18_writel(cx, IRQ_CPU_TO_APU_ACK, &cx->scb->cpu2apu_irq_ack); cx18_writel(cx, IRQ_HPU_TO_CPU, &cx->scb->hpu2cpu_irq); cx18_writel(cx, IRQ_CPU_TO_HPU_ACK, &cx->scb->cpu2hpu_irq_ack); cx18_writel(cx, IRQ_PPU_TO_CPU, &cx->scb->ppu2cpu_irq); cx18_writel(cx, IRQ_CPU_TO_PPU_ACK, &cx->scb->cpu2ppu_irq_ack); cx18_writel(cx, IRQ_EPU_TO_CPU, &cx->scb->epu2cpu_irq); cx18_writel(cx, IRQ_CPU_TO_EPU_ACK, &cx->scb->cpu2epu_irq_ack); cx18_writel(cx, IRQ_CPU_TO_APU, &cx->scb->cpu2apu_irq); cx18_writel(cx, IRQ_APU_TO_CPU_ACK, &cx->scb->apu2cpu_irq_ack); cx18_writel(cx, IRQ_HPU_TO_APU, &cx->scb->hpu2apu_irq); cx18_writel(cx, IRQ_APU_TO_HPU_ACK, &cx->scb->apu2hpu_irq_ack); cx18_writel(cx, IRQ_PPU_TO_APU, &cx->scb->ppu2apu_irq); cx18_writel(cx, IRQ_APU_TO_PPU_ACK, &cx->scb->apu2ppu_irq_ack); cx18_writel(cx, IRQ_EPU_TO_APU, &cx->scb->epu2apu_irq); cx18_writel(cx, IRQ_APU_TO_EPU_ACK, &cx->scb->apu2epu_irq_ack); cx18_writel(cx, IRQ_CPU_TO_HPU, &cx->scb->cpu2hpu_irq); cx18_writel(cx, IRQ_HPU_TO_CPU_ACK, &cx->scb->hpu2cpu_irq_ack); cx18_writel(cx, IRQ_APU_TO_HPU, &cx->scb->apu2hpu_irq); cx18_writel(cx, IRQ_HPU_TO_APU_ACK, &cx->scb->hpu2apu_irq_ack); cx18_writel(cx, IRQ_PPU_TO_HPU, &cx->scb->ppu2hpu_irq); cx18_writel(cx, IRQ_HPU_TO_PPU_ACK, &cx->scb->hpu2ppu_irq_ack); cx18_writel(cx, IRQ_EPU_TO_HPU, &cx->scb->epu2hpu_irq); cx18_writel(cx, IRQ_HPU_TO_EPU_ACK, &cx->scb->hpu2epu_irq_ack); cx18_writel(cx, IRQ_CPU_TO_PPU, &cx->scb->cpu2ppu_irq); cx18_writel(cx, IRQ_PPU_TO_CPU_ACK, &cx->scb->ppu2cpu_irq_ack); cx18_writel(cx, IRQ_APU_TO_PPU, &cx->scb->apu2ppu_irq); cx18_writel(cx, IRQ_PPU_TO_APU_ACK, &cx->scb->ppu2apu_irq_ack); cx18_writel(cx, IRQ_HPU_TO_PPU, &cx->scb->hpu2ppu_irq); cx18_writel(cx, IRQ_PPU_TO_HPU_ACK, &cx->scb->ppu2hpu_irq_ack); cx18_writel(cx, IRQ_EPU_TO_PPU, &cx->scb->epu2ppu_irq); cx18_writel(cx, IRQ_PPU_TO_EPU_ACK, &cx->scb->ppu2epu_irq_ack); cx18_writel(cx, IRQ_CPU_TO_EPU, &cx->scb->cpu2epu_irq); cx18_writel(cx, IRQ_EPU_TO_CPU_ACK, &cx->scb->epu2cpu_irq_ack); cx18_writel(cx, IRQ_APU_TO_EPU, &cx->scb->apu2epu_irq); cx18_writel(cx, IRQ_EPU_TO_APU_ACK, &cx->scb->epu2apu_irq_ack); cx18_writel(cx, IRQ_HPU_TO_EPU, &cx->scb->hpu2epu_irq); cx18_writel(cx, IRQ_EPU_TO_HPU_ACK, &cx->scb->epu2hpu_irq_ack); cx18_writel(cx, IRQ_PPU_TO_EPU, &cx->scb->ppu2epu_irq); cx18_writel(cx, IRQ_EPU_TO_PPU_ACK, &cx->scb->epu2ppu_irq_ack); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2cpu_mb), &cx->scb->apu2cpu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2cpu_mb), &cx->scb->hpu2cpu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2cpu_mb), &cx->scb->ppu2cpu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2cpu_mb), &cx->scb->epu2cpu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2apu_mb), &cx->scb->cpu2apu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2apu_mb), &cx->scb->hpu2apu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2apu_mb), &cx->scb->ppu2apu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2apu_mb), &cx->scb->epu2apu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2hpu_mb), &cx->scb->cpu2hpu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2hpu_mb), &cx->scb->apu2hpu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2hpu_mb), &cx->scb->ppu2hpu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2hpu_mb), &cx->scb->epu2hpu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2ppu_mb), &cx->scb->cpu2ppu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2ppu_mb), &cx->scb->apu2ppu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2ppu_mb), &cx->scb->hpu2ppu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2ppu_mb), &cx->scb->epu2ppu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2epu_mb), &cx->scb->cpu2epu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2epu_mb), &cx->scb->apu2epu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2epu_mb), &cx->scb->hpu2epu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2epu_mb), &cx->scb->ppu2epu_mb_offset); cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu_state), &cx->scb->ipc_offset); cx18_writel(cx, 1, &cx->scb->epu_state); }