void cyg_hal_sh_pcic_pci_init(void) { cyg_uint8 next_bus; cyg_uint32 tmp; static int initialized = 0; if (initialized) return; initialized = 1; // PCI bus/wait state configs must match those used in the BSC. HAL_READ_UINT32(CYGARC_REG_BCR1, tmp); tmp |= 0x40000000; HAL_WRITE_UINT32(CYGARC_REG_PCIC_BCR1, tmp); HAL_READ_UINT16(CYGARC_REG_BCR2, tmp); HAL_WRITE_UINT32(CYGARC_REG_PCIC_BCR2, tmp); HAL_READ_UINT32(CYGARC_REG_WCR1, tmp); HAL_WRITE_UINT32(CYGARC_REG_PCIC_WCR1, tmp); HAL_READ_UINT32(CYGARC_REG_WCR2, tmp); HAL_WRITE_UINT32(CYGARC_REG_PCIC_WCR2, tmp); HAL_READ_UINT32(CYGARC_REG_WCR3, tmp); HAL_WRITE_UINT32(CYGARC_REG_PCIC_WCR3, tmp); HAL_READ_UINT32(CYGARC_REG_MCR, tmp); tmp &= ~(CYGARC_REG_MCR_MRSET | CYGARC_REG_MCR_RFSH); HAL_WRITE_UINT32(CYGARC_REG_PCIC_MCR, tmp); // Unmask all PCI related interrupts HAL_WRITE_UINT32(CYGARC_REG_PCIC_INTM, CYGARC_REG_PCIC_INTM_INIT); HAL_WRITE_UINT32(CYGARC_REG_PCIC_AINTM, CYGARC_REG_PCIC_AINTM_INIT); // Set host PCI config using platform specified parameters. HAL_WRITE_UINT32(CYGARC_REG_PCIC_CFG+CYG_PCI_CFG_COMMAND, 0xfb9000c7); HAL_WRITE_UINT32(CYGARC_REG_PCIC_CFG+CYG_PCI_CFG_CLASS_REV, 0x00000000); HAL_WRITE_UINT32(CYGARC_REG_PCIC_CFG+CYG_PCI_CFG_CACHE_LINE_SIZE, 64<<8); HAL_WRITE_UINT32(CYGARC_REG_PCIC_CFG+CYG_PCI_CFG_BAR_0, CYGARC_REG_PCIC_BAR0_PLF_INIT); HAL_WRITE_UINT32(CYGARC_REG_PCIC_CFG+CYG_PCI_CFG_BAR_1, CYGARC_REG_PCIC_BAR1_PLF_INIT); HAL_WRITE_UINT32(CYGARC_REG_PCIC_CFG+CYG_PCI_CFG_BAR_2, CYGARC_REG_PCIC_BAR2_PLF_INIT); HAL_WRITE_UINT32(CYGARC_REG_PCIC_CFG+CYG_PCI_CFG_SUB_VENDOR, 0x35051054); HAL_WRITE_UINT32(CYGARC_REG_PCIC_LSR0, CYGARC_REG_PCIC_LSR0_PLF_INIT); HAL_WRITE_UINT32(CYGARC_REG_PCIC_LSR1, CYGARC_REG_PCIC_LSR1_PLF_INIT); HAL_WRITE_UINT32(CYGARC_REG_PCIC_LAR0, CYGARC_REG_PCIC_LAR0_PLF_INIT); HAL_WRITE_UINT32(CYGARC_REG_PCIC_LAR1, CYGARC_REG_PCIC_LAR1_PLF_INIT); HAL_WRITE_UINT32(CYGARC_REG_PCIC_CR, CYGARC_REG_PCIC_CR_INIT); // Configure PCI bus. next_bus = 1; cyg_pci_configure_bus(0, &next_bus); }
void cyg_hal_plf_pci_init(void) { cyg_uint8 next_bus; static int initialized = 0; if (initialized) return; initialized = 1; // Set PCI bases HAL_WRITE_UINT32(CYGARC_REG_PCI_IO_MEMOFFSET, CYGARC_BUS_ADDRESS(HAL_PCI_ALLOC_BASE_IO)); HAL_WRITE_UINT32(CYGARC_REG_PCI_MEM_MEMOFFSET, CYGARC_BUS_ADDRESS(HAL_PCI_ALLOC_BASE_MEMORY)); // Reset PCI - this does not have the desired effect; devices remain enabled. HAL_WRITE_UINT32(CYGARC_REG_SD0001_RESET, CYGARC_REG_SD0001_RESET_PCIRST); CYGACC_CALL_IF_DELAY_US(100); // Bring PCI out of reset HAL_WRITE_UINT32(CYGARC_REG_SD0001_RESET, 0); CYGACC_CALL_IF_DELAY_US(10000); // Set PCI access timeouts/retries to max HAL_WRITE_UINT32(CYGARC_REG_SD0001_PCI_CTL, (CYGARC_REG_SD0001_PCI_CTL_MAX_DEADLOCK_CNT |CYGARC_REG_SD0001_PCI_CTL_MAX_RETRY_CNT)); CYGACC_CALL_IF_DELAY_US(10000); // Enable controller // Setup for bus mastering cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_COMMAND, CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_MASTER | CYG_PCI_CFG_COMMAND_PARITY | CYG_PCI_CFG_COMMAND_SERR); // Setup latency timer field cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_LATENCY_TIMER, 32); // Set memory base cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_1, 0x0c000008); // Configure PCI bus. next_bus = 1; cyg_pci_configure_bus(0, &next_bus); }
externC void _mb93091_pci_init(void) { static int _init = 0; cyg_uint8 next_bus; cyg_uint32 cmd_state; if (_init) return; _init = 1; cyg_pci_init(); // Enable controller - most of the basic configuration // was set up at boot time in "platform.inc" // Setup for bus mastering HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_COMMAND, cmd_state); if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) { HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_COMMAND, CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_MASTER | CYG_PCI_CFG_COMMAND_PARITY | CYG_PCI_CFG_COMMAND_SERR); } // Setup latency timer field HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_LATENCY_TIMER, 32); HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0x10,0), CYG_PCI_CFG_COMMAND, cmd_state); if ((cmd_state & CYG_PCI_CFG_COMMAND_ACTIVE)) { /* It was already active. Turn it off so it gets configured with a base address which is actually in the range Redboot can see */ cmd_state &= ~CYG_PCI_CFG_COMMAND_ACTIVE; HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0x10,0), CYG_PCI_CFG_COMMAND, cmd_state); } // Configure PCI bus. next_bus = 1; cyg_pci_configure_bus(0, &next_bus); }
externC void _csb281_pci_init(void) { static int _init = 0; cyg_uint8 next_bus; cyg_uint32 cmd_state; if (_init) return; _init = 1; // Initialize PCI support cyg_pci_init(); // Setup for bus mastering HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_COMMAND, cmd_state); if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) { // Force PCI-side window to 0 HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_0, 0x01); // Enable bus mastering from host HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_COMMAND, CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_MASTER | CYG_PCI_CFG_COMMAND_PARITY | CYG_PCI_CFG_COMMAND_SERR); // Setup latency timer field HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_LATENCY_TIMER, 32); // Configure PCI bus. next_bus = 1; cyg_pci_configure_bus(0, &next_bus); } // Configure interrupts (high level)? HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI0, 1, 1); HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI1, 1, 1); HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 1); }
externC void hal_ppc405_pci_init(void) { static int _init = 0; cyg_uint8 next_bus; cyg_uint32 cmd_state, bridge_state; if (_init) return; _init = 1; // Configure PCI bridge HAL_WRITE_UINT32LE(PCIL0_PMM0PCILA, 0); HAL_WRITE_UINT32LE(PCIL0_PMM0PCIHA, 0); HAL_WRITE_UINT32LE(PCIL0_PMM0LA, HAL_PCI_PHYSICAL_MEMORY_BASE); HAL_WRITE_UINT32LE(PCIL0_PMM0MA, ~(0x10000000-1) | 0x00000001); HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_1, 0); HAL_WRITE_UINT32LE(PCIL0_PTM1LA, 0); HAL_WRITE_UINT32LE(PCIL0_PTM1MS, ~(0x10000000-1) | 0x00000001); // Indicate that the bridge has been configured HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state); bridge_state |= 0x0001; HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), 0x60, bridge_state); // Setup for bus mastering HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_COMMAND, cmd_state); cyg_pci_init(); if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) { #if defined(CYGPKG_IO_PCI_DEBUG) diag_printf("Configure PCI bus\n"); #endif HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_COMMAND, CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_MASTER | CYG_PCI_CFG_COMMAND_PARITY | CYG_PCI_CFG_COMMAND_SERR); // Setup latency timer field HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_LATENCY_TIMER, 32); // Configure PCI bus. next_bus = 1; cyg_pci_configure_bus(0, &next_bus); } #if defined(CYGSEM_HAL_POWERPC_PPC405_PCI_SHOW_BUS) if (1) { cyg_uint8 req; cyg_uint8 devfn; cyg_pci_device_id devid; cyg_pci_device dev_info; int i; devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN; while (cyg_pci_find_next(devid, &devid)) { devfn = CYG_PCI_DEV_GET_DEVFN(devid); cyg_pci_get_device_info(devid, &dev_info); HAL_PCI_CFG_READ_UINT8(0, devfn, CYG_PCI_CFG_INT_PIN, req); diag_printf("\n"); diag_printf("Bus: %d", CYG_PCI_DEV_GET_BUS(devid)); diag_printf(", PCI Device: %d", CYG_PCI_DEV_GET_DEV(devfn)); diag_printf(", PCI Func: %d\n", CYG_PCI_DEV_GET_FN(devfn)); diag_printf(" Vendor Id: 0x%04X", dev_info.vendor); diag_printf(", Device Id: 0x%04X", dev_info.device); diag_printf(", Command: 0x%04X", dev_info.command); diag_printf(", IRQ: %d\n", req); for (i = 0; i < dev_info.num_bars; i++) { diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]); diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n", dev_info.base_size[i], dev_info.base_map[i]); } } } #endif }
externC void _csb281_pci_init(void) { static int _init = 0; cyg_uint8 next_bus; cyg_uint32 cmd_state; if (_init) return; _init = 1; // Initialize PCI support cyg_pci_init(); // Setup for bus mastering HAL_PCI_CFG_READ_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_COMMAND, cmd_state); if ((cmd_state & CYG_PCI_CFG_COMMAND_MEMORY) == 0) { // Force PCI-side window to 0 HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_0, 0x01); // Enable bus mastering from host HAL_PCI_CFG_WRITE_UINT32(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_COMMAND, CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_MASTER | CYG_PCI_CFG_COMMAND_PARITY | CYG_PCI_CFG_COMMAND_SERR); // Setup latency timer field HAL_PCI_CFG_WRITE_UINT8(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_LATENCY_TIMER, 32); // Configure PCI bus. next_bus = 1; cyg_pci_configure_bus(0, &next_bus); } if (0){ cyg_uint8 devfn; cyg_pci_device_id devid; cyg_pci_device dev_info; int i; devid = CYG_PCI_DEV_MAKE_ID(next_bus-1, 0) | CYG_PCI_NULL_DEVFN; while (cyg_pci_find_next(devid, &devid)) { devfn = CYG_PCI_DEV_GET_DEVFN(devid); cyg_pci_get_device_info(devid, &dev_info); diag_printf("\n"); diag_printf("Bus: %d\n", CYG_PCI_DEV_GET_BUS(devid)); diag_printf("PCI Device: %d\n", CYG_PCI_DEV_GET_DEV(devfn)); diag_printf("PCI Func : %d\n", CYG_PCI_DEV_GET_FN(devfn)); diag_printf("Vendor Id : 0x%08X\n", dev_info.vendor); diag_printf("Device Id : 0x%08X\n", dev_info.device); for (i = 0; i < dev_info.num_bars; i++) { diag_printf(" BAR[%d] 0x%08x /", i, dev_info.base_address[i]); diag_printf(" probed size 0x%08x / CPU addr 0x%08x\n", dev_info.base_size[i], dev_info.base_map[i]); } } } // Configure interrupts (high level)? HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI0, 1, 1); HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_PCI1, 1, 1); HAL_INTERRUPT_CONFIGURE(CYGNUM_HAL_INTERRUPT_LAN, 1, 1); }
void cyg_hal_plf_pci_init(void) { cyg_uint32 bar_ena, start10, start32, end, size; cyg_uint8 next_bus; // Program PCI window in CPU address space and CPU->PCI remap HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM0_LD_OFFSET, HAL_OCELOT_PCI_MEM0_BASE >> HAL_GALILEO_CPU_DECODE_SHIFT); HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM0_HD_OFFSET, (HAL_OCELOT_PCI_MEM0_BASE+HAL_OCELOT_PCI_MEM0_SIZE-1) >> HAL_GALILEO_CPU_DECODE_SHIFT); HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM1_LD_OFFSET, HAL_OCELOT_PCI_MEM1_BASE >> HAL_GALILEO_CPU_DECODE_SHIFT); HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM1_HD_OFFSET, (HAL_OCELOT_PCI_MEM1_BASE+HAL_OCELOT_PCI_MEM1_SIZE-1) >> HAL_GALILEO_CPU_DECODE_SHIFT); HAL_GALILEO_PUTREG(HAL_GALILEO_PCIIO_LD_OFFSET, HAL_OCELOT_PCI_IO_BASE >> HAL_GALILEO_CPU_DECODE_SHIFT); HAL_GALILEO_PUTREG(HAL_GALILEO_PCIIO_HD_OFFSET, (HAL_OCELOT_PCI_IO_BASE+HAL_OCELOT_PCI_IO_SIZE-1) >> HAL_GALILEO_CPU_DECODE_SHIFT); // Setup for bus mastering cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_COMMAND, CYG_PCI_CFG_COMMAND_IO | CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_MASTER | CYG_PCI_CFG_COMMAND_PARITY | CYG_PCI_CFG_COMMAND_SERR); // Setup latency timer field cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_LATENCY_TIMER, 6); // Disable all BARs bar_ena = 0x1ff; // Allow PCI bus to access local memory // Check for active SCS10 start10 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_LD_OFFSET) << HAL_GALILEO_CPU_DECODE_SHIFT; end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_HD_OFFSET) & 0x7f) + 1) << HAL_GALILEO_CPU_DECODE_SHIFT; if (end > start10) { if ((size = __check_bar(start10, end - start10)) != 0) { // Enable BAR HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET, size); bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10; } } // Check for active SCS32 start32 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_LD_OFFSET) << HAL_GALILEO_CPU_DECODE_SHIFT; end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_HD_OFFSET) & 0x7f) + 1) << HAL_GALILEO_CPU_DECODE_SHIFT; if (end > start32) { if ((size = __check_bar(start32, end - start32)) != 0) { // Enable BAR HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET, size); bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS32; } } bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10; HAL_GALILEO_PUTREG(HAL_GALILEO_BAR_ENA_OFFSET, bar_ena); cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_0, 0xffffffff); end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_0); cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_0, start10); cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_1, 0xffffffff); end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_1); cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), CYG_PCI_CFG_BAR_1, start32); // Configure PCI bus. next_bus = 1; cyg_pci_configure_bus(0, &next_bus); }
void cyg_hal_plf_pci_init(void) { cyg_uint32 limit_reg, adj_dram_size; cyg_uint8 next_bus; // Initialize Secondary PCI bus (bus 1) *(volatile cyg_uint16 *)BCR_ADDR |= 0x40; // reset secondary bus hal_delay_us(10 * 1000); // 10ms enough?? *(volatile cyg_uint16 *)BCR_ADDR &= ~0x40; // release reset // ********* vendor / device id ********** *(cyg_uint16 *)ASVIR_ADDR = 0x113C; *(cyg_uint16 *)ASIR_ADDR = 0x0700; // suppress secondary bus idsels to provide private secondary devices *(cyg_uint16 *)SISR_ADDR = 0x03FF; // ******* Primary Inbound ATU ********* // set primary inbound ATU translate value register to point to // base of local DRAM *(cyg_uint32 *)PIATVR_ADDR = MEMBASE_DRAM & 0xFFFFFFFC; // set primary inbound ATU limit register to include all of installed DRAM. // This value used as a mask. adj_dram_size = hal_dram_size; limit_reg = (0xFFFFFFFF-(adj_dram_size-1)) & 0xFFFFFFF0; *(cyg_uint32 *)PIALR_ADDR = limit_reg; if (iq80310_is_host()) { // set the primary inbound ATU base address to the start of DRAM *(cyg_uint32 *)PIABAR_ADDR = MEMBASE_DRAM & 0xFFFFF000; // ********* Set Primary Outbound Windows ********* // Note: The primary outbound ATU memory window value register // and i/o window value registers are defaulted to 0 // set the primary outbound windows to directly map Local - PCI // requests // outbound memory window *(cyg_uint32 *)POMWVR_ADDR = PRIMARY_MEM_BASE; // outbound DAC Window *(cyg_uint32 *)PODWVR_ADDR = PRIMARY_DAC_BASE; // outbound I/O window *(cyg_uint32 *)POIOWVR_ADDR = PRIMARY_IO_BASE; } #ifdef CYGSEM_HAL_ARM_IQ80310_CLEAR_PCI_RETRY // clear RETRY *(cyg_uint16 *)EBCR_ADDR = 0x0008; #endif // ******** Secondary Inbound ATU *********** // set secondary inbound ATU translate value register to point to base // of local DRAM *(cyg_uint32 *)SIATVR_ADDR = MEMBASE_DRAM & 0xFFFFFFFC; // set secondary inbound ATU base address to start of DRAM *(cyg_uint32 *)SIABAR_ADDR = MEMBASE_DRAM & 0xFFFFF000; // set secondary inbound ATU limit register to include all of // installed DRAM. This value used as a mask. // always allow secondary pci access to all memory (even with A0 step) limit_reg = (0xFFFFFFFF - (adj_dram_size - 1)) & 0xFFFFFFF0; *(cyg_uint32 *)SIALR_ADDR = limit_reg; // ********** Set Secondary Outbound Windows *********** // Note: The secondary outbound ATU memory window value register // and i/o window value registers are defaulted to 0 // set the secondary outbound window to directly map Local - PCI requests // outbound memory window *(cyg_uint32 *)SOMWVR_ADDR = SECONDARY_MEM_BASE; // outbound DAC Window *(cyg_uint32 *)SODWVR_ADDR = SECONDARY_DAC_BASE; // outbound I/O window *(cyg_uint32 *)SOIOWVR_ADDR = SECONDARY_IO_BASE; // *********** command / config / latency registers ************ if (iq80310_is_host()) { // allow primary ATU to act as a bus master, respond to PCI // memory accesses, assert P_SERR#, and enable parity checking *(cyg_uint16 *)PATUCMD_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \ CYG_PCI_CFG_COMMAND_PARITY | \ CYG_PCI_CFG_COMMAND_MASTER | \ CYG_PCI_CFG_COMMAND_MEMORY); } // allow secondary ATU to act as a bus master, respond to PCI memory // accesses, and assert S_SERR# *(cyg_uint16 *)SATUCMD_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \ CYG_PCI_CFG_COMMAND_PARITY | \ CYG_PCI_CFG_COMMAND_MASTER | \ CYG_PCI_CFG_COMMAND_MEMORY); // enable primary and secondary outbound ATUs, BIST, and primary bus // direct addressing *(cyg_uint32 *)ATUCR_ADDR = 0x00000006; // ************ bridge registers ******************* if (iq80310_is_host()) { // set the bridge command register *(cyg_uint16 *)PCR_ADDR = (CYG_PCI_CFG_COMMAND_SERR | \ CYG_PCI_CFG_COMMAND_PARITY | \ CYG_PCI_CFG_COMMAND_MASTER | \ CYG_PCI_CFG_COMMAND_MEMORY); // set the secondary bus number to 1 *(cyg_uint8 *)SBNR_ADDR = SECONDARY_BUS_NUM; *(cyg_uint16 *)BCR_ADDR = 0x0823; // set the primary bus number to 0 *(cyg_uint8 *)PBNR_ADDR = PRIMARY_BUS_NUM; } else { #ifdef CYGSEM_HAL_ARM_IQ80310_CLEAR_PCI_RETRY // Wait for PC BIOS to initialize bus number int i; for (i = 0; i < 15000; i++) { if (*((volatile cyg_uint8 *)SBNR_ADDR) != 0) break; hal_delay_us(1000); // 1msec } #endif if (*((volatile cyg_uint8 *)SBNR_ADDR) == 0) *(cyg_uint8 *)SBNR_ADDR = SECONDARY_BUS_NUM; } pbus_nr = *(cyg_uint8 *)PBNR_ADDR; sbus_nr = *(cyg_uint8 *)SBNR_ADDR; // Now initialize the PCI busses. // Next assignable bus number. Yavapai primary bus is fixed as // bus zero and yavapai secondary is fixed as bus 1. next_bus = sbus_nr + 1; // If we are the host on the Primary bus, then configure it. if (iq80310_is_host()) { // Initialize Primary PCI bus (bus 0) cyg_pci_set_memory_base(PRIMARY_MEM_BASE); cyg_pci_set_io_base(PRIMARY_IO_BASE); cyg_pci_configure_bus(0, &next_bus); } // Initialize Secondary PCI bus (bus 1) cyg_pci_set_memory_base(SECONDARY_MEM_BASE); cyg_pci_set_io_base(SECONDARY_IO_BASE); cyg_pci_configure_bus(sbus_nr, &next_bus); }