bool dal_clock_source_construct(
struct clock_source *clk_src,
struct clock_source_init_data *clk_src_init_data)
{
if (clk_src_init_data == NULL || clk_src_init_data->as == NULL)
return false;
clk_src->dal_ctx = clk_src_init_data->dal_ctx;
clk_src->id = clk_src_init_data->clk_src_id;
clk_src->adapter_service = clk_src_init_data->as;
clk_src->bios_parser = dal_adapter_service_get_bios_parser(
clk_src_init_data->as);
clk_src->turn_off_ds = false;
clk_src->clk_src_id = dal_graphics_object_id_get_clock_source_id(
clk_src_init_data->clk_src_id);
clk_src->is_gen_lock_capable = true;
/*NOTE is_gen_lock_capable is false only for ext clock source dce80 */
clk_src->ep_ss_params = NULL;
clk_src->dp_ss_params = NULL;
clk_src->hdmi_ss_params = NULL;
clk_src->hdmi_ss_params = NULL;
clk_src->ep_ss_params_cnt = 0;
clk_src->dp_ss_params_cnt = 0;
clk_src->hdmi_ss_params_cnt = 0;
clk_src->dvi_ss_params_cnt = 0;
clk_src->output_signals = SIGNAL_TYPE_ALL;
clk_src->input_signals = SIGNAL_TYPE_ALL;
return true;
}
static void set_clock(
struct display_clock *base,
uint32_t requested_clk_khz)
{
struct bp_pixel_clock_parameters pxl_clk_params;
struct display_clock_dce110 *dc = DCLCK110_FROM_BASE(base);
struct dc_bios *bp = dal_adapter_service_get_bios_parser(base->as);
/* Prepare to program display clock*/
memset(&pxl_clk_params, 0, sizeof(pxl_clk_params));
pxl_clk_params.target_pixel_clock = requested_clk_khz;
pxl_clk_params.pll_id = base->id;
bp->funcs->program_display_engine_pll(bp, &pxl_clk_params);
if (dc->dfs_bypass_enabled) {
/* Cache the fixed display clock*/
dc->dfs_bypass_disp_clk =
pxl_clk_params.dfs_bypass_display_clock;
}
/* from power down, we need mark the clock state as ClocksStateNominal
* from HWReset, so when resume we will call pplib voltage regulator.*/
if (requested_clk_khz == 0)
base->cur_min_clks_state = CLOCKS_STATE_NOMINAL;
}
bool dce80_timing_generator_construct(
struct dce110_timing_generator *tg110,
struct adapter_service *as,
struct dc_context *ctx,
uint32_t instance,
const struct dce110_timing_generator_offsets *offsets)
{
if (!tg110)
return false;
if (!as)
return false;
tg110->controller_id = CONTROLLER_ID_D0 + instance;
tg110->offsets = *offsets;
tg110->derived_offsets = reg_offsets[instance];
tg110->base.funcs = &dce80_tg_funcs;
tg110->base.ctx = ctx;
tg110->base.bp = dal_adapter_service_get_bios_parser(as);
tg110->max_h_total = CRTC_H_TOTAL__CRTC_H_TOTAL_MASK + 1;
tg110->max_v_total = CRTC_V_TOTAL__CRTC_V_TOTAL_MASK + 1;
tg110->min_h_blank = 56;
tg110->min_h_front_porch = 4;
tg110->min_h_back_porch = 4;
return true;
}
static bool construct(struct timing_generator *tg,
struct dal_context *ctx,
struct adapter_service *as,
enum controller_id id)
{
if (!as)
return false;
switch (id) {
case CONTROLLER_ID_UNDERLAY0:
break;
default:
return false;
}
if (!dal_timing_generator_construct(tg, id))
return false;
tg->ctx = ctx;
tg->bp = dal_adapter_service_get_bios_parser(as);
tg->regs = tg_underlay_regs[id - CONTROLLER_ID_UNDERLAY0];
tg->funcs = &timing_generator_dce110_funcs;
return true;
}
static enum bp_result link_transmitter_control(
struct dce110_link_encoder *enc110,
struct bp_transmitter_control *cntl)
{
enum bp_result result;
struct dc_bios *bp = dal_adapter_service_get_bios_parser(
enc110->base.adapter_service);
result = bp->funcs->transmitter_control(bp, cntl);
return result;
}
/*
* @brief
* Configure digital transmitter and enable both encoder and transmitter
* Actual output will be available after calling unblank()
*/
static enum encoder_result enable_output(
struct encoder_impl *enc,
const struct encoder_output *output)
{
enum bp_result result = dal_bios_parser_crt_control(
dal_adapter_service_get_bios_parser(enc->adapter_service),
output->ctx.engine, true, output->crtc_timing.pixel_clock);
ASSERT(BP_RESULT_OK == result);
return ENCODER_RESULT_OK;
}
/*
* @brief
* Disable transmitter and its encoder
*/
static enum encoder_result disable_output(
struct encoder_impl *enc,
const struct encoder_output *output)
{
enum bp_result result;
struct hw_ctx_analog_encoder *hw_ctx =
FROM_ENCODER_IMPL(enc)->base.hw_ctx;
if (!hw_ctx->funcs->is_output_enabled(hw_ctx, output->ctx.engine))
return ENCODER_RESULT_OK;
result = dal_bios_parser_crt_control(
dal_adapter_service_get_bios_parser(enc->adapter_service),
output->ctx.engine,
false,
output->crtc_timing.pixel_clock);
ASSERT(BP_RESULT_OK == result);
return ENCODER_RESULT_OK;
}
