bool dal_line_buffer_construct_base(
struct line_buffer *lb,
struct line_buffer_init_data *init_data
)
{
struct dal_context *dal_context = init_data->dal_context;
if (init_data == NULL || init_data->as == NULL)
return false;
lb->dal_context = init_data->dal_context;
lb->size = dal_adapter_service_get_line_buffer_size(init_data->as);
lb->power_gating = dal_adapter_service_is_feature_supported(
FEATURE_POWER_GATING_LB_PORTION);
dal_logger_write(dal_context->logger,
LOG_MAJOR_LINE_BUFFER,
LOG_MINOR_LINE_BUFFER_POWERGATING,
"LB Partial Power Gating option: %s\n",
(lb->power_gating == true ? "Enabled" : "Disabled"));
return true;
}
static bool display_clock_integrated_info_construct(
struct display_clock_dce110 *disp_clk,
struct adapter_service *as)
{
struct integrated_info info;
struct firmware_info fw_info;
uint32_t i;
struct display_clock *base = &disp_clk->disp_clk_base;
bool res;
memset(&info, 0, sizeof(struct integrated_info));
memset(&fw_info, 0, sizeof(struct firmware_info));
res = dal_adapter_service_get_integrated_info(as, &info);
disp_clk->dentist_vco_freq_khz = info.dentist_vco_freq;
if (disp_clk->dentist_vco_freq_khz == 0) {
dal_adapter_service_get_firmware_info(as, &fw_info);
disp_clk->dentist_vco_freq_khz =
fw_info.smu_gpu_pll_output_freq;
if (disp_clk->dentist_vco_freq_khz == 0)
disp_clk->dentist_vco_freq_khz = 3600000;
}
base->min_display_clk_threshold_khz =
disp_clk->dentist_vco_freq_khz / 64;
if (!res)
return false;
/*update the maximum display clock for each power state*/
for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) {
enum clocks_state clk_state = CLOCKS_STATE_INVALID;
switch (i) {
case 0:
clk_state = CLOCKS_STATE_ULTRA_LOW;
break;
case 1:
clk_state = CLOCKS_STATE_LOW;
break;
case 2:
clk_state = CLOCKS_STATE_NOMINAL;
break;
case 3:
clk_state = CLOCKS_STATE_PERFORMANCE;
break;
default:
clk_state = CLOCKS_STATE_INVALID;
break;
}
/*Do not allow bad VBIOS/SBIOS to override with invalid values,
* check for > 100MHz*/
if (info.disp_clk_voltage[i].max_supported_clk >= 100000) {
max_clks_by_state[clk_state].display_clk_khz =
info.disp_clk_voltage[i].max_supported_clk;
}
}
disp_clk->dfs_bypass_enabled =
dal_adapter_service_is_dfs_bypass_enabled(as);
disp_clk->use_max_disp_clk =
dal_adapter_service_is_feature_supported(
FEATURE_USE_MAX_DISPLAY_CLK);
return true;
}
bool dce80_link_encoder_construct(
struct dce110_link_encoder *enc110,
const struct encoder_init_data *init_data,
const struct dce110_link_enc_registers *link_regs,
const struct dce110_link_enc_aux_registers *aux_regs,
const struct dce110_link_enc_bl_registers *bl_regs)
{
struct graphics_object_encoder_cap_info enc_cap_info = {0};
enc110->base.funcs = &dce80_lnk_enc_funcs;
enc110->base.ctx = init_data->ctx;
enc110->base.id = init_data->encoder;
enc110->base.hpd_source = init_data->hpd_source;
enc110->base.connector = init_data->connector;
enc110->base.input_signals = SIGNAL_TYPE_ALL;
enc110->base.adapter_service = init_data->adapter_service;
enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
enc110->base.features.flags.raw = 0;
enc110->base.transmitter = init_data->transmitter;
enc110->base.features.flags.bits.IS_AUDIO_CAPABLE = true;
enc110->base.features.max_pixel_clock = DCE8_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
enc110->base.features.max_hdmi_pixel_clock =
DCE8_UNIPHY_MAX_PIXEL_CLK_IN_KHZ;
enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212;
/* set the flag to indicate whether driver poll the I2C data pin
* while doing the DP sink detect
*/
if (dal_adapter_service_is_feature_supported(
FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
enc110->base.features.flags.bits.
DP_SINK_DETECT_POLL_DATA_PIN = true;
enc110->base.output_signals =
SIGNAL_TYPE_DVI_SINGLE_LINK |
SIGNAL_TYPE_DVI_DUAL_LINK |
SIGNAL_TYPE_LVDS |
SIGNAL_TYPE_DISPLAY_PORT |
SIGNAL_TYPE_DISPLAY_PORT_MST |
SIGNAL_TYPE_EDP |
SIGNAL_TYPE_HDMI_TYPE_A;
/* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
* SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
* SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
* DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
* Prefer DIG assignment is decided by board design.
* For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
* and VBIOS will filter out 7 UNIPHY for DCE 8.0.
* By this, adding DIGG should not hurt DCE 8.0.
* This will let DCE 8.1 share DCE 8.0 as much as possible
*/
enc110->link_regs = link_regs;
enc110->aux_regs = aux_regs;
enc110->bl_regs = bl_regs;
switch (enc110->base.transmitter) {
case TRANSMITTER_UNIPHY_A:
enc110->base.preferred_engine = ENGINE_ID_DIGA;
break;
case TRANSMITTER_UNIPHY_B:
enc110->base.preferred_engine = ENGINE_ID_DIGB;
break;
case TRANSMITTER_UNIPHY_C:
enc110->base.preferred_engine = ENGINE_ID_DIGC;
break;
case TRANSMITTER_UNIPHY_D:
enc110->base.preferred_engine = ENGINE_ID_DIGD;
break;
case TRANSMITTER_UNIPHY_E:
enc110->base.preferred_engine = ENGINE_ID_DIGE;
break;
case TRANSMITTER_UNIPHY_F:
enc110->base.preferred_engine = ENGINE_ID_DIGF;
break;
default:
ASSERT_CRITICAL(false);
enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
break;
}
dal_logger_write(init_data->ctx->logger,
LOG_MAJOR_I2C_AUX,
LOG_MINOR_I2C_AUX_CFG,
"Using channel: %s [%d]\n",
DECODE_CHANNEL_ID(init_data->channel),
init_data->channel);
/* Override features with DCE-specific values */
if (dal_adapter_service_get_encoder_cap_info(
enc110->base.adapter_service,
enc110->base.id, &enc_cap_info))
enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
enc_cap_info.dp_hbr2_cap;
/* test pattern 3 support */
enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
enc110->base.features.max_deep_color = COLOR_DEPTH_121212;
enc110->base.features.flags.bits.IS_Y_ONLY_CAPABLE =
dal_adapter_service_is_feature_supported(
FEATURE_SUPPORT_DP_Y_ONLY);
enc110->base.features.flags.bits.IS_YCBCR_CAPABLE =
dal_adapter_service_is_feature_supported(
FEATURE_SUPPORT_DP_YUV);
return true;
}
