static __init void dm355_leopard_init(void) { struct clk *aemif; gpio_request(9, "dm9000"); gpio_direction_input(9); dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9); aemif = clk_get(&dm355leopard_dm9000.dev, "aemif"); if (IS_ERR(aemif)) WARN("%s: unable to get AEMIF clock\n", __func__); else clk_enable(aemif); platform_add_devices(davinci_leopard_devices, ARRAY_SIZE(davinci_leopard_devices)); leopard_init_i2c(); davinci_serial_init(&uart_config); /* NOTE: NAND flash timings set by the UBL are slower than * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 * but could be 0x0400008c for about 25% faster page reads. */ gpio_request(2, "usb_id_toggle"); gpio_direction_output(2, USB_ID_VALUE); /* irlml6401 switches over 1A in under 8 msec */ davinci_setup_usb(1000, 8); davinci_setup_mmc(0, &dm355leopard_mmc_config); davinci_setup_mmc(1, &dm355leopard_mmc_config); dm355_init_spi0(BIT(0), dm355_leopard_spi_info, ARRAY_SIZE(dm355_leopard_spi_info)); }
static void dm365evm_usb_configure(void) { davinci_cfg_reg(DM365_GPIO33); gpio_request(33, "usb"); gpio_direction_output(33, 1); davinci_setup_usb(500, 8); }
static __init void dm355_leopard_init(void) { struct clk *aemif; gpio_request(9, "dm9000"); gpio_direction_input(9); dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9); aemif = clk_get(&dm355leopard_dm9000.dev, "aemif"); if (IS_ERR(aemif)) WARN("%s: unable to get AEMIF clock\n", __func__); else clk_enable(aemif); platform_add_devices(davinci_leopard_devices, ARRAY_SIZE(davinci_leopard_devices)); leopard_init_i2c(); davinci_serial_init(&uart_config); gpio_request(2, "usb_id_toggle"); gpio_direction_output(2, USB_ID_VALUE); davinci_setup_usb(1000, 8); davinci_setup_mmc(0, &dm355leopard_mmc_config); davinci_setup_mmc(1, &dm355leopard_mmc_config); dm355_init_spi0(BIT(0), dm355_leopard_spi_info, ARRAY_SIZE(dm355_leopard_spi_info)); }
static __init void davinci_ntosd2_init(void) { struct clk *aemif_clk; struct davinci_soc_info *soc_info = &davinci_soc_info; int status; aemif_clk = clk_get(NULL, "aemif"); clk_enable(aemif_clk); if (HAS_ATA) { if (HAS_NAND) pr_warning("WARNING: both IDE and Flash are " "enabled, but they share AEMIF pins.\n" "\tDisable IDE for NAND/NOR support.\n"); davinci_init_ide(); } else if (HAS_NAND) { davinci_cfg_reg(DM644X_HPIEN_DISABLE); davinci_cfg_reg(DM644X_ATAEN_DISABLE); /* only one device will be jumpered and detected */ if (HAS_NAND) platform_device_register( &davinci_ntosd2_nandflash_device); } platform_add_devices(davinci_ntosd2_devices, ARRAY_SIZE(davinci_ntosd2_devices)); /* Initialize I2C interface specific for this board */ status = ntosd2_init_i2c(); if (status < 0) pr_warning("davinci_ntosd2_init: msp430 irq setup failed:" " %d\n", status); davinci_serial_init(&uart_config); dm644x_init_asp(&dm644x_ntosd2_snd_data); soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK; soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY; davinci_setup_usb(1000, 8); /* * Mux the pins to be GPIOs, VLYNQEN is already done at startup. * The AEAWx are five new AEAW pins that can be muxed by separately. * They are a bitmask for GPIO management. According TI * documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ * gpio(10,11,12,13) for leds any combination of bits works except * four last. So we are to reset all five. */ davinci_cfg_reg(DM644X_AEAW0); davinci_cfg_reg(DM644X_AEAW1); davinci_cfg_reg(DM644X_AEAW2); davinci_cfg_reg(DM644X_AEAW3); davinci_cfg_reg(DM644X_AEAW4); davinci_setup_mmc(0, &davinci_ntosd2_mmc_config); }
static __init void davinci_ntosd2_init(void) { int ret; struct clk *aemif_clk; struct davinci_soc_info *soc_info = &davinci_soc_info; ret = dm644x_gpio_register(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); aemif_clk = clk_get(NULL, "aemif"); clk_prepare_enable(aemif_clk); if (HAS_ATA) { if (HAS_NAND) pr_warn("WARNING: both IDE and Flash are enabled, but they share AEMIF pins\n" "\tDisable IDE for NAND/NOR support\n"); davinci_init_ide(); } else if (HAS_NAND) { davinci_cfg_reg(DM644X_HPIEN_DISABLE); davinci_cfg_reg(DM644X_ATAEN_DISABLE); /* only one device will be jumpered and detected */ if (HAS_NAND) platform_device_register( &davinci_ntosd2_nandflash_device); } platform_add_devices(davinci_ntosd2_devices, ARRAY_SIZE(davinci_ntosd2_devices)); davinci_serial_init(dm644x_serial_device); dm644x_init_asp(&dm644x_ntosd2_snd_data); soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID; davinci_setup_usb(1000, 8); /* * Mux the pins to be GPIOs, VLYNQEN is already done at startup. * The AEAWx are five new AEAW pins that can be muxed by separately. * They are a bitmask for GPIO management. According TI * documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ * gpio(10,11,12,13) for leds any combination of bits works except * four last. So we are to reset all five. */ davinci_cfg_reg(DM644X_AEAW0); davinci_cfg_reg(DM644X_AEAW1); davinci_cfg_reg(DM644X_AEAW2); davinci_cfg_reg(DM644X_AEAW3); davinci_cfg_reg(DM644X_AEAW4); davinci_setup_mmc(0, &davinci_ntosd2_mmc_config); }
static __init void davinci_sffsdr_init(void) { struct davinci_soc_info *soc_info = &davinci_soc_info; platform_add_devices(davinci_sffsdr_devices, ARRAY_SIZE(davinci_sffsdr_devices)); sffsdr_init_i2c(); davinci_serial_init(&uart_config); soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID; davinci_setup_usb(0, 0); /* We support only peripheral mode. */ /* mux VLYNQ pins */ davinci_cfg_reg(DM644X_VLYNQEN); davinci_cfg_reg(DM644X_VLYNQWD); }
static __init void dm355_evm_init(void) { struct clk *aemif; int ret; ret = dm355_gpio_register(); if (ret) pr_warn("%s: GPIO init failed: %d\n", __func__, ret); gpio_request(1, "dm9000"); gpio_direction_input(1); dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1); aemif = clk_get(&dm355evm_dm9000.dev, "aemif"); if (IS_ERR(aemif)) WARN("%s: unable to get AEMIF clock\n", __func__); else clk_prepare_enable(aemif); platform_add_devices(davinci_evm_devices, ARRAY_SIZE(davinci_evm_devices)); evm_init_i2c(); davinci_serial_init(dm355_serial_device); /* NOTE: NAND flash timings set by the UBL are slower than * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 * but could be 0x0400008c for about 25% faster page reads. */ gpio_request(2, "usb_id_toggle"); gpio_direction_output(2, USB_ID_VALUE); /* irlml6401 switches over 1A in under 8 msec */ davinci_setup_usb(1000, 8); davinci_setup_mmc(0, &dm355evm_mmc_config); davinci_setup_mmc(1, &dm355evm_mmc_config); dm355_init_video(&vpfe_cfg, &dm355evm_display_cfg); dm355_init_spi0(BIT(0), dm355_evm_spi_info, ARRAY_SIZE(dm355_evm_spi_info)); /* DM335 EVM uses ASP1; line-out is a stereo mini-jack */ dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN, &dm355_evm_snd_data); }
static int evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c) { /* p0 = nDRV_VBUS (initial: don't supply it) */ gpio_request(gpio + 0, "nDRV_VBUS"); gpio_direction_output(gpio + 0, 1); /* p1 = VDDIMX_EN */ gpio_request(gpio + 1, "VDDIMX_EN"); gpio_direction_output(gpio + 1, 1); /* p2 = VLYNQ_EN */ gpio_request(gpio + 2, "VLYNQ_EN"); gpio_direction_output(gpio + 2, 1); /* p3 = n3V3_CF_RESET (initial: stay in reset) */ gpio_request(gpio + 3, "nCF_RESET"); gpio_direction_output(gpio + 3, 0); /* (p4 unused) */ /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */ gpio_request(gpio + 5, "WLAN_RESET"); gpio_direction_output(gpio + 5, 1); /* p6 = nATA_SEL (initial: select) */ gpio_request(gpio + 6, "nATA_SEL"); gpio_direction_output(gpio + 6, 0); /* p7 = nCF_SEL (initial: deselect) */ gpio_request(gpio + 7, "nCF_SEL"); gpio_direction_output(gpio + 7, 1); /* irlml6401 switches over 1A, in under 8 msec; * now it can be managed by nDRV_VBUS ... */ davinci_setup_usb(1000, 8); return 0; }