C++ (Cpp) dbgu_init示例

示例#1

文件： init.c 项目： no111u3/arm_my_learn

// Low level initing Soc
extern void low_level_init(void) {
    // enable led 0
    AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB27;
    AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB27;
    AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB27;
    // enable led 1
    AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB0;
    AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB0;
    AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB0;
    // enable dbgu
    dbgu_init(48000000, 115200);
    // put first string
    put_string("\n");
    put_string("Start on 48MHz clock\n");
    put_string("Switching to main clock\n");
    // wait for stable
    delay(120000);
    // change clock to main clock
    mck_init(AT91C_CKGR_MOSCEN | (0xff << 8));
    mck_en();
    // wait for stable
    delay(120000);
    // reinit dbgu on 16MHz msck
    dbgu_init(16000000, 115200);
    // put second string
    put_string("\n");
    put_string("Running on 16MHz clock\n");
    // setup plla_value
    put_string("Setup plla_value\nMultiplay: 210\nDivide: 16\nOutput clock: 210MHz\n");
    put_string("Initing PLLA\n");
    plla_init(plla_setup(16, 100, 2, 209));
    put_string("PLLA inited, switching to PLLA clock\n");
    delay(100000);
    pllack_en(AT91C_PMC_MDIV_2);
    dbgu_init(105000000, 115200);
    delay(100000);
    put_string("\n");
    put_string("Running on 105MHz clock\n");
    // init aic
    aic_init(AT91C_AIC_BRANCH_OPCODE, aic_default,
             aic_default, aic_spirious_int, 0);
    // perform 8 end of interrupt command to make sure AIC will not lock out nIRQ
    aic_acknowledge_irq();
    aic_acknowledge_irq();
    aic_acknowledge_irq();
    aic_acknowledge_irq();
    aic_acknowledge_irq();
    aic_acknowledge_irq();
    aic_acknowledge_irq();
    aic_acknowledge_irq();
    // setup basic exception vectors
    aic_set_exception_vector((unsigned int *)0x0C, aic_fetch_abort);
    aic_set_exception_vector((unsigned int *)0x10, aic_data_abort);
    aic_set_exception_vector((unsigned int *)0x4, aic_undefined);
    // initing ebi
    ebi_init();
    // initing sdramc
    sdramc_init();
}

示例#2

文件： init.c 项目： no111u3/arm_my_learn

// Low level initing Soc
extern void low_level_init(void) {
    // Enable led
    AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB27;
    AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB27;
    AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB27;
    // enable dbgu
    dbgu_init(48000000, 115200);
    // put first string
    put_string("\n");
    put_string("Start on 48MHz clock\n");
    put_string("Switching to main clock\n");
    // wait for stable
    delay(120000);
    // change clock to main clock
    mck_init(AT91C_CKGR_MOSCEN | (0xff << 8));
    mck_en();
    // wait for stable
    delay(120000);
    // reinit dbgu on 16MHz msck
    dbgu_init(16000000, 115200);
    // put second string
    put_string("\n");
    put_string("Running on 16MHz clock\n");
    // init aic
    aic_init(aic_default, aic_default,
             aic_default, aic_spirious_int, 0);
    // perform 8 end of interrupt command to make sure AIC will not lock out nIRQ
    aic_acknowledge_irq();
    aic_acknowledge_irq();
    aic_acknowledge_irq();
    aic_acknowledge_irq();
    aic_acknowledge_irq();
    aic_acknowledge_irq();
    aic_acknowledge_irq();
    aic_acknowledge_irq();
    // setup basic exception vectors
    aic_set_exception_vector((unsigned int *)0x0C, aic_fetch_abort);
    aic_set_exception_vector((unsigned int *)0x10, aic_data_abort);
    aic_set_exception_vector((unsigned int *)0x4, aic_undefined);
    // Infinity loop
    while (1) {
        wait();
        AT91C_BASE_PIOB->PIO_SODR = AT91C_PIO_PB27;
        wait();
        AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB27;
    }
}

示例#3

文件： at91sam9260ek.c 项目： rucoder/at91bootstrap

static void initialize_dbgu(void)
{
	/* Configure DBGU pin */
	/* {"RXD", AT91C_PIN_PB(14), 0, PIO_DEFAULT, PIO_PERIPH_A}, */
	/* {"TXD", AT91C_PIN_PB(15), 0, PIO_DEFAULT, PIO_PERIPH_A}, */
	writel(((0x01 << 14) | (0x01 << 15)), AT91C_BASE_PIOB + PIO_ASR(0));
	writel(((0x01 << 14) | (0x01 << 15)), AT91C_BASE_PIOB + PIO_PDR(0));

	writel((1 << AT91C_ID_PIOB), (PMC_PCER + AT91C_BASE_PMC));

	dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
}

示例#4

文件： at91sam9g10ek.c 项目： rucoder/at91bootstrap

static void initialize_dbgu(void)
{
	/* const struct pio_desc dbgu_pins[] = {
		{"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A},
		{"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A},
		{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
	}; */
	/* Configure the dbgu pins */
	writel(((0x01 << 9) | (0x01 << 10)), AT91C_BASE_PIOA + PIO_ASR(0));
	writel(((0x01 << 9) | (0x01 << 10)), AT91C_BASE_PIOA + PIO_PDR(0));

	writel((1 << AT91C_ID_PIOA), (PMC_PCER + AT91C_BASE_PMC));

	dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
}

示例#5

文件： init.c 项目： no111u3/arm_my_learn

// Low level initing Soc
extern void low_level_init(void) {
    // Enable led
    AT91C_BASE_PIOB->PIO_PER = AT91C_PIO_PB27;
    AT91C_BASE_PIOB->PIO_OER = AT91C_PIO_PB27;
    AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB27;
    // enable dbgu
    dbgu_init();
    // Infinity loop
    while (1) {
        wait();
        AT91C_BASE_PIOB->PIO_SODR = AT91C_PIO_PB27;
        wait();
        AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB27;
    }
}

示例#6

文件： start.c 项目： DenniJensen/Betriebssysteme

/*
 * start_kernel() - unser C-Eintrittspunkt
 *
 * Wird direkt nach Initialisierung des Supervisor-Stacks gestartet.
 */
void start_kernel(void)
{
  /*
   * System initialisieren.
   */
  init_other_stacks();
  init_exceptions();

  dbgu_init();

  st_init();
  st_set_interval(500);


  put_char('c');

  scheduler_init();
}

示例#7

文件： at91sam9xeek.c 项目： amangarg08/at91bootstrap

static void initialize_dbgu(void)
{
	at91_dbgu_hw_init();

	dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
}

示例#8

文件： at91sam9rlek.c 项目： Lefinnois/AriaBoot

/*------------------------------------------------------------------------------*/
void hw_init(void)
{
    unsigned int cp15;

    /*
     * Configure PIOs 
     */
    const struct pio_desc hw_pio[] = {
#ifdef CONFIG_DEBUG
        {"RXD", AT91C_PIN_PA(21), 0, PIO_DEFAULT, PIO_PERIPH_A},
        {"TXD", AT91C_PIN_PA(22), 0, PIO_DEFAULT, PIO_PERIPH_A},
#endif
        {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
    };

    /*
     * Disable watchdog 
     */
    writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);

    /*
     * At this stage the main oscillator is supposed to be enabled
     * * PCK = MCK = MOSC 
     */

    /*
     * Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA 
     */
    pmc_cfg_plla(PLL_SETTINGS, PLL_LOCK_TIMEOUT);

    /*
     * PCK = PLL = 2 * MCK 
     */
    pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
    /*
     * Switch MCK on PLLA output 
     */
    pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);

    /*
     * Enable External Reset 
     */
    writel(AT91C_RSTC_KEY_UNLOCK
           || AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);

    /*
     * Configure CP15 
     */
    cp15 = get_cp15();
    //cp15 |= I_CACHE;
    set_cp15(cp15);

#ifdef CONFIG_SCLK
    sclk_enable();
#endif

    /*
     * Configure the PIO controller to output PCK0 
     */
    pio_setup(hw_pio);

#ifdef CONFIG_DEBUG
    /*
     * Enable Debug messages on the DBGU 
     */
    dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
    dbgu_print("Start AT91Bootstrap...\n\r");
#endif                          /* CONFIG_VERBOSE */

    /*
     * Configure the EBI Slave Slot Cycle to 64 
     */
    writel((readl((AT91C_MATRIX_SCFG4)) & ~0xFF) | 0x40, AT91C_MATRIX_SCFG4);

    /*
     * Initialize the matrix Slave 0 & Slave 4 (SRAM & EBI)
     */
    writel(readl(AT91C_MATRIX_SCFG0) | AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR |
           AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D, AT91C_MATRIX_SCFG0);
    writel(readl(AT91C_MATRIX_SCFG4) | AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR |
           AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D, AT91C_MATRIX_SCFG4);

#ifdef CONFIG_SDRAM
    /*
     * Initialize the matrix 
     */
    writel(readl(AT91C_CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_CCFG_EBICSA);

#ifdef MCK_100
    /*
     * Configure SDRAM Controller 
     */
    sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 | AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8,       /* Control Register */
               (MASTER_CLOCK * 7) / 1000000,    /* Refresh Timer Register */
               AT91C_SDRAMC_MD_SDRAM);  /* SDRAM (no low power)   */
#else                           /* 133 MHz */
    /*
     * Configure SDRAM Controller 
     */
    sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_9 | AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3 | AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10,      /* Control Register */
               (MASTER_CLOCK * 7) / 1000000,    /* Refresh Timer Register */
               AT91C_SDRAMC_MD_SDRAM);  /* SDRAM (no low power)   */
#endif

#endif
}

示例#9

文件： at91sam9x5ek.c 项目： rascalmicro/at91bootstrap

/*----------------------------------------------------------------------------*/
void hw_init(void)
{
    unsigned int cp15;

    /*
     * Configure PIOs 
     */
    const struct pio_desc hw_pio[] = {
#ifdef CONFIG_DEBUG
        {"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A},
        {"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A},
#endif
        {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
    };

    /*
     * Disable watchdog 
     */
    writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);

    /*
     * At this stage the main oscillator is supposed to be enabled
     * * PCK = MCK = MOSC 
     */
    writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR);

    /*
     * Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA 
     */
    pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);

    /*
     * PCK = PLLA/2 = 3 * MCK 
     */
    pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK, PLL_LOCK_TIMEOUT);

    /*
     * Switch MCK on PLLA output 
     */
    pmc_cfg_mck(BOARD_PRESCALER_PLLA, PLL_LOCK_TIMEOUT);

    /*
     * Enable External Reset 
     */
    writel(AT91C_RSTC_KEY_UNLOCK
           || AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);

    /*
     * Configure CP15 
     */
    cp15 = get_cp15();
    cp15 |= I_CACHE;
    set_cp15(cp15);

#ifdef CONFIG_SCLK
    sclk_enable();
#endif
    /*
     * Configure the PIO controller 
     */
    writel((1 << AT91C_ID_PIOA_B), (PMC_PCER + AT91C_BASE_PMC));
    pio_setup(hw_pio);

    /*
     * Enable Debug messages on the DBGU 
     */
#ifdef CONFIG_DEBUG
    dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
    dbgu_print("Start AT91Bootstrap...\n\r");
#endif

#ifdef CONFIG_DDR2
    /*
     * Configure DDRAM Controller 
     */
    dbg_log(1, "Init DDR... ");
    ddramc_hw_init();
    dbg_log(1, "Done!\n\r");
#endif                          /* CONFIG_DDR2 */
}

示例#10

文件： at91sam9g20ek.c 项目： Lefinnois/AriaBoot

/*----------------------------------------------------------------------------*/
void hw_init(void)
{
    unsigned int cp15;

    /*
     * Configure PIOs 
     */
    const struct pio_desc hw_pio[] = {
#ifdef CONFIG_DEBUG
        {"RXD", AT91C_PIN_PB(14), 0, PIO_DEFAULT, PIO_PERIPH_A},
        {"TXD", AT91C_PIN_PB(15), 0, PIO_DEFAULT, PIO_PERIPH_A},
#endif
        {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
    };

    /*
     * Disable watchdog 
     */
    writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR);

    /*
     * At this stage the main oscillator is supposed to be enabled
     * * PCK = MCK = MOSC 
     */
    writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR);

    /*
     * Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA 
     */
    pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT);

    /*
     * PCK = PLLA/2 = 3 * MCK 
     */
    pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT);
    /*
     * Switch MCK on PLLA output 
     */
    pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT);

    /*
     * Configure PLLB 
     */
    pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT);

    /*
     * Enable External Reset 
     */
    writel(AT91C_RSTC_KEY_UNLOCK
           || AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);

    /*
     * Configure CP15 
     */
    cp15 = get_cp15();
    //cp15 |= I_CACHE;
    set_cp15(cp15);

    /*
     * Enable External Reset 
     */
    writel(AT91C_RSTC_KEY_UNLOCK
           || AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
    /*
     * Configure the PIO controller 
     */
    pio_setup(hw_pio);

    /*
     * Configure the EBI Slave Slot Cycle to 64 
     */
    writel((readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40,
           (AT91C_BASE_MATRIX + MATRIX_SCFG3));

#ifdef CONFIG_DEBUG
    /*
     * Enable Debug messages on the DBGU 
     */
    dbgu_init(BAUDRATE(MASTER_CLOCK, 115200));
    dbgu_print("Start AT91Bootstrap...\n\r");
#endif                          /* CONFIG_DEBUG */

#ifdef CONFIG_SDRAM
    /*
     * Initialize the matrix (memory voltage = 3.3) 
     */
    writel((readl(AT91C_BASE_CCFG + CCFG_EBICSA)) | AT91C_EBI_CS1A_SDRAMC |
           (1 << 16), AT91C_BASE_CCFG + CCFG_EBICSA);

    /*
     * Configure SDRAM Controller 
     */
    sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_3 | AT91C_SDRAMC_TRC_9 | AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3 | AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10,      /* Control Register */
               (MASTER_CLOCK * 7) / 1000000,    /* Refresh Timer Register */
               AT91C_SDRAMC_MD_SDRAM);  /* SDRAM (no low power)   */

#endif                          /* CONFIG_SDRAM */
}