void ddb5477_runtime_detection(void) { volatile char *test_offset; char saved_test_byte; /* Determine if this is a DDB5477 board, or a BSB-VR0300 base board. We can tell by checking for the location of the NVRAM. It lives at the beginning of LCS1 on the DDB5477, and the beginning of LCS1 on the BSB-VR0300 is flash memory. The first 2K of the NVRAM are reserved, so don't we'll poke around just after that. */ /* We can only use the PCI bus to distinquish between the Rockhopper and RockhopperII backplanes and this must wait until ddb5477_board_init() in setup.c after the 5477 is initialized. So, until then handle both Rockhopper and RockhopperII backplanes as Rockhopper 1 */ test_offset = (char *)KSEG1ADDR(DEFAULT_LCS1_BASE + 0x800); saved_test_byte = *test_offset; *test_offset = TESTVAL1; if (*test_offset != TESTVAL1) { /* We couldn't set our test value, so it must not be NVRAM, so it's a BSB_VR0300 */ mips_machtype = MACH_NEC_ROCKHOPPER; } else { /* We may have gotten lucky, and the TESTVAL1 was already stored at the test location, so we must check a second test value */ *test_offset = TESTVAL2; if (*test_offset != TESTVAL2) { /* OK, we couldn't set this value either, so it must definately be a BSB_VR0300 */ mips_machtype = MACH_NEC_ROCKHOPPER; } else { /* We could change the value twice, so it must be NVRAM, so it's a DDB_VRC5477 */ mips_machtype = MACH_NEC_DDB5477; } } /* Restore the original byte */ *test_offset = saved_test_byte; /* before we know a better way, we will trust PMON for getting * RAM size */ board_ram_size = 1 << (36 - (ddb_in32(DDB_SDRAM0) & 0xf)); db_run(printk("DDB run-time detection : %s, %d MB RAM\n", mips_machtype == MACH_NEC_DDB5477 ? "DDB5477" : "Rockhopper", board_ram_size >> 20)); /* we can't handle ram size > 128 MB */ db_assert(board_ram_size <= (128 << 20)); }
asmlinkage void vrc5477_irq_dispatch(struct pt_regs *regs) { extern unsigned int do_IRQ(int irq, struct pt_regs *regs); u32 intStatus; u32 bitmask; u32 i; db_assert(ddb_in32(DDB_INT2STAT) == 0); db_assert(ddb_in32(DDB_INT3STAT) == 0); db_assert(ddb_in32(DDB_INT4STAT) == 0); db_assert(ddb_in32(DDB_NMISTAT) == 0); if (ddb_in32(DDB_INT1STAT) != 0) { #if defined(CONFIG_DEBUG) vrc5477_show_int_regs(); #endif panic("error interrupt has happened."); } intStatus = ddb_in32(DDB_INT0STAT); for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) { /* do we need to "and" with the int mask? */ if (intStatus & bitmask) { do_IRQ(8 + i, regs); } } }
static inline void set_pci_int_attr(u32 pci, u32 intn, u32 active, u32 trigger) { u32 reg_value; u32 reg_bitmask; reg_value = ddb_in32(pci); reg_bitmask = 0x3 << (intn * 2); reg_value &= ~reg_bitmask; reg_value |= (active | trigger) << (intn * 2); ddb_out32(pci, reg_value); }
void __init ddb_pci_reset_bus(void) { u32 temp; /* * I am not sure about the "official" procedure, the following * steps work as far as I know: * We first set PCI cold reset bit (bit 31) in PCICTRL-H. * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. * The same is true for both PCI channels. */ temp = ddb_in32(DDB_PCICTL0_H); temp |= 0x80000000; ddb_out32(DDB_PCICTL0_H, temp); temp &= ~0xc0000000; ddb_out32(DDB_PCICTL0_H, temp); temp = ddb_in32(DDB_PCICTL1_H); temp |= 0x80000000; ddb_out32(DDB_PCICTL1_H, temp); temp &= ~0xc0000000; ddb_out32(DDB_PCICTL1_H, temp); }
u8 i8259_interrupt_ack(void) { u8 irq; u32 reg; /* Set window 0 for interrupt acknowledge */ reg = ddb_in32(DDB_PCIINIT10); ddb_set_pmr(DDB_PCIINIT10, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32); irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE); ddb_out32(DDB_PCIINIT10, reg); return irq; }
void ll_vrc5477_irq_enable(int vrc5477_irq) { u32 reg_value; u32 reg_bitmask; u32 reg_index; db_assert(vrc5477_irq >= 0); db_assert(vrc5477_irq < NUM_5477_IRQ); reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; reg_value = ddb_in32(reg_index); reg_bitmask = 8 << (vrc5477_irq % 8 * 4); db_assert((reg_value & reg_bitmask) == 0); ddb_out32(reg_index, reg_value | reg_bitmask); }
void ll_vrc5477_irq_disable(int vrc5477_irq) { u32 reg_value; u32 reg_bitmask; u32 reg_index; db_assert(vrc5477_irq >= 0); db_assert(vrc5477_irq < NUM_5477_IRQ); reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; reg_value = ddb_in32(reg_index); reg_bitmask = 8 << (vrc5477_irq % 8 * 4); /* we assert that the interrupt is enabled (perhaps over-zealous) */ db_assert( (reg_value & reg_bitmask) != 0); ddb_out32(reg_index, reg_value & ~reg_bitmask); }
void ll_vrc5477_irq_route(int vrc5477_irq, int ip) { u32 reg_value; u32 reg_bitmask; u32 reg_index; db_assert(vrc5477_irq >= 0); db_assert(vrc5477_irq < NUM_5477_IRQ); db_assert(ip >= 0); db_assert((ip < 5) || (ip == 6)); reg_index = DDB_INTCTRL0 + vrc5477_irq/8*4; reg_value = ddb_in32(reg_index); reg_bitmask = 7 << (vrc5477_irq % 8 * 4); reg_value &= ~reg_bitmask; reg_value |= ip << (vrc5477_irq % 8 * 4); ddb_out32(reg_index, reg_value); }
static void vrc5477_irq_dispatch(struct pt_regs *regs) { u32 intStatus; u32 bitmask; u32 i; db_assert(ddb_in32(DDB_INT2STAT) == 0); db_assert(ddb_in32(DDB_INT3STAT) == 0); db_assert(ddb_in32(DDB_INT4STAT) == 0); db_assert(ddb_in32(DDB_NMISTAT) == 0); if (ddb_in32(DDB_INT1STAT) != 0) { #if defined(CONFIG_RUNTIME_DEBUG) vrc5477_show_int_regs(); #endif panic("error interrupt has happened."); } intStatus = ddb_in32(DDB_INT0STAT); if (mips_machtype == MACH_NEC_ROCKHOPPERII) { /* check for i8259 interrupts */ if (intStatus & (1 << VRC5477_I8259_CASCADE)) { int i8259_irq = i8259_interrupt_ack(); do_IRQ(I8259_IRQ_BASE + i8259_irq, regs); return; } } for (i=0, bitmask=1; i<= NUM_5477_IRQS; bitmask <<=1, i++) { /* do we need to "and" with the int mask? */ if (intStatus & bitmask) { do_IRQ(VRC5477_IRQ_BASE + i, regs); return; } } }