static inline void debugfs_init(struct ser_device *ser, struct tty_struct *tty)
{
ser->debugfs_tty_dir =
debugfs_create_dir(tty->name, debugfsdir);
if (!IS_ERR(ser->debugfs_tty_dir)) {
debugfs_create_blob("last_tx_msg", S_IRUSR,
ser->debugfs_tty_dir,
&ser->tx_blob);
debugfs_create_blob("last_rx_msg", S_IRUSR,
ser->debugfs_tty_dir,
&ser->rx_blob);
debugfs_create_x32("ser_state", S_IRUSR,
ser->debugfs_tty_dir,
(u32 *)&ser->state);
debugfs_create_x8("tty_status", S_IRUSR,
ser->debugfs_tty_dir,
&ser->tty_status);
}
ser->tx_blob.data = ser->tx_data;
ser->tx_blob.size = 0;
ser->rx_blob.data = ser->rx_data;
ser->rx_blob.size = 0;
}
/**
* wil6210_debugfs_init_offset - create set of debugfs files
* @wil - driver's context, used for printing
* @dbg - directory on the debugfs, where files will be created
* @base - base address used in address calculation
* @tbl - table with file descriptions. Should be terminated with empty element.
*
* Creates files accordingly to the @tbl.
*/
static void wil6210_debugfs_init_offset(struct wil6210_priv *wil,
struct dentry *dbg, void *base,
const struct dbg_off * const tbl)
{
int i;
for (i = 0; tbl[i].name; i++) {
struct dentry *f;
switch (tbl[i].type) {
case doff_u32:
f = debugfs_create_u32(tbl[i].name, tbl[i].mode, dbg,
base + tbl[i].off);
break;
case doff_x32:
f = debugfs_create_x32(tbl[i].name, tbl[i].mode, dbg,
base + tbl[i].off);
break;
case doff_ulong:
f = wil_debugfs_create_ulong(tbl[i].name, tbl[i].mode,
dbg, base + tbl[i].off);
break;
case doff_io32:
f = wil_debugfs_create_iomem_x32(tbl[i].name,
tbl[i].mode, dbg,
base + tbl[i].off);
break;
default:
f = ERR_PTR(-EINVAL);
}
if (IS_ERR_OR_NULL(f))
wil_err(wil, "Create file \"%s\": err %ld\n",
tbl[i].name, PTR_ERR(f));
}
}
void mmc_add_card_debugfs(struct mmc_card *card)
{
struct mmc_host *host = card->host;
struct dentry *root;
if (!host->debugfs_root)
return;
root = debugfs_create_dir(mmc_card_id(card), host->debugfs_root);
if (IS_ERR(root))
/* Don't complain -- debugfs just isn't enabled */
return;
if (!root)
/* Complain -- debugfs is enabled, but it failed to
* create the directory. */
goto err;
card->debugfs_root = root;
if (!debugfs_create_x32("state", S_IRUSR, root, &card->state))
goto err;
if (mmc_card_mmc(card) || mmc_card_sd(card))
if (!debugfs_create_file("status", S_IRUSR, root, card,
&mmc_dbg_card_status_fops))
goto err;
return;
err:
debugfs_remove_recursive(root);
card->debugfs_root = NULL;
dev_err(&card->dev, "failed to initialize debugfs\n");
}
void mmc_add_card_debugfs(struct mmc_card *card)
{
struct mmc_host *host = card->host;
struct dentry *root;
if (!host->debugfs_root)
return;
root = debugfs_create_dir(mmc_card_id(card), host->debugfs_root);
if (IS_ERR(root))
/* Don't complain -- debugfs just isn't enabled */
return;
if (!root)
/* Complain -- debugfs is enabled, but it failed to
* create the directory. */
goto err;
card->debugfs_root = root;
if (!debugfs_create_x32("state", S_IRUSR, root, &card->state))
goto err;
if (mmc_card_mmc(card) || mmc_card_sd(card))
if (!debugfs_create_file("status", S_IRUSR, root, card,
&mmc_dbg_card_status_fops))
goto err;
if (mmc_card_mmc(card))
if (!debugfs_create_file("ext_csd", S_IRUSR, root, card,
&mmc_dbg_ext_csd_fops))
goto err;
if (mmc_card_mmc(card) && (card->ext_csd.rev >= 6) &&
(card->host->caps2 & MMC_CAP2_PACKED_WR))
if (!debugfs_create_file("wr_pack_stats", S_IRUSR, root, card,
&mmc_dbg_wr_pack_stats_fops))
goto err;
if (mmc_card_mmc(card) && (card->ext_csd.rev >= 5) &&
card->ext_csd.bkops_en)
if (!debugfs_create_file("bkops_stats", S_IRUSR, root, card,
&mmc_dbg_bkops_stats_fops))
goto err;
//ASUS_BSP +++ Gavin_Chang "mmc cmd statistics"
if (mmc_card_mmc(card))
if (!debugfs_create_file("cmd_stats", S_IRUSR, root, card,
&mmc_dbg_cmd_stats_fops))
goto err;
//ASUS_BSP --- Gavin_Chang "mmc cmd statistics"
return;
err:
debugfs_remove_recursive(root);
card->debugfs_root = NULL;
dev_err(&card->dev, "failed to initialize debugfs\n");
}
int wil6210_debugfs_init(struct wil6210_priv *wil)
{
struct dentry *dbg = wil->debug = debugfs_create_dir(WIL_NAME,
wil_to_wiphy(wil)->debugfsdir);
if (IS_ERR_OR_NULL(dbg))
return -ENODEV;
debugfs_create_file("mbox", S_IRUGO, dbg, wil, &fops_mbox);
debugfs_create_file("vrings", S_IRUGO, dbg, wil, &fops_vring);
debugfs_create_file("stations", S_IRUGO, dbg, wil, &fops_sta);
debugfs_create_file("desc", S_IRUGO, dbg, wil, &fops_txdesc);
debugfs_create_u32("desc_index", S_IRUGO | S_IWUSR, dbg,
&dbg_txdesc_index);
debugfs_create_u32("vring_index", S_IRUGO | S_IWUSR, dbg,
&dbg_vring_index);
debugfs_create_file("bf", S_IRUGO, dbg, wil, &fops_bf);
debugfs_create_file("ssid", S_IRUGO | S_IWUSR, dbg, wil, &fops_ssid);
debugfs_create_u32("secure_pcp", S_IRUGO | S_IWUSR, dbg,
&wil->secure_pcp);
wil_debugfs_create_ulong("status", S_IRUGO | S_IWUSR, dbg,
&wil->status);
debugfs_create_u32("fw_version", S_IRUGO, dbg, &wil->fw_version);
debugfs_create_x32("hw_version", S_IRUGO, dbg, &wil->hw_version);
wil6210_debugfs_create_ISR(wil, "USER_ICR", dbg,
HOSTADDR(RGF_USER_USER_ICR));
wil6210_debugfs_create_ISR(wil, "DMA_EP_TX_ICR", dbg,
HOSTADDR(RGF_DMA_EP_TX_ICR));
wil6210_debugfs_create_ISR(wil, "DMA_EP_RX_ICR", dbg,
HOSTADDR(RGF_DMA_EP_RX_ICR));
wil6210_debugfs_create_ISR(wil, "DMA_EP_MISC_ICR", dbg,
HOSTADDR(RGF_DMA_EP_MISC_ICR));
wil6210_debugfs_create_pseudo_ISR(wil, dbg);
wil6210_debugfs_create_ITR_CNT(wil, dbg);
wil_debugfs_create_iomem_x32("RGF_USER_USAGE_1", S_IRUGO, dbg,
wil->csr +
HOSTADDR(RGF_USER_USAGE_1));
debugfs_create_u32("mem_addr", S_IRUGO | S_IWUSR, dbg, &mem_addr);
debugfs_create_file("mem_val", S_IRUGO, dbg, wil, &fops_memread);
debugfs_create_file("reset", S_IWUSR, dbg, wil, &fops_reset);
debugfs_create_file("rxon", S_IWUSR, dbg, wil, &fops_rxon);
debugfs_create_file("tx_mgmt", S_IWUSR, dbg, wil, &fops_txmgmt);
debugfs_create_file("wmi_send", S_IWUSR, dbg, wil, &fops_wmi);
debugfs_create_file("temp", S_IRUGO, dbg, wil, &fops_temp);
debugfs_create_file("freq", S_IRUGO, dbg, wil, &fops_freq);
debugfs_create_file("link", S_IRUGO, dbg, wil, &fops_link);
debugfs_create_file("info", S_IRUGO, dbg, wil, &fops_info);
wil6210_debugfs_init_blobs(wil, dbg);
return 0;
}
static int vc_mem_debugfs_init(
struct device *dev)
{
vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
if (!vc_mem_debugfs_entry) {
dev_warn(dev, "could not create debugfs entry\n");
return -EFAULT;
}
if (!debugfs_create_x32("vc_mem_phys_addr",
0444,
vc_mem_debugfs_entry,
(u32 *)&mm_vc_mem_phys_addr)) {
dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
__func__);
goto fail;
}
if (!debugfs_create_x32("vc_mem_size",
0444,
vc_mem_debugfs_entry,
(u32 *)&mm_vc_mem_size)) {
dev_warn(dev, "%s:could not create vc_mem_size entry\n",
__func__);
goto fail;
}
if (!debugfs_create_x32("vc_mem_base",
0444,
vc_mem_debugfs_entry,
(u32 *)&mm_vc_mem_base)) {
dev_warn(dev, "%s:could not create vc_mem_base entry\n",
__func__);
goto fail;
}
return 0;
fail:
vc_mem_debugfs_deinit();
return -EFAULT;
}
static void rk_mmc_init_debugfs(struct rk_mmc *host)
{
struct mmc_host *mmc = host->mmc;
struct dentry *root;
struct dentry *node;
root = mmc->debugfs_root;
if (!root)
return;
node = debugfs_create_file("regs", S_IRUSR, root, host,
&rk_mmc_regs_fops);
if (!node)
goto err;
node = debugfs_create_file("req", S_IRUSR, root, host,
&rk_mmc_req_fops);
if (!node)
goto err;
node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
if (!node)
goto err;
node = debugfs_create_x32("pending_events", S_IRUSR, root,
(u32 *)&host->pending_events);
if (!node)
goto err;
node = debugfs_create_x32("completed_events", S_IRUSR, root,
(u32 *)&host->completed_events);
if (!node)
goto err;
return;
err:
dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
}
void mmc_add_card_debugfs(struct mmc_card *card)
{
struct mmc_host *host = card->host;
struct dentry *root;
if (!host->debugfs_root)
return;
root = debugfs_create_dir(mmc_card_id(card), host->debugfs_root);
if (IS_ERR(root))
return;
if (!root)
goto err;
card->debugfs_root = root;
if (!debugfs_create_x32("state", S_IRUSR, root, &card->state))
goto err;
if (mmc_card_mmc(card) || mmc_card_sd(card))
if (!debugfs_create_file("status", S_IRUSR, root, card,
&mmc_dbg_card_status_fops))
goto err;
if (mmc_card_mmc(card))
if (!debugfs_create_file("ext_csd", S_IRUSR, root, card,
&mmc_dbg_ext_csd_fops))
goto err;
if (mmc_card_mmc(card) && (card->ext_csd.rev >= 6) &&
(card->host->caps2 & MMC_CAP2_PACKED_WR))
if (!debugfs_create_file("wr_pack_stats", S_IRUSR, root, card,
&mmc_dbg_wr_pack_stats_fops))
goto err;
if (mmc_card_mmc(card) && (card->ext_csd.rev >= 5) &&
card->ext_csd.bkops_en)
if (!debugfs_create_file("bkops_stats", S_IRUSR, root, card,
&mmc_dbg_bkops_stats_fops))
goto err;
return;
err:
debugfs_remove_recursive(root);
card->debugfs_root = NULL;
dev_err(&card->dev, "failed to initialize debugfs\n");
}
void opchg_debugfs_create(struct opchg_charger *chip)
{
int rc = 0;
chip->debug_root = debugfs_create_dir("opchg", NULL);//debugfs_create_dir("smb358", NULL);
if (!chip->debug_root) {
dev_err(chip->dev, "Couldn't create debug dir\n");
}
if (chip->debug_root) {
struct dentry *ent;
ent = debugfs_create_file("config_registers", S_IFREG | S_IRUGO,
chip->debug_root, chip,
&cnfg_debugfs_ops);
if (!ent) {
dev_err(chip->dev, "Couldn't create cnfg debug file rc = %d\n", rc);
}
ent = debugfs_create_file("status_registers", S_IFREG | S_IRUGO,
chip->debug_root, chip,
&status_debugfs_ops);
if (!ent) {
dev_err(chip->dev, "Couldn't create status debug file rc = %d\n", rc);
}
ent = debugfs_create_file("cmd_registers", S_IFREG | S_IRUGO,
chip->debug_root, chip,
&cmd_debugfs_ops);
if (!ent) {
dev_err(chip->dev, "Couldn't create cmd debug file rc = %d\n", rc);
}
ent = debugfs_create_x32("address", S_IFREG | S_IWUSR | S_IRUGO,
chip->debug_root,
&(chip->peek_poke_address));
if (!ent) {
dev_err(chip->dev, "Couldn't create address debug file rc = %d\n", rc);
}
ent = debugfs_create_file("data", S_IFREG | S_IWUSR | S_IRUGO,
chip->debug_root, chip,
&poke_poke_debug_ops);
if (!ent) {
dev_err(chip->dev, "Couldn't create data debug file rc = %d\n", rc);
}
}
}
static int __init tegra_cpuidle_debug_init(void)
{
struct dentry *dir;
struct dentry *d;
dir = debugfs_create_dir("cpuidle", NULL);
if (!dir)
return -ENOMEM;
d = debugfs_create_file("power_down_stats", S_IRUGO, dir, NULL,
&tegra_pd_debug_ops);
if (!d)
return -ENOMEM;
#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
d = debugfs_create_x32("force_clkgt_at_vmin", S_IRUGO | S_IWUSR,
dir, &tegra_force_clkgt_at_vmin);
if (!d)
return -ENOMEM;
#endif
return 0;
}
static int acpi_ec_add_debugfs(struct acpi_ec *ec, unsigned int ec_device_count)
{
struct dentry *dev_dir;
char name[64];
umode_t mode = 0400;
if (ec_device_count == 0) {
acpi_ec_debugfs_dir = debugfs_create_dir("ec", NULL);
if (!acpi_ec_debugfs_dir)
return -ENOMEM;
}
sprintf(name, "ec%u", ec_device_count);
dev_dir = debugfs_create_dir(name, acpi_ec_debugfs_dir);
if (!dev_dir) {
if (ec_device_count != 0)
goto error;
return -ENOMEM;
}
if (!debugfs_create_x32("gpe", 0444, dev_dir, (u32 *)&first_ec->gpe))
goto error;
if (!debugfs_create_bool("use_global_lock", 0444, dev_dir,
&first_ec->global_lock))
goto error;
if (write_support)
mode = 0600;
if (!debugfs_create_file("io", mode, dev_dir, ec, &acpi_ec_io_ops))
goto error;
return 0;
error:
debugfs_remove_recursive(acpi_ec_debugfs_dir);
return -ENOMEM;
}
static int __init kernel_trace_init(void)
{
struct dentry *d;
struct dentry *perf_para_root;
int i;
/*In order to mmap g_perf_para to userspace, the memory size should be at least one page.*/
g_perf_para = (unsigned int *)get_zeroed_page(GFP_KERNEL);
if (NULL == g_perf_para)
{
printk(KERN_ERR "trace_kernel[E] kernel_trace_init g_perf_para=NULL\n");
return -ENOMEM;
}
d = debugfs_create_dir("perf_para", NULL);
perf_para_root = d;
d = debugfs_create_file("perf_para", S_IWUSR|S_IWGRP|S_IRUGO, perf_para_root, NULL, &kernel_trace_fops);
for (i=0; i<MODULE_ID_MAX; i++)
{
debugfs_create_x32(tracedot_name[i], S_IWUSR|S_IWGRP|S_IRUGO, perf_para_root, (unsigned int *)(g_perf_para + i));
}
return 0;
}
static int ncp6335d_regulator_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
int rc;
unsigned int val = 0;
struct ncp6335d_info *dd;
const struct ncp6335d_platform_data *pdata;
struct regulator_config config = { };
if (client->dev.of_node)
pdata = ncp6335d_get_of_platform_data(client);
else
pdata = client->dev.platform_data;
if (!pdata) {
dev_err(&client->dev, "Platform data not specified\n");
return -EINVAL;
}
dd = devm_kzalloc(&client->dev, sizeof(*dd), GFP_KERNEL);
if (!dd) {
dev_err(&client->dev, "Unable to allocate memory\n");
return -ENOMEM;
}
if (client->dev.of_node) {
rc = ncp6335d_parse_dt(client, dd);
if (rc)
return rc;
} else {
dd->step_size = NCP6335D_STEP_VOLTAGE_UV;
dd->min_voltage = NCP6335D_MIN_VOLTAGE_UV;
dd->min_slew_ns = NCP6335D_MIN_SLEW_NS;
dd->max_slew_ns = NCP6335D_MAX_SLEW_NS;
}
dd->regmap = devm_regmap_init_i2c(client, &ncp6335d_regmap_config);
if (IS_ERR(dd->regmap)) {
dev_err(&client->dev, "Error allocating regmap\n");
return PTR_ERR(dd->regmap);
}
rc = ncp6335x_read(dd, REG_NCP6335D_PID, &val);
if (rc) {
dev_err(&client->dev, "Unable to identify NCP6335D, rc(%d)\n",
rc);
return rc;
}
dev_info(&client->dev, "Detected Regulator NCP6335D PID = %d\n", val);
dd->init_data = pdata->init_data;
dd->dev = &client->dev;
i2c_set_clientdata(client, dd);
rc = ncp6335d_init(client, dd, pdata);
if (rc) {
dev_err(&client->dev, "Unable to intialize the regulator\n");
return -EINVAL;
}
config.dev = &client->dev;
config.init_data = dd->init_data;
config.regmap = dd->regmap;
config.driver_data = dd;
config.of_node = client->dev.of_node;
dd->regulator = regulator_register(&rdesc, &config);
if (IS_ERR(dd->regulator)) {
dev_err(&client->dev, "Unable to register regulator rc(%ld)",
PTR_ERR(dd->regulator));
return PTR_ERR(dd->regulator);
}
dd->debug_root = debugfs_create_dir("ncp6335x", NULL);
if (!dd->debug_root)
dev_err(&client->dev, "Couldn't create debug dir\n");
if (dd->debug_root) {
struct dentry *ent;
ent = debugfs_create_x32("address", S_IFREG | S_IWUSR | S_IRUGO,
dd->debug_root,
&(dd->peek_poke_address));
if (!ent)
dev_err(&client->dev, "Couldn't create address debug file rc = %d\n",
rc);
ent = debugfs_create_file("data", S_IFREG | S_IWUSR | S_IRUGO,
dd->debug_root, dd,
&poke_poke_debug_ops);
if (!ent)
dev_err(&client->dev, "Couldn't create data debug file rc = %d\n",
rc);
}
return 0;
}
void mmc_add_card_debugfs(struct mmc_card *card)
{
struct mmc_host *host = card->host;
struct dentry *root = NULL;
struct dentry *sdxc_root = NULL;
if (!host->debugfs_root)
return;
sdxc_root = debugfs_create_dir("sdxc_root", host->debugfs_root);
if (IS_ERR(sdxc_root))
return;
if (!sdxc_root)
goto err;
root = debugfs_create_dir(mmc_card_id(card), host->debugfs_root);
if (IS_ERR(root))
/* Don't complain -- debugfs just isn't enabled */
return;
if (!root)
/* Complain -- debugfs is enabled, but it failed to
* create the directory. */
goto err;
card->debugfs_sdxc = sdxc_root;
card->debugfs_root = root;
if (!debugfs_create_x32("state", S_IRUSR, root, &card->state))
goto err;
if (mmc_card_mmc(card) || mmc_card_sd(card))
if (!debugfs_create_file("status", S_IRUSR, root, card,
&mmc_dbg_card_status_fops))
goto err;
if (mmc_card_mmc(card))
if (!debugfs_create_file("ext_csd", S_IRUSR, root, card,
&mmc_dbg_ext_csd_fops))
goto err;
if (mmc_card_sd(card))
if (!debugfs_create_file("sdxc", S_IRUSR, sdxc_root, card,
&mmc_sdxc_fops))
goto err;
#ifdef CONFIG_HW_MMC_TEST
if (mmc_card_mmc(card))
if (!debugfs_create_file("card_addr", S_IRUSR, root, card,
&mmc_dbg_card_addr_fops))
goto err;
if (mmc_card_mmc(card))
if (!debugfs_create_file("test_st", S_IRUSR, root, card,
&mmc_dbg_test_st_fops))
goto err;
#endif
return;
err:
debugfs_remove_recursive(root);
debugfs_remove_recursive(sdxc_root);
card->debugfs_root = NULL;
card->debugfs_sdxc = NULL;
dev_err(&card->dev, "failed to initialize debugfs\n");
}
static int ncp6335d_regulator_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
int rc;
unsigned int val = 0;
struct ncp6335d_info *dd;
const struct ncp6335d_platform_data *pdata;
struct regulator_config config = { };
#ifdef CONFIG_MACH_YULONG
/* the i2c address of ncp6335d is somehow changed, trying to poll if failed.
[email protected] 2014-12-29*/
int i2c_addr_backup[3] = { 0x18, 0x10, 0x14};
int i_a = 0;
pr_err("%s:ncp addr is 0x%2x\n",__func__,client->addr);
#endif
if (client->dev.of_node)
pdata = ncp6335d_get_of_platform_data(client);
else
pdata = client->dev.platform_data;
if (!pdata) {
dev_err(&client->dev, "Platform data not specified\n");
return -EINVAL;
}
dd = devm_kzalloc(&client->dev, sizeof(*dd), GFP_KERNEL);
if (!dd) {
dev_err(&client->dev, "Unable to allocate memory\n");
return -ENOMEM;
}
if (client->dev.of_node) {
rc = ncp6335d_parse_dt(client, dd);
if (rc)
return rc;
} else {
dd->step_size = NCP6335D_STEP_VOLTAGE_UV;
dd->min_voltage = NCP6335D_MIN_VOLTAGE_UV;
dd->min_slew_ns = NCP6335D_MIN_SLEW_NS;
dd->max_slew_ns = NCP6335D_MAX_SLEW_NS;
}
dd->regmap = devm_regmap_init_i2c(client, &ncp6335d_regmap_config);
if (IS_ERR(dd->regmap)) {
dev_err(&client->dev, "Error allocating regmap\n");
return PTR_ERR(dd->regmap);
}
#ifdef CONFIG_MACH_YULONG
AGAIN:
#endif
rc = ncp6335x_read(dd, REG_NCP6335D_PID, &val);
if (rc) {
dev_err(&client->dev, "Unable to identify NCP6335D, rc(%d)\n",
rc);
#ifdef CONFIG_MACH_YULONG
dev_err(&client->dev, "ncp addr is 0x%2x, force addr as 0x%2x and retry\n",
client->addr, i2c_addr_backup[i_a]);
while (i_a < 3) {
client->addr = i2c_addr_backup[i_a];
i_a++;
goto AGAIN;
}
#endif
return rc;
}
dev_info(&client->dev, "Detected Regulator NCP6335D PID = %d\n", val);
dd->init_data = pdata->init_data;
dd->dev = &client->dev;
i2c_set_clientdata(client, dd);
mutex_init(&dd->ncp_mutex);
rc = ncp6335d_init(client, dd, pdata);
if (rc) {
dev_err(&client->dev, "Unable to intialize the regulator\n");
return -EINVAL;
}
config.dev = &client->dev;
config.init_data = dd->init_data;
config.regmap = dd->regmap;
config.driver_data = dd;
config.of_node = client->dev.of_node;
dd->regulator = regulator_register(&rdesc, &config);
if (IS_ERR(dd->regulator)) {
dev_err(&client->dev, "Unable to register regulator rc(%ld)",
PTR_ERR(dd->regulator));
return PTR_ERR(dd->regulator);
}
dd->debug_root = debugfs_create_dir("ncp6335x", NULL);
if (!dd->debug_root)
dev_err(&client->dev, "Couldn't create debug dir\n");
if (dd->debug_root) {
struct dentry *ent;
ent = debugfs_create_x32("address", S_IFREG | S_IWUSR | S_IRUGO,
dd->debug_root,
&(dd->peek_poke_address));
if (!ent)
dev_err(&client->dev, "Couldn't create address debug file rc = %d\n",
rc);
ent = debugfs_create_file("data", S_IFREG | S_IWUSR | S_IRUGO,
dd->debug_root, dd,
&poke_poke_debug_ops);
if (!ent)
dev_err(&client->dev, "Couldn't create data debug file rc = %d\n",
rc);
}
return 0;
}
int b2r2_debug_init(struct b2r2_control *cont)
{
int i;
if (!module_init) {
for (i = 0; i < B2R2_LOG_LEVEL_COUNT; i++)
b2r2_log_levels[i] = 0;
#if !defined(CONFIG_DYNAMIC_DEBUG) && defined(CONFIG_DEBUG_FS)
/*
* If dynamic debug is disabled we need some other way to
* control the log prints
*/
log_lvl_dir = debugfs_create_dir("b2r2_log", NULL);
/* No need to save the files,
* they will be removed recursively */
if (!IS_ERR_OR_NULL(log_lvl_dir)) {
(void)debugfs_create_bool("warnings", 0644, log_lvl_dir,
&b2r2_log_levels[B2R2_LOG_LEVEL_WARN]);
(void)debugfs_create_bool("info", 0644, log_lvl_dir,
&b2r2_log_levels[B2R2_LOG_LEVEL_INFO]);
(void)debugfs_create_bool("debug", 0644, log_lvl_dir,
&b2r2_log_levels[B2R2_LOG_LEVEL_DEBUG]);
(void)debugfs_create_bool("regdumps", 0644, log_lvl_dir,
&b2r2_log_levels[B2R2_LOG_LEVEL_REGDUMP]);
}
#elif defined(CONFIG_DYNAMIC_DEBUG)
/* log_lvl_dir is never used */
(void)log_lvl_dir;
#endif
module_init++;
}
if (!IS_ERR_OR_NULL(cont->debugfs_debug_root_dir)) {
/* No need to save the file,
* it will be removed recursively */
(void)debugfs_create_file("last_job", 0444,
cont->debugfs_debug_root_dir, cont,
&last_job_fops);
}
if (!IS_ERR_OR_NULL(cont->debugfs_debug_root_dir)) {
cont->dump.debugfs_root_dir =
debugfs_create_dir("dump",
cont->debugfs_debug_root_dir);
if (!IS_ERR_OR_NULL(cont->dump.debugfs_root_dir)) {
(void)debugfs_create_x32("src_filter", 0644,
cont->dump.debugfs_root_dir,
&cont->dump.src_filter);
(void)debugfs_create_x32("dst_filter", 0644,
cont->dump.debugfs_root_dir,
&cont->dump.dst_filter);
(void)debugfs_create_file("capture", 0444,
cont->dump.debugfs_root_dir,
cont, &capture_buffers_fops);
}
}
mutex_init(&cont->last_job_lock);
mutex_init(&cont->dump.lock);
return 0;
}
static int smb349_charger_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
int rc, irq;
struct smb349_charger *chip;
struct power_supply *usb_psy;
u8 reg = 0;
usb_psy = power_supply_get_by_name("usb");
if (!usb_psy) {
dev_dbg(&client->dev, "USB psy not found; deferring probe\n");
return -EPROBE_DEFER;
}
chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
if (!chip) {
dev_err(&client->dev, "Couldn't allocate memory\n");
return -ENOMEM;
}
chip->client = client;
chip->dev = &client->dev;
chip->usb_psy = usb_psy;
chip->fake_battery_soc = -EINVAL;
/* probe the device to check if its actually connected */
rc = smb349_read_reg(chip, CHG_OTH_CURRENT_CTRL_REG, ®);
if (rc) {
pr_err("Failed to detect SMB349, device may be absent\n");
return -ENODEV;
}
rc = smb_parse_dt(chip);
if (rc) {
dev_err(&client->dev, "Couldn't parse DT nodes rc=%d\n", rc);
return rc;
}
i2c_set_clientdata(client, chip);
chip->batt_psy.name = "battery";
chip->batt_psy.type = POWER_SUPPLY_TYPE_BATTERY;
chip->batt_psy.get_property = smb349_battery_get_property;
chip->batt_psy.set_property = smb349_battery_set_property;
chip->batt_psy.property_is_writeable =
smb349_batt_property_is_writeable;
chip->batt_psy.properties = smb349_battery_properties;
chip->batt_psy.num_properties = ARRAY_SIZE(smb349_battery_properties);
chip->batt_psy.external_power_changed = smb349_external_power_changed;
chip->resume_completed = true;
init_completion(&chip->resumed);
mutex_init(&chip->irq_complete);
rc = power_supply_register(chip->dev, &chip->batt_psy);
if (rc < 0) {
dev_err(&client->dev, "Couldn't register batt psy rc=%d\n",
rc);
return rc;
}
dump_regs(chip);
rc = smb349_regulator_init(chip);
if (rc) {
dev_err(&client->dev,
"Couldn't initialize smb349 ragulator rc=%d\n", rc);
return rc;
}
rc = smb349_hw_init(chip);
if (rc) {
dev_err(&client->dev,
"Couldn't intialize hardware rc=%d\n", rc);
goto fail_smb349_hw_init;
}
rc = determine_initial_state(chip);
if (rc) {
dev_err(&client->dev,
"Couldn't determine initial state rc=%d\n", rc);
goto fail_smb349_hw_init;
}
if (gpio_is_valid(chip->chg_valid_gpio)) {
rc = gpio_request(chip->chg_valid_gpio, "smb349_chg_valid");
if (rc) {
dev_err(&client->dev,
"gpio_request for %d failed rc=%d\n",
chip->chg_valid_gpio, rc);
goto fail_smb349_hw_init;
}
irq = gpio_to_irq(chip->chg_valid_gpio);
if (irq < 0) {
dev_err(&client->dev,
"Invalid chg_valid irq = %d\n", irq);
goto fail_chg_valid_irq;
}
rc = devm_request_threaded_irq(&client->dev, irq,
NULL, smb349_chg_valid_handler,
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
"smb349_chg_valid_irq", chip);
if (rc) {
dev_err(&client->dev,
"Failed request_irq irq=%d, gpio=%d rc=%d\n",
irq, chip->chg_valid_gpio, rc);
goto fail_chg_valid_irq;
}
smb349_chg_valid_handler(irq, chip);
enable_irq_wake(irq);
}
/* STAT irq configuration */
if (client->irq) {
rc = devm_request_threaded_irq(&client->dev, client->irq, NULL,
smb349_chg_stat_handler,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
"smb349_chg_stat_irq", chip);
if (rc) {
dev_err(&client->dev,
"Failed STAT irq=%d request rc = %d\n",
client->irq, rc);
goto fail_chg_valid_irq;
}
enable_irq_wake(client->irq);
}
chip->debug_root = debugfs_create_dir("smb349", NULL);
if (!chip->debug_root)
dev_err(chip->dev, "Couldn't create debug dir\n");
if (chip->debug_root) {
struct dentry *ent;
ent = debugfs_create_file("config_registers", S_IFREG | S_IRUGO,
chip->debug_root, chip,
&cnfg_debugfs_ops);
if (!ent)
dev_err(chip->dev,
"Couldn't create cnfg debug file rc = %d\n",
rc);
ent = debugfs_create_file("status_registers", S_IFREG | S_IRUGO,
chip->debug_root, chip,
&status_debugfs_ops);
if (!ent)
dev_err(chip->dev,
"Couldn't create status debug file rc = %d\n",
rc);
ent = debugfs_create_file("cmd_registers", S_IFREG | S_IRUGO,
chip->debug_root, chip,
&cmd_debugfs_ops);
if (!ent)
dev_err(chip->dev,
"Couldn't create cmd debug file rc = %d\n",
rc);
ent = debugfs_create_x32("address", S_IFREG | S_IWUSR | S_IRUGO,
chip->debug_root,
&(chip->peek_poke_address));
if (!ent)
dev_err(chip->dev,
"Couldn't create address debug file rc = %d\n",
rc);
ent = debugfs_create_file("data", S_IFREG | S_IWUSR | S_IRUGO,
chip->debug_root, chip,
&poke_poke_debug_ops);
if (!ent)
dev_err(chip->dev,
"Couldn't create data debug file rc = %d\n",
rc);
ent = debugfs_create_file("force_irq",
S_IFREG | S_IWUSR | S_IRUGO,
chip->debug_root, chip,
&force_irq_ops);
if (!ent)
dev_err(chip->dev,
"Couldn't create data debug file rc = %d\n",
rc);
ent = debugfs_create_file("irq_count", S_IFREG | S_IRUGO,
chip->debug_root, chip,
&irq_count_debugfs_ops);
if (!ent)
dev_err(chip->dev,
"Couldn't create count debug file rc = %d\n",
rc);
}
dump_regs(chip);
dev_info(chip->dev, "SMB349 successfully probed. charger=%d, batt=%d\n",
chip->chg_present, smb349_get_prop_batt_present(chip));
return 0;
fail_chg_valid_irq:
if (gpio_is_valid(chip->chg_valid_gpio))
gpio_free(chip->chg_valid_gpio);
fail_smb349_hw_init:
power_supply_unregister(&chip->batt_psy);
regulator_unregister(chip->otg_vreg.rdev);
return rc;
}
static int __init bfin_debug_mmrs_init(void)
{
struct dentry *top, *parent;
pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
top = debugfs_create_dir("blackfin", NULL);
if (top == NULL)
return -1;
parent = debugfs_create_dir("core_regs", top);
debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
D_SYSREG(cycles);
D_SYSREG(cycles2);
D_SYSREG(emudat);
D_SYSREG(seqstat);
D_SYSREG(syscfg);
parent = debugfs_create_dir("ctimer", top);
D32(TCNTL);
D32(TCOUNT);
D32(TPERIOD);
D32(TSCALE);
parent = debugfs_create_dir("cec", top);
D32(EVT0);
D32(EVT1);
D32(EVT2);
D32(EVT3);
D32(EVT4);
D32(EVT5);
D32(EVT6);
D32(EVT7);
D32(EVT8);
D32(EVT9);
D32(EVT10);
D32(EVT11);
D32(EVT12);
D32(EVT13);
D32(EVT14);
D32(EVT15);
D32(EVT_OVERRIDE);
D32(IMASK);
D32(IPEND);
D32(ILAT);
D32(IPRIO);
parent = debugfs_create_dir("debug", top);
D32(DBGSTAT);
D32(DSPID);
parent = debugfs_create_dir("mmu", top);
D32(SRAM_BASE_ADDRESS);
D32(DCPLB_ADDR0);
D32(DCPLB_ADDR10);
D32(DCPLB_ADDR11);
D32(DCPLB_ADDR12);
D32(DCPLB_ADDR13);
D32(DCPLB_ADDR14);
D32(DCPLB_ADDR15);
D32(DCPLB_ADDR1);
D32(DCPLB_ADDR2);
D32(DCPLB_ADDR3);
D32(DCPLB_ADDR4);
D32(DCPLB_ADDR5);
D32(DCPLB_ADDR6);
D32(DCPLB_ADDR7);
D32(DCPLB_ADDR8);
D32(DCPLB_ADDR9);
D32(DCPLB_DATA0);
D32(DCPLB_DATA10);
D32(DCPLB_DATA11);
D32(DCPLB_DATA12);
D32(DCPLB_DATA13);
D32(DCPLB_DATA14);
D32(DCPLB_DATA15);
D32(DCPLB_DATA1);
D32(DCPLB_DATA2);
D32(DCPLB_DATA3);
D32(DCPLB_DATA4);
D32(DCPLB_DATA5);
D32(DCPLB_DATA6);
D32(DCPLB_DATA7);
D32(DCPLB_DATA8);
D32(DCPLB_DATA9);
D32(DCPLB_FAULT_ADDR);
D32(DCPLB_STATUS);
D32(DMEM_CONTROL);
D32(DTEST_COMMAND);
D32(DTEST_DATA0);
D32(DTEST_DATA1);
D32(ICPLB_ADDR0);
D32(ICPLB_ADDR1);
D32(ICPLB_ADDR2);
D32(ICPLB_ADDR3);
D32(ICPLB_ADDR4);
D32(ICPLB_ADDR5);
D32(ICPLB_ADDR6);
D32(ICPLB_ADDR7);
D32(ICPLB_ADDR8);
D32(ICPLB_ADDR9);
D32(ICPLB_ADDR10);
D32(ICPLB_ADDR11);
D32(ICPLB_ADDR12);
D32(ICPLB_ADDR13);
D32(ICPLB_ADDR14);
D32(ICPLB_ADDR15);
D32(ICPLB_DATA0);
D32(ICPLB_DATA1);
D32(ICPLB_DATA2);
D32(ICPLB_DATA3);
D32(ICPLB_DATA4);
D32(ICPLB_DATA5);
D32(ICPLB_DATA6);
D32(ICPLB_DATA7);
D32(ICPLB_DATA8);
D32(ICPLB_DATA9);
D32(ICPLB_DATA10);
D32(ICPLB_DATA11);
D32(ICPLB_DATA12);
D32(ICPLB_DATA13);
D32(ICPLB_DATA14);
D32(ICPLB_DATA15);
D32(ICPLB_FAULT_ADDR);
D32(ICPLB_STATUS);
D32(IMEM_CONTROL);
if (!ANOMALY_05000481) {
D32(ITEST_COMMAND);
D32(ITEST_DATA0);
D32(ITEST_DATA1);
}
parent = debugfs_create_dir("perf", top);
D32(PFCNTR0);
D32(PFCNTR1);
D32(PFCTL);
parent = debugfs_create_dir("trace", top);
D32(TBUF);
D32(TBUFCTL);
D32(TBUFSTAT);
parent = debugfs_create_dir("watchpoint", top);
D32(WPIACTL);
D32(WPIA0);
D32(WPIA1);
D32(WPIA2);
D32(WPIA3);
D32(WPIA4);
D32(WPIA5);
D32(WPIACNT0);
D32(WPIACNT1);
D32(WPIACNT2);
D32(WPIACNT3);
D32(WPIACNT4);
D32(WPIACNT5);
D32(WPDACTL);
D32(WPDA0);
D32(WPDA1);
D32(WPDACNT0);
D32(WPDACNT1);
D32(WPSTAT);
#ifdef ATAPI_CONTROL
parent = debugfs_create_dir("atapi", top);
D16(ATAPI_CONTROL);
D16(ATAPI_DEV_ADDR);
D16(ATAPI_DEV_RXBUF);
D16(ATAPI_DEV_TXBUF);
D16(ATAPI_DMA_TFRCNT);
D16(ATAPI_INT_MASK);
D16(ATAPI_INT_STATUS);
D16(ATAPI_LINE_STATUS);
D16(ATAPI_MULTI_TIM_0);
D16(ATAPI_MULTI_TIM_1);
D16(ATAPI_MULTI_TIM_2);
D16(ATAPI_PIO_TFRCNT);
D16(ATAPI_PIO_TIM_0);
D16(ATAPI_PIO_TIM_1);
D16(ATAPI_REG_TIM_0);
D16(ATAPI_SM_STATE);
D16(ATAPI_STATUS);
D16(ATAPI_TERMINATE);
D16(ATAPI_UDMAOUT_TFRCNT);
D16(ATAPI_ULTRA_TIM_0);
D16(ATAPI_ULTRA_TIM_1);
D16(ATAPI_ULTRA_TIM_2);
D16(ATAPI_ULTRA_TIM_3);
D16(ATAPI_UMAIN_TFRCNT);
D16(ATAPI_XFER_LEN);
#endif
#if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
parent = debugfs_create_dir("can", top);
# ifdef CAN_MC1
bfin_debug_mmrs_can(parent, CAN_MC1, -1);
# endif
# ifdef CAN0_MC1
CAN(0);
# endif
# ifdef CAN1_MC1
CAN(1);
# endif
#endif
#ifdef CNT_COMMAND
parent = debugfs_create_dir("counter", top);
D16(CNT_COMMAND);
D16(CNT_CONFIG);
D32(CNT_COUNTER);
D16(CNT_DEBOUNCE);
D16(CNT_IMASK);
D32(CNT_MAX);
D32(CNT_MIN);
D16(CNT_STATUS);
#endif
parent = debugfs_create_dir("dmac", top);
#ifdef DMAC_TC_CNT
D16(DMAC_TC_CNT);
D16(DMAC_TC_PER);
#endif
#ifdef DMAC0_TC_CNT
D16(DMAC0_TC_CNT);
D16(DMAC0_TC_PER);
#endif
#ifdef DMAC1_TC_CNT
D16(DMAC1_TC_CNT);
D16(DMAC1_TC_PER);
#endif
#ifdef DMAC1_PERIMUX
D16(DMAC1_PERIMUX);
#endif
#ifdef __ADSPBF561__
# define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
# define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
# define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
# define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
# define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
# define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
# define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
# define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
# define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
# define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
# define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
# define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
# define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
# define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
# define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
# define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
# define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
# define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
# define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
# define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
# define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
# define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
# define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
# define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
#endif
parent = debugfs_create_dir("dma", top);
DMA(0);
DMA(1);
DMA(1);
DMA(2);
DMA(3);
DMA(4);
DMA(5);
DMA(6);
DMA(7);
#ifdef DMA8_NEXT_DESC_PTR
DMA(8);
DMA(9);
DMA(10);
DMA(11);
#endif
#ifdef DMA12_NEXT_DESC_PTR
DMA(12);
DMA(13);
DMA(14);
DMA(15);
DMA(16);
DMA(17);
DMA(18);
DMA(19);
#endif
#ifdef DMA20_NEXT_DESC_PTR
DMA(20);
DMA(21);
DMA(22);
DMA(23);
#endif
parent = debugfs_create_dir("ebiu_amc", top);
D32(EBIU_AMBCTL0);
D32(EBIU_AMBCTL1);
D16(EBIU_AMGCTL);
#ifdef EBIU_MBSCTL
D16(EBIU_MBSCTL);
D32(EBIU_ARBSTAT);
D32(EBIU_MODE);
D16(EBIU_FCTL);
#endif
#ifdef EBIU_SDGCTL
parent = debugfs_create_dir("ebiu_sdram", top);
# ifdef __ADSPBF561__
D32(EBIU_SDBCTL);
# else
D16(EBIU_SDBCTL);
# endif
D32(EBIU_SDGCTL);
D16(EBIU_SDRRC);
D16(EBIU_SDSTAT);
#endif
#ifdef EBIU_DDRACCT
parent = debugfs_create_dir("ebiu_ddr", top);
D32(EBIU_DDRACCT);
D32(EBIU_DDRARCT);
D32(EBIU_DDRBRC0);
D32(EBIU_DDRBRC1);
D32(EBIU_DDRBRC2);
D32(EBIU_DDRBRC3);
D32(EBIU_DDRBRC4);
D32(EBIU_DDRBRC5);
D32(EBIU_DDRBRC6);
D32(EBIU_DDRBRC7);
D32(EBIU_DDRBWC0);
D32(EBIU_DDRBWC1);
D32(EBIU_DDRBWC2);
D32(EBIU_DDRBWC3);
D32(EBIU_DDRBWC4);
D32(EBIU_DDRBWC5);
D32(EBIU_DDRBWC6);
D32(EBIU_DDRBWC7);
D32(EBIU_DDRCTL0);
D32(EBIU_DDRCTL1);
D32(EBIU_DDRCTL2);
D32(EBIU_DDRCTL3);
D32(EBIU_DDRGC0);
D32(EBIU_DDRGC1);
D32(EBIU_DDRGC2);
D32(EBIU_DDRGC3);
D32(EBIU_DDRMCCL);
D32(EBIU_DDRMCEN);
D32(EBIU_DDRQUE);
D32(EBIU_DDRTACT);
D32(EBIU_ERRADD);
D16(EBIU_ERRMST);
D16(EBIU_RSTCTL);
#endif
#ifdef EMAC_ADDRHI
parent = debugfs_create_dir("emac", top);
D32(EMAC_ADDRHI);
D32(EMAC_ADDRLO);
D32(EMAC_FLC);
D32(EMAC_HASHHI);
D32(EMAC_HASHLO);
D32(EMAC_MMC_CTL);
D32(EMAC_MMC_RIRQE);
D32(EMAC_MMC_RIRQS);
D32(EMAC_MMC_TIRQE);
D32(EMAC_MMC_TIRQS);
D32(EMAC_OPMODE);
D32(EMAC_RXC_ALIGN);
D32(EMAC_RXC_ALLFRM);
D32(EMAC_RXC_ALLOCT);
D32(EMAC_RXC_BROAD);
D32(EMAC_RXC_DMAOVF);
D32(EMAC_RXC_EQ64);
D32(EMAC_RXC_FCS);
D32(EMAC_RXC_GE1024);
D32(EMAC_RXC_LNERRI);
D32(EMAC_RXC_LNERRO);
D32(EMAC_RXC_LONG);
D32(EMAC_RXC_LT1024);
D32(EMAC_RXC_LT128);
D32(EMAC_RXC_LT256);
D32(EMAC_RXC_LT512);
D32(EMAC_RXC_MACCTL);
D32(EMAC_RXC_MULTI);
D32(EMAC_RXC_OCTET);
D32(EMAC_RXC_OK);
D32(EMAC_RXC_OPCODE);
D32(EMAC_RXC_PAUSE);
D32(EMAC_RXC_SHORT);
D32(EMAC_RXC_TYPED);
D32(EMAC_RXC_UNICST);
D32(EMAC_RX_IRQE);
D32(EMAC_RX_STAT);
D32(EMAC_RX_STKY);
D32(EMAC_STAADD);
D32(EMAC_STADAT);
D32(EMAC_SYSCTL);
D32(EMAC_SYSTAT);
D32(EMAC_TXC_1COL);
D32(EMAC_TXC_ABORT);
D32(EMAC_TXC_ALLFRM);
D32(EMAC_TXC_ALLOCT);
D32(EMAC_TXC_BROAD);
D32(EMAC_TXC_CRSERR);
D32(EMAC_TXC_DEFER);
D32(EMAC_TXC_DMAUND);
D32(EMAC_TXC_EQ64);
D32(EMAC_TXC_GE1024);
D32(EMAC_TXC_GT1COL);
D32(EMAC_TXC_LATECL);
D32(EMAC_TXC_LT1024);
D32(EMAC_TXC_LT128);
D32(EMAC_TXC_LT256);
D32(EMAC_TXC_LT512);
D32(EMAC_TXC_MACCTL);
D32(EMAC_TXC_MULTI);
D32(EMAC_TXC_OCTET);
D32(EMAC_TXC_OK);
D32(EMAC_TXC_UNICST);
D32(EMAC_TXC_XS_COL);
D32(EMAC_TXC_XS_DFR);
D32(EMAC_TX_IRQE);
D32(EMAC_TX_STAT);
D32(EMAC_TX_STKY);
D32(EMAC_VLAN1);
D32(EMAC_VLAN2);
D32(EMAC_WKUP_CTL);
D32(EMAC_WKUP_FFCMD);
D32(EMAC_WKUP_FFCRC0);
D32(EMAC_WKUP_FFCRC1);
D32(EMAC_WKUP_FFMSK0);
D32(EMAC_WKUP_FFMSK1);
D32(EMAC_WKUP_FFMSK2);
D32(EMAC_WKUP_FFMSK3);
D32(EMAC_WKUP_FFOFF);
# ifdef EMAC_PTP_ACCR
D32(EMAC_PTP_ACCR);
D32(EMAC_PTP_ADDEND);
D32(EMAC_PTP_ALARMHI);
D32(EMAC_PTP_ALARMLO);
D16(EMAC_PTP_CTL);
D32(EMAC_PTP_FOFF);
D32(EMAC_PTP_FV1);
D32(EMAC_PTP_FV2);
D32(EMAC_PTP_FV3);
D16(EMAC_PTP_ID_OFF);
D32(EMAC_PTP_ID_SNAP);
D16(EMAC_PTP_IE);
D16(EMAC_PTP_ISTAT);
D32(EMAC_PTP_OFFSET);
D32(EMAC_PTP_PPS_PERIOD);
D32(EMAC_PTP_PPS_STARTHI);
D32(EMAC_PTP_PPS_STARTLO);
D32(EMAC_PTP_RXSNAPHI);
D32(EMAC_PTP_RXSNAPLO);
D32(EMAC_PTP_TIMEHI);
D32(EMAC_PTP_TIMELO);
D32(EMAC_PTP_TXSNAPHI);
D32(EMAC_PTP_TXSNAPLO);
# endif
#endif
#if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
parent = debugfs_create_dir("eppi", top);
# ifdef EPPI0_STATUS
EPPI(0);
# endif
# ifdef EPPI1_STATUS
EPPI(1);
# endif
# ifdef EPPI2_STATUS
EPPI(2);
# endif
#endif
parent = debugfs_create_dir("gptimer", top);
#ifdef TIMER_ENABLE
GPTIMER_GROUP(TIMER_ENABLE, -1);
#endif
#ifdef TIMER_ENABLE0
GPTIMER_GROUP(TIMER_ENABLE0, 0);
#endif
#ifdef TIMER_ENABLE1
GPTIMER_GROUP(TIMER_ENABLE1, 1);
#endif
#ifdef TMRS4_DISABLE
GPTIMER_GROUP(TMRS4_ENABLE, 0);
GPTIMER_GROUP(TMRS8_ENABLE, 1);
#endif
GPTIMER(0);
GPTIMER(1);
GPTIMER(2);
#ifdef TIMER3_CONFIG
GPTIMER(3);
GPTIMER(4);
GPTIMER(5);
GPTIMER(6);
GPTIMER(7);
#endif
#ifdef TIMER8_CONFIG
GPTIMER(8);
GPTIMER(9);
GPTIMER(10);
#endif
#ifdef TIMER11_CONFIG
GPTIMER(11);
#endif
#ifdef HMDMA0_CONTROL
parent = debugfs_create_dir("hmdma", top);
HMDMA(0);
HMDMA(1);
#endif
#ifdef HOST_CONTROL
parent = debugfs_create_dir("hostdp", top);
D16(HOST_CONTROL);
D16(HOST_STATUS);
D16(HOST_TIMEOUT);
#endif
#ifdef IMDMA_S0_CONFIG
parent = debugfs_create_dir("imdma", top);
IMDMA(0);
IMDMA(1);
#endif
#ifdef KPAD_CTL
parent = debugfs_create_dir("keypad", top);
D16(KPAD_CTL);
D16(KPAD_PRESCALE);
D16(KPAD_MSEL);
D16(KPAD_ROWCOL);
D16(KPAD_STAT);
D16(KPAD_SOFTEVAL);
#endif
parent = debugfs_create_dir("mdma", top);
MDMA(0);
MDMA(1);
#ifdef MDMA_D2_CONFIG
MDMA(2);
MDMA(3);
#endif
#ifdef MXVR_CONFIG
parent = debugfs_create_dir("mxvr", top);
D16(MXVR_CONFIG);
# ifdef MXVR_PLL_CTL_0
D32(MXVR_PLL_CTL_0);
# endif
D32(MXVR_STATE_0);
D32(MXVR_STATE_1);
D32(MXVR_INT_STAT_0);
D32(MXVR_INT_STAT_1);
D32(MXVR_INT_EN_0);
D32(MXVR_INT_EN_1);
D16(MXVR_POSITION);
D16(MXVR_MAX_POSITION);
D16(MXVR_DELAY);
D16(MXVR_MAX_DELAY);
D32(MXVR_LADDR);
D16(MXVR_GADDR);
D32(MXVR_AADDR);
D32(MXVR_ALLOC_0);
D32(MXVR_ALLOC_1);
D32(MXVR_ALLOC_2);
D32(MXVR_ALLOC_3);
D32(MXVR_ALLOC_4);
D32(MXVR_ALLOC_5);
D32(MXVR_ALLOC_6);
D32(MXVR_ALLOC_7);
D32(MXVR_ALLOC_8);
D32(MXVR_ALLOC_9);
D32(MXVR_ALLOC_10);
D32(MXVR_ALLOC_11);
D32(MXVR_ALLOC_12);
D32(MXVR_ALLOC_13);
D32(MXVR_ALLOC_14);
D32(MXVR_SYNC_LCHAN_0);
D32(MXVR_SYNC_LCHAN_1);
D32(MXVR_SYNC_LCHAN_2);
D32(MXVR_SYNC_LCHAN_3);
D32(MXVR_SYNC_LCHAN_4);
D32(MXVR_SYNC_LCHAN_5);
D32(MXVR_SYNC_LCHAN_6);
D32(MXVR_SYNC_LCHAN_7);
D32(MXVR_DMA0_CONFIG);
D32(MXVR_DMA0_START_ADDR);
D16(MXVR_DMA0_COUNT);
D32(MXVR_DMA0_CURR_ADDR);
D16(MXVR_DMA0_CURR_COUNT);
D32(MXVR_DMA1_CONFIG);
D32(MXVR_DMA1_START_ADDR);
D16(MXVR_DMA1_COUNT);
D32(MXVR_DMA1_CURR_ADDR);
D16(MXVR_DMA1_CURR_COUNT);
D32(MXVR_DMA2_CONFIG);
D32(MXVR_DMA2_START_ADDR);
D16(MXVR_DMA2_COUNT);
D32(MXVR_DMA2_CURR_ADDR);
D16(MXVR_DMA2_CURR_COUNT);
D32(MXVR_DMA3_CONFIG);
D32(MXVR_DMA3_START_ADDR);
D16(MXVR_DMA3_COUNT);
D32(MXVR_DMA3_CURR_ADDR);
D16(MXVR_DMA3_CURR_COUNT);
D32(MXVR_DMA4_CONFIG);
D32(MXVR_DMA4_START_ADDR);
D16(MXVR_DMA4_COUNT);
D32(MXVR_DMA4_CURR_ADDR);
D16(MXVR_DMA4_CURR_COUNT);
D32(MXVR_DMA5_CONFIG);
D32(MXVR_DMA5_START_ADDR);
D16(MXVR_DMA5_COUNT);
D32(MXVR_DMA5_CURR_ADDR);
D16(MXVR_DMA5_CURR_COUNT);
D32(MXVR_DMA6_CONFIG);
D32(MXVR_DMA6_START_ADDR);
D16(MXVR_DMA6_COUNT);
D32(MXVR_DMA6_CURR_ADDR);
D16(MXVR_DMA6_CURR_COUNT);
D32(MXVR_DMA7_CONFIG);
D32(MXVR_DMA7_START_ADDR);
D16(MXVR_DMA7_COUNT);
D32(MXVR_DMA7_CURR_ADDR);
D16(MXVR_DMA7_CURR_COUNT);
D16(MXVR_AP_CTL);
D32(MXVR_APRB_START_ADDR);
D32(MXVR_APRB_CURR_ADDR);
D32(MXVR_APTB_START_ADDR);
D32(MXVR_APTB_CURR_ADDR);
D32(MXVR_CM_CTL);
D32(MXVR_CMRB_START_ADDR);
D32(MXVR_CMRB_CURR_ADDR);
D32(MXVR_CMTB_START_ADDR);
D32(MXVR_CMTB_CURR_ADDR);
D32(MXVR_RRDB_START_ADDR);
D32(MXVR_RRDB_CURR_ADDR);
D32(MXVR_PAT_DATA_0);
D32(MXVR_PAT_EN_0);
D32(MXVR_PAT_DATA_1);
D32(MXVR_PAT_EN_1);
D16(MXVR_FRAME_CNT_0);
D16(MXVR_FRAME_CNT_1);
D32(MXVR_ROUTING_0);
D32(MXVR_ROUTING_1);
D32(MXVR_ROUTING_2);
D32(MXVR_ROUTING_3);
D32(MXVR_ROUTING_4);
D32(MXVR_ROUTING_5);
D32(MXVR_ROUTING_6);
D32(MXVR_ROUTING_7);
D32(MXVR_ROUTING_8);
D32(MXVR_ROUTING_9);
D32(MXVR_ROUTING_10);
D32(MXVR_ROUTING_11);
D32(MXVR_ROUTING_12);
D32(MXVR_ROUTING_13);
D32(MXVR_ROUTING_14);
# ifdef MXVR_PLL_CTL_1
D32(MXVR_PLL_CTL_1);
# endif
D16(MXVR_BLOCK_CNT);
# ifdef MXVR_CLK_CTL
D32(MXVR_CLK_CTL);
# endif
# ifdef MXVR_CDRPLL_CTL
D32(MXVR_CDRPLL_CTL);
# endif
# ifdef MXVR_FMPLL_CTL
D32(MXVR_FMPLL_CTL);
# endif
# ifdef MXVR_PIN_CTL
D16(MXVR_PIN_CTL);
# endif
# ifdef MXVR_SCLK_CNT
D16(MXVR_SCLK_CNT);
# endif
#endif
#ifdef NFC_ADDR
parent = debugfs_create_dir("nfc", top);
D_WO(NFC_ADDR, 16);
D_WO(NFC_CMD, 16);
D_RO(NFC_COUNT, 16);
D16(NFC_CTL);
D_WO(NFC_DATA_RD, 16);
D_WO(NFC_DATA_WR, 16);
D_RO(NFC_ECC0, 16);
D_RO(NFC_ECC1, 16);
D_RO(NFC_ECC2, 16);
D_RO(NFC_ECC3, 16);
D16(NFC_IRQMASK);
D16(NFC_IRQSTAT);
D_WO(NFC_PGCTL, 16);
D_RO(NFC_READ, 16);
D16(NFC_RST);
D_RO(NFC_STAT, 16);
#endif
#ifdef OTP_CONTROL
parent = debugfs_create_dir("otp", top);
D16(OTP_CONTROL);
D16(OTP_BEN);
D16(OTP_STATUS);
D32(OTP_TIMING);
D32(OTP_DATA0);
D32(OTP_DATA1);
D32(OTP_DATA2);
D32(OTP_DATA3);
#endif
#ifdef PINT0_MASK_SET
parent = debugfs_create_dir("pint", top);
PINT(0);
PINT(1);
PINT(2);
PINT(3);
#endif
#ifdef PIXC_CTL
parent = debugfs_create_dir("pixc", top);
D16(PIXC_CTL);
D16(PIXC_PPL);
D16(PIXC_LPF);
D16(PIXC_AHSTART);
D16(PIXC_AHEND);
D16(PIXC_AVSTART);
D16(PIXC_AVEND);
D16(PIXC_ATRANSP);
D16(PIXC_BHSTART);
D16(PIXC_BHEND);
D16(PIXC_BVSTART);
D16(PIXC_BVEND);
D16(PIXC_BTRANSP);
D16(PIXC_INTRSTAT);
D32(PIXC_RYCON);
D32(PIXC_GUCON);
D32(PIXC_BVCON);
D32(PIXC_CCBIAS);
D32(PIXC_TC);
#endif
parent = debugfs_create_dir("pll", top);
D16(PLL_CTL);
D16(PLL_DIV);
D16(PLL_LOCKCNT);
D16(PLL_STAT);
D16(VR_CTL);
D32(CHIPID);
#if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
parent = debugfs_create_dir("ppi", top);
# ifdef PPI_CONTROL
bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
# endif
# ifdef PPI0_CONTROL
PPI(0);
# endif
# ifdef PPI1_CONTROL
PPI(1);
# endif
#endif
#ifdef PWM_CTRL
parent = debugfs_create_dir("pwm", top);
D16(PWM_CTRL);
D16(PWM_STAT);
D16(PWM_TM);
D16(PWM_DT);
D16(PWM_GATE);
D16(PWM_CHA);
D16(PWM_CHB);
D16(PWM_CHC);
D16(PWM_SEG);
D16(PWM_SYNCWT);
D16(PWM_CHAL);
D16(PWM_CHBL);
D16(PWM_CHCL);
D16(PWM_LSI);
D16(PWM_STAT2);
#endif
#ifdef RSI_CONFIG
parent = debugfs_create_dir("rsi", top);
D32(RSI_ARGUMENT);
D16(RSI_CEATA_CONTROL);
D16(RSI_CLK_CONTROL);
D16(RSI_COMMAND);
D16(RSI_CONFIG);
D16(RSI_DATA_CNT);
D16(RSI_DATA_CONTROL);
D16(RSI_DATA_LGTH);
D32(RSI_DATA_TIMER);
D16(RSI_EMASK);
D16(RSI_ESTAT);
D32(RSI_FIFO);
D16(RSI_FIFO_CNT);
D32(RSI_MASK0);
D32(RSI_MASK1);
D16(RSI_PID0);
D16(RSI_PID1);
D16(RSI_PID2);
D16(RSI_PID3);
D16(RSI_PID4);
D16(RSI_PID5);
D16(RSI_PID6);
D16(RSI_PID7);
D16(RSI_PWR_CONTROL);
D16(RSI_RD_WAIT_EN);
D32(RSI_RESPONSE0);
D32(RSI_RESPONSE1);
D32(RSI_RESPONSE2);
D32(RSI_RESPONSE3);
D16(RSI_RESP_CMD);
D32(RSI_STATUS);
D_WO(RSI_STATUSCL, 16);
#endif
#ifdef RTC_ALARM
parent = debugfs_create_dir("rtc", top);
D32(RTC_ALARM);
D16(RTC_ICTL);
D16(RTC_ISTAT);
D16(RTC_PREN);
D32(RTC_STAT);
D16(RTC_SWCNT);
#endif
#ifdef SDH_CFG
parent = debugfs_create_dir("sdh", top);
D32(SDH_ARGUMENT);
D16(SDH_CFG);
D16(SDH_CLK_CTL);
D16(SDH_COMMAND);
D_RO(SDH_DATA_CNT, 16);
D16(SDH_DATA_CTL);
D16(SDH_DATA_LGTH);
D32(SDH_DATA_TIMER);
D16(SDH_E_MASK);
D16(SDH_E_STATUS);
D32(SDH_FIFO);
D_RO(SDH_FIFO_CNT, 16);
D32(SDH_MASK0);
D32(SDH_MASK1);
D_RO(SDH_PID0, 16);
D_RO(SDH_PID1, 16);
D_RO(SDH_PID2, 16);
D_RO(SDH_PID3, 16);
D_RO(SDH_PID4, 16);
D_RO(SDH_PID5, 16);
D_RO(SDH_PID6, 16);
D_RO(SDH_PID7, 16);
D16(SDH_PWR_CTL);
D16(SDH_RD_WAIT_EN);
D_RO(SDH_RESPONSE0, 32);
D_RO(SDH_RESPONSE1, 32);
D_RO(SDH_RESPONSE2, 32);
D_RO(SDH_RESPONSE3, 32);
D_RO(SDH_RESP_CMD, 16);
D_RO(SDH_STATUS, 32);
D_WO(SDH_STATUS_CLR, 16);
#endif
#ifdef SECURE_CONTROL
parent = debugfs_create_dir("security", top);
D16(SECURE_CONTROL);
D16(SECURE_STATUS);
D32(SECURE_SYSSWT);
#endif
parent = debugfs_create_dir("sic", top);
D16(SWRST);
D16(SYSCR);
D16(SIC_RVECT);
D32(SIC_IAR0);
D32(SIC_IAR1);
D32(SIC_IAR2);
#ifdef SIC_IAR3
D32(SIC_IAR3);
#endif
#ifdef SIC_IAR4
D32(SIC_IAR4);
D32(SIC_IAR5);
D32(SIC_IAR6);
#endif
#ifdef SIC_IAR7
D32(SIC_IAR7);
#endif
#ifdef SIC_IAR8
D32(SIC_IAR8);
D32(SIC_IAR9);
D32(SIC_IAR10);
D32(SIC_IAR11);
#endif
#ifdef SIC_IMASK
D32(SIC_IMASK);
D32(SIC_ISR);
D32(SIC_IWR);
#endif
#ifdef SIC_IMASK0
D32(SIC_IMASK0);
D32(SIC_IMASK1);
D32(SIC_ISR0);
D32(SIC_ISR1);
D32(SIC_IWR0);
D32(SIC_IWR1);
#endif
#ifdef SIC_IMASK2
D32(SIC_IMASK2);
D32(SIC_ISR2);
D32(SIC_IWR2);
#endif
#ifdef SICB_RVECT
D16(SICB_SWRST);
D16(SICB_SYSCR);
D16(SICB_RVECT);
D32(SICB_IAR0);
D32(SICB_IAR1);
D32(SICB_IAR2);
D32(SICB_IAR3);
D32(SICB_IAR4);
D32(SICB_IAR5);
D32(SICB_IAR6);
D32(SICB_IAR7);
D32(SICB_IMASK0);
D32(SICB_IMASK1);
D32(SICB_ISR0);
D32(SICB_ISR1);
D32(SICB_IWR0);
D32(SICB_IWR1);
#endif
parent = debugfs_create_dir("spi", top);
#ifdef SPI0_REGBASE
SPI(0);
#endif
#ifdef SPI1_REGBASE
SPI(1);
#endif
#ifdef SPI2_REGBASE
SPI(2);
#endif
parent = debugfs_create_dir("sport", top);
#ifdef SPORT0_STAT
SPORT(0);
#endif
#ifdef SPORT1_STAT
SPORT(1);
#endif
#ifdef SPORT2_STAT
SPORT(2);
#endif
#ifdef SPORT3_STAT
SPORT(3);
#endif
#if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
parent = debugfs_create_dir("twi", top);
# ifdef TWI_CLKDIV
bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
# endif
# ifdef TWI0_CLKDIV
TWI(0);
# endif
# ifdef TWI1_CLKDIV
TWI(1);
# endif
#endif
parent = debugfs_create_dir("uart", top);
#ifdef BFIN_UART_DLL
bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
#endif
#ifdef UART0_DLL
UART(0);
#endif
#ifdef UART1_DLL
UART(1);
#endif
#ifdef UART2_DLL
UART(2);
#endif
#ifdef UART3_DLL
UART(3);
#endif
#ifdef USB_FADDR
parent = debugfs_create_dir("usb", top);
D16(USB_FADDR);
D16(USB_POWER);
D16(USB_INTRTX);
D16(USB_INTRRX);
D16(USB_INTRTXE);
D16(USB_INTRRXE);
D16(USB_INTRUSB);
D16(USB_INTRUSBE);
D16(USB_FRAME);
D16(USB_INDEX);
D16(USB_TESTMODE);
D16(USB_GLOBINTR);
D16(USB_GLOBAL_CTL);
D16(USB_TX_MAX_PACKET);
D16(USB_CSR0);
D16(USB_TXCSR);
D16(USB_RX_MAX_PACKET);
D16(USB_RXCSR);
D16(USB_COUNT0);
D16(USB_RXCOUNT);
D16(USB_TXTYPE);
D16(USB_NAKLIMIT0);
D16(USB_TXINTERVAL);
D16(USB_RXTYPE);
D16(USB_RXINTERVAL);
D16(USB_TXCOUNT);
D16(USB_EP0_FIFO);
D16(USB_EP1_FIFO);
D16(USB_EP2_FIFO);
D16(USB_EP3_FIFO);
D16(USB_EP4_FIFO);
D16(USB_EP5_FIFO);
D16(USB_EP6_FIFO);
D16(USB_EP7_FIFO);
D16(USB_OTG_DEV_CTL);
D16(USB_OTG_VBUS_IRQ);
D16(USB_OTG_VBUS_MASK);
D16(USB_LINKINFO);
D16(USB_VPLEN);
D16(USB_HS_EOF1);
D16(USB_FS_EOF1);
D16(USB_LS_EOF1);
D16(USB_APHY_CNTRL);
D16(USB_APHY_CALIB);
D16(USB_APHY_CNTRL2);
D16(USB_PHY_TEST);
D16(USB_PLLOSC_CTRL);
D16(USB_SRP_CLKDIV);
D16(USB_EP_NI0_TXMAXP);
D16(USB_EP_NI0_TXCSR);
D16(USB_EP_NI0_RXMAXP);
D16(USB_EP_NI0_RXCSR);
D16(USB_EP_NI0_RXCOUNT);
D16(USB_EP_NI0_TXTYPE);
D16(USB_EP_NI0_TXINTERVAL);
D16(USB_EP_NI0_RXTYPE);
D16(USB_EP_NI0_RXINTERVAL);
D16(USB_EP_NI0_TXCOUNT);
D16(USB_EP_NI1_TXMAXP);
D16(USB_EP_NI1_TXCSR);
D16(USB_EP_NI1_RXMAXP);
D16(USB_EP_NI1_RXCSR);
D16(USB_EP_NI1_RXCOUNT);
D16(USB_EP_NI1_TXTYPE);
D16(USB_EP_NI1_TXINTERVAL);
D16(USB_EP_NI1_RXTYPE);
D16(USB_EP_NI1_RXINTERVAL);
D16(USB_EP_NI1_TXCOUNT);
D16(USB_EP_NI2_TXMAXP);
D16(USB_EP_NI2_TXCSR);
D16(USB_EP_NI2_RXMAXP);
D16(USB_EP_NI2_RXCSR);
D16(USB_EP_NI2_RXCOUNT);
D16(USB_EP_NI2_TXTYPE);
D16(USB_EP_NI2_TXINTERVAL);
D16(USB_EP_NI2_RXTYPE);
D16(USB_EP_NI2_RXINTERVAL);
D16(USB_EP_NI2_TXCOUNT);
D16(USB_EP_NI3_TXMAXP);
D16(USB_EP_NI3_TXCSR);
D16(USB_EP_NI3_RXMAXP);
D16(USB_EP_NI3_RXCSR);
D16(USB_EP_NI3_RXCOUNT);
D16(USB_EP_NI3_TXTYPE);
D16(USB_EP_NI3_TXINTERVAL);
D16(USB_EP_NI3_RXTYPE);
D16(USB_EP_NI3_RXINTERVAL);
D16(USB_EP_NI3_TXCOUNT);
D16(USB_EP_NI4_TXMAXP);
D16(USB_EP_NI4_TXCSR);
D16(USB_EP_NI4_RXMAXP);
D16(USB_EP_NI4_RXCSR);
D16(USB_EP_NI4_RXCOUNT);
D16(USB_EP_NI4_TXTYPE);
D16(USB_EP_NI4_TXINTERVAL);
D16(USB_EP_NI4_RXTYPE);
D16(USB_EP_NI4_RXINTERVAL);
D16(USB_EP_NI4_TXCOUNT);
D16(USB_EP_NI5_TXMAXP);
D16(USB_EP_NI5_TXCSR);
D16(USB_EP_NI5_RXMAXP);
D16(USB_EP_NI5_RXCSR);
D16(USB_EP_NI5_RXCOUNT);
D16(USB_EP_NI5_TXTYPE);
D16(USB_EP_NI5_TXINTERVAL);
D16(USB_EP_NI5_RXTYPE);
D16(USB_EP_NI5_RXINTERVAL);
D16(USB_EP_NI5_TXCOUNT);
D16(USB_EP_NI6_TXMAXP);
D16(USB_EP_NI6_TXCSR);
D16(USB_EP_NI6_RXMAXP);
D16(USB_EP_NI6_RXCSR);
D16(USB_EP_NI6_RXCOUNT);
D16(USB_EP_NI6_TXTYPE);
D16(USB_EP_NI6_TXINTERVAL);
D16(USB_EP_NI6_RXTYPE);
D16(USB_EP_NI6_RXINTERVAL);
D16(USB_EP_NI6_TXCOUNT);
D16(USB_EP_NI7_TXMAXP);
D16(USB_EP_NI7_TXCSR);
D16(USB_EP_NI7_RXMAXP);
D16(USB_EP_NI7_RXCSR);
D16(USB_EP_NI7_RXCOUNT);
D16(USB_EP_NI7_TXTYPE);
D16(USB_EP_NI7_TXINTERVAL);
D16(USB_EP_NI7_RXTYPE);
D16(USB_EP_NI7_RXINTERVAL);
D16(USB_EP_NI7_TXCOUNT);
D16(USB_DMA_INTERRUPT);
D16(USB_DMA0CONTROL);
D16(USB_DMA0ADDRLOW);
D16(USB_DMA0ADDRHIGH);
D16(USB_DMA0COUNTLOW);
D16(USB_DMA0COUNTHIGH);
D16(USB_DMA1CONTROL);
D16(USB_DMA1ADDRLOW);
D16(USB_DMA1ADDRHIGH);
D16(USB_DMA1COUNTLOW);
D16(USB_DMA1COUNTHIGH);
D16(USB_DMA2CONTROL);
D16(USB_DMA2ADDRLOW);
D16(USB_DMA2ADDRHIGH);
D16(USB_DMA2COUNTLOW);
D16(USB_DMA2COUNTHIGH);
D16(USB_DMA3CONTROL);
D16(USB_DMA3ADDRLOW);
D16(USB_DMA3ADDRHIGH);
D16(USB_DMA3COUNTLOW);
D16(USB_DMA3COUNTHIGH);
D16(USB_DMA4CONTROL);
D16(USB_DMA4ADDRLOW);
D16(USB_DMA4ADDRHIGH);
D16(USB_DMA4COUNTLOW);
D16(USB_DMA4COUNTHIGH);
D16(USB_DMA5CONTROL);
D16(USB_DMA5ADDRLOW);
D16(USB_DMA5ADDRHIGH);
D16(USB_DMA5COUNTLOW);
D16(USB_DMA5COUNTHIGH);
D16(USB_DMA6CONTROL);
D16(USB_DMA6ADDRLOW);
D16(USB_DMA6ADDRHIGH);
D16(USB_DMA6COUNTLOW);
D16(USB_DMA6COUNTHIGH);
D16(USB_DMA7CONTROL);
D16(USB_DMA7ADDRLOW);
D16(USB_DMA7ADDRHIGH);
D16(USB_DMA7COUNTLOW);
D16(USB_DMA7COUNTHIGH);
#endif
#ifdef WDOG_CNT
parent = debugfs_create_dir("watchdog", top);
D32(WDOG_CNT);
D16(WDOG_CTL);
D32(WDOG_STAT);
#endif
#ifdef WDOGA_CNT
parent = debugfs_create_dir("watchdog", top);
D32(WDOGA_CNT);
D16(WDOGA_CTL);
D32(WDOGA_STAT);
D32(WDOGB_CNT);
D16(WDOGB_CTL);
D32(WDOGB_STAT);
#endif
#ifdef FIO_FLAG_D
#define PORTFIO FIO_FLAG_D
#endif
#ifdef FIO0_FLAG_D
#define PORTFIO FIO0_FLAG_D
#endif
#ifdef FIO1_FLAG_D
#define PORTGIO FIO1_FLAG_D
#endif
#ifdef FIO2_FLAG_D
#define PORTHIO FIO2_FLAG_D
#endif
parent = debugfs_create_dir("port", top);
#ifdef PORTFIO
PORT(PORTFIO, 'F');
#endif
#ifdef PORTGIO
PORT(PORTGIO, 'G');
#endif
#ifdef PORTHIO
PORT(PORTHIO, 'H');
#endif
#ifdef __ADSPBF51x__
D16(PORTF_FER);
D16(PORTF_DRIVE);
D16(PORTF_HYSTERESIS);
D16(PORTF_MUX);
D16(PORTG_FER);
D16(PORTG_DRIVE);
D16(PORTG_HYSTERESIS);
D16(PORTG_MUX);
D16(PORTH_FER);
D16(PORTH_DRIVE);
D16(PORTH_HYSTERESIS);
D16(PORTH_MUX);
D16(MISCPORT_DRIVE);
D16(MISCPORT_HYSTERESIS);
#endif
#ifdef __ADSPBF52x__
D16(PORTF_FER);
D16(PORTF_DRIVE);
D16(PORTF_HYSTERESIS);
D16(PORTF_MUX);
D16(PORTF_SLEW);
D16(PORTG_FER);
D16(PORTG_DRIVE);
D16(PORTG_HYSTERESIS);
D16(PORTG_MUX);
D16(PORTG_SLEW);
D16(PORTH_FER);
D16(PORTH_DRIVE);
D16(PORTH_HYSTERESIS);
D16(PORTH_MUX);
D16(PORTH_SLEW);
D16(MISCPORT_DRIVE);
D16(MISCPORT_HYSTERESIS);
D16(MISCPORT_SLEW);
#endif
#ifdef BF537_FAMILY
D16(PORTF_FER);
D16(PORTG_FER);
D16(PORTH_FER);
D16(PORT_MUX);
#endif
#ifdef BF538_FAMILY
D16(PORTCIO_FER);
D16(PORTCIO);
D16(PORTCIO_CLEAR);
D16(PORTCIO_SET);
D16(PORTCIO_TOGGLE);
D16(PORTCIO_DIR);
D16(PORTCIO_INEN);
D16(PORTDIO);
D16(PORTDIO_CLEAR);
D16(PORTDIO_DIR);
D16(PORTDIO_FER);
D16(PORTDIO_INEN);
D16(PORTDIO_SET);
D16(PORTDIO_TOGGLE);
D16(PORTEIO);
D16(PORTEIO_CLEAR);
D16(PORTEIO_DIR);
D16(PORTEIO_FER);
D16(PORTEIO_INEN);
D16(PORTEIO_SET);
D16(PORTEIO_TOGGLE);
#endif
#ifdef __ADSPBF54x__
{
int num;
unsigned long base;
base = PORTA_FER;
for (num = 0; num < 10; ++num) {
PORT(base, num);
base += sizeof(struct bfin_gpio_regs);
}
}
#endif
debug_mmrs_dentry = top;
return 0;
}
static int fan53555_regulator_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct fan53555_device_info *di;
struct fan53555_platform_data *pdata;
struct regulator_config config = { };
unsigned int val;
int ret;
if (client->dev.of_node)
pdata = fan53555_get_of_platform_data(client);
else
pdata = client->dev.platform_data;
if (!pdata || !pdata->regulator) {
dev_err(&client->dev, "Platform data not found!\n");
return -ENODEV;
}
di = devm_kzalloc(&client->dev, sizeof(struct fan53555_device_info),
GFP_KERNEL);
if (!di) {
dev_err(&client->dev, "Failed to allocate device info data!\n");
return -ENOMEM;
}
di->regmap = devm_regmap_init_i2c(client, &fan53555_regmap_config);
if (IS_ERR(di->regmap)) {
dev_err(&client->dev, "Failed to allocate regmap!\n");
return PTR_ERR(di->regmap);
}
di->dev = &client->dev;
di->regulator = pdata->regulator;
i2c_set_clientdata(client, di);
/* Get chip ID */
ret = fan53555_read(di, FAN53555_ID1, &val);
if (ret < 0) {
dev_err(&client->dev, "Failed to get chip ID!\n");
return -ENODEV;
}
di->chip_id = val & DIE_ID;
/* Get chip revision */
ret = fan53555_read(di, FAN53555_ID2, &val);
if (ret < 0) {
dev_err(&client->dev, "Failed to get chip Rev!\n");
return -ENODEV;
}
di->chip_rev = val & DIE_REV;
dev_info(&client->dev, "FAN53555 Option[%d] Rev[%d] Detected!\n",
di->chip_id, di->chip_rev);
/* Device init */
ret = fan53555_device_setup(di, pdata);
if (ret < 0) {
dev_err(&client->dev, "Failed to setup device!\n");
return ret;
}
/* Set up from device tree */
if (client->dev.of_node) {
ret = fan53555_of_init(client->dev.of_node, di);
if (ret)
return ret;
}
/* Register regulator */
config.dev = di->dev;
config.init_data = di->regulator;
config.regmap = di->regmap;
config.driver_data = di;
config.of_node = client->dev.of_node;
ret = fan53555_regulator_register(di, &config);
if (ret < 0)
dev_err(&client->dev, "Failed to register regulator!\n");
di->debug_root = debugfs_create_dir("fan53555", NULL);
if (!di->debug_root)
dev_err(&client->dev, "Couldn't create debug dir\n");
if (di->debug_root) {
struct dentry *ent;
ent = debugfs_create_x32("address", S_IFREG | S_IWUSR | S_IRUGO,
di->debug_root,
&(di->peek_poke_address));
if (!ent)
dev_err(&client->dev, "Couldn't create address debug file rc = %d\n",
ret);
ent = debugfs_create_file("data", S_IFREG | S_IWUSR | S_IRUGO,
di->debug_root, di,
&poke_poke_debug_ops);
if (!ent)
dev_err(&client->dev, "Couldn't create data debug file rc = %d\n",
ret);
}
return ret;
}
void mmc_add_card_debugfs(struct mmc_card *card)
{
struct mmc_host *host = card->host;
struct dentry *root;
if (!host->debugfs_root)
return;
root = debugfs_create_dir(mmc_card_id(card), host->debugfs_root);
if (IS_ERR(root))
/* Don't complain -- debugfs just isn't enabled */
return;
if (!root)
/* Complain -- debugfs is enabled, but it failed to
* create the directory. */
goto err;
card->debugfs_root = root;
if (!debugfs_create_x32("state", S_IRUSR, root, &card->state))
goto err;
if (mmc_card_mmc(card) || mmc_card_sd(card))
if (!debugfs_create_file("status", S_IRUSR, root, card,
&mmc_dbg_card_status_fops))
goto err;
if (mmc_card_mmc(card)) {
if (!debugfs_create_file("ext_csd", S_IRUSR, root, card,
&mmc_dbg_ext_csd_fops))
goto err;
if (!debugfs_create_file("eol_status", S_IRUSR, root, card,
&mmc_dbg_ext_csd_eol_fops))
goto err;
if (!debugfs_create_file("dhs_type_a", S_IRUSR, root, card,
&mmc_dbg_ext_csd_life_time_type_a_fops))
goto err;
if (!debugfs_create_file("dhs_type_b", S_IRUSR, root, card,
&mmc_dbg_ext_csd_life_time_type_b_fops))
goto err;
if (!debugfs_create_file("emmc_device_type", S_IRUSR, root,
card, &mmc_dbg_ext_csd_device_type_fops))
goto err;
if (!debugfs_create_file("firmware_version", S_IRUSR, root,
card, &mmc_dbg_ext_csd_fw_v_fops))
goto err;
if (!debugfs_create_file("bkops_status", S_IRUSR, root, card,
&mmc_dbg_ext_csd_bkops_status_fops))
goto err;
if (!debugfs_create_file("bkops_support", S_IRUSR, root, card,
&mmc_dbg_ext_csd_bkops_support_fops))
goto err;
if (!debugfs_create_file("poweron_notify", S_IRUSR, root, card,
&mmc_dbg_ext_csd_pon_notify_fops))
goto err;
if (!debugfs_create_file("hpi_support", S_IRUSR, root, card,
&mmc_dbg_ext_csd_hpi_support_fops))
goto err;
}
if (mmc_card_sd(card))
if (!debugfs_create_file("speed_class", S_IROTH, root, card,
&mmc_dbg_card_speed_class_fops))
goto err;
return;
err:
debugfs_remove_recursive(root);
card->debugfs_root = NULL;
dev_err(&card->dev, "failed to initialize debugfs\n");
}
