static unsigned
mn103int_io_write_buffer (struct hw *me,
const void *source,
int space,
unsigned_word base,
unsigned nr_bytes)
{
struct mn103int *controller = hw_data (me);
const unsigned8 *buf = source;
unsigned byte;
/* HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes)); */
for (byte = 0; byte < nr_bytes; byte++)
{
unsigned_word address = base + byte;
unsigned_word offset;
switch (decode_addr (me, controller, address, &offset))
{
case ICR_BLOCK:
write_icr (me, controller, offset, buf[byte]);
break;
case IAGR_BLOCK:
/* not allowed */
break;
case EXTMD_BLOCK:
write_extmd (me, controller, offset, buf[byte]);
break;
default:
hw_abort (me, "bad switch");
}
}
return nr_bytes;
}
uint8_t ax25_decode_header(FBUF* b, addr_t* from,
addr_t* to,
addr_t digis[],
uint8_t* ctrl,
uint8_t* pid)
{
register int8_t i=-1;
decode_addr(b, to);
if (!(decode_addr(b, from) & FLAG_LAST))
for (i=0; i<7; i++)
if ( decode_addr(b, &digis[i]) & FLAG_LAST)
break;
*ctrl = fbuf_getChar(b);
*pid = fbuf_getChar(b);
return (i==-1 ? 0 : i+1);
}
static unsigned
mn103int_io_read_buffer (struct hw *me,
void *dest,
int space,
unsigned_word base,
unsigned nr_bytes)
{
struct mn103int *controller = hw_data (me);
unsigned8 *buf = dest;
unsigned byte;
/* HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes)); */
for (byte = 0; byte < nr_bytes; byte++)
{
unsigned_word address = base + byte;
unsigned_word offset;
switch (decode_addr (me, controller, address, &offset))
{
case ICR_BLOCK:
buf[byte] = read_icr (me, controller, offset);
break;
case IAGR_BLOCK:
buf[byte] = read_iagr (me, controller, offset);
break;
case EXTMD_BLOCK:
buf[byte] = read_extmd (me, controller, offset);
break;
default:
hw_abort (me, "bad switch");
}
}
return nr_bytes;
}
static unsigned
mn103iop_io_write_buffer (struct hw *me,
const void *source,
int space,
unsigned_word base,
unsigned nr_bytes)
{
struct mn103iop *io_port = hw_data (me);
enum io_port_register_types io_port_reg;
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
io_port_reg = decode_addr (me, io_port, base);
switch (io_port_reg)
{
/* Port output registers */
case P0OUT:
case P1OUT:
case P2OUT:
case P3OUT:
write_output_reg(me, io_port, io_port_reg-P0OUT, source, nr_bytes);
break;
/* Port output mode registers */
case P0MD:
case P1MD:
case P2MD:
case P3MD:
write_output_mode_reg(me, io_port, io_port_reg-P0MD, source, nr_bytes);
break;
/* Port control registers */
case P0DIR:
case P1DIR:
case P2DIR:
case P3DIR:
write_control_reg(me, io_port, io_port_reg-P0DIR, source, nr_bytes);
break;
/* Port pin registers */
case P0IN:
case P1IN:
case P2IN:
hw_abort(me, "Cannot write to pin register.");
break;
case P2SS:
case P4SS:
write_dedicated_control_reg(me, io_port, io_port_reg, source, nr_bytes);
break;
default:
hw_abort(me, "invalid address");
}
return nr_bytes;
}
static unsigned
mn103tim_io_write_buffer (struct hw *me,
const void *source,
int space,
unsigned_word base,
unsigned nr_bytes)
{
struct mn103tim *timers = hw_data (me);
enum timer_register_types timer_reg;
HW_TRACE ((me, "write to 0x%08lx length %d with 0x%x", (long) base,
(int) nr_bytes, *(unsigned32 *)source));
timer_reg = decode_addr (me, timers, base);
/* It can be either a mode register, a base register, a binary counter, */
/* or a special timer 6 register. Check in that order. */
if ( timer_reg <= LAST_MODE_REG )
{
if ( timer_reg == 6 )
{
write_tm6md(me, timers, base, source, nr_bytes);
}
else
{
write_mode_reg(me, timers, timer_reg-FIRST_MODE_REG,
source, nr_bytes);
}
}
else if ( timer_reg <= LAST_BASE_REG )
{
write_base_reg(me, timers, timer_reg-FIRST_BASE_REG, source, nr_bytes);
}
else if ( timer_reg <= LAST_COUNTER )
{
hw_abort(me, "cannot write to counter");
}
else if ( timer_reg <= LAST_TIMER_REG )
{
write_special_timer6_reg(me, timers, timer_reg, source, nr_bytes);
}
else
{
hw_abort(me, "invalid reg type");
}
return nr_bytes;
}
static unsigned
mn103tim_io_read_buffer (struct hw *me,
void *dest,
int space,
unsigned_word base,
unsigned nr_bytes)
{
struct mn103tim *timers = hw_data (me);
enum timer_register_types timer_reg;
HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
timer_reg = decode_addr (me, timers, base);
/* It can be either a mode register, a base register, a binary counter, */
/* or a special timer 6 register. Check in that order. */
if ( timer_reg >= FIRST_MODE_REG && timer_reg <= LAST_MODE_REG )
{
read_mode_reg(me, timers, timer_reg-FIRST_MODE_REG, dest, nr_bytes);
}
else if ( timer_reg <= LAST_BASE_REG )
{
read_base_reg(me, timers, timer_reg-FIRST_BASE_REG, dest, nr_bytes);
}
else if ( timer_reg <= LAST_COUNTER )
{
read_counter(me, timers, timer_reg-FIRST_COUNTER, dest, nr_bytes);
}
else if ( timer_reg <= LAST_TIMER_REG )
{
read_special_timer6_reg(me, timers, timer_reg, dest, nr_bytes);
}
else
{
hw_abort(me, "invalid timer register address.");
}
return nr_bytes;
}
static unsigned
mn103ser_io_write_buffer (struct hw *me,
const void *source,
int space,
unsigned_word base,
unsigned nr_bytes)
{
struct mn103ser *serial = hw_data (me);
enum serial_register_types serial_reg;
HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
serial_reg = decode_addr (me, serial, base);
switch (serial_reg)
{
/* control registers */
case SC0CTR:
case SC1CTR:
case SC2CTR:
HW_TRACE ((me, "write - ctrl reg%d has 0x%x, nrbytes=%d.\n",
serial_reg-SC0CTR, *(unsigned8 *)source, nr_bytes));
write_control_reg(me, serial, serial_reg-SC0CTR, source, nr_bytes);
break;
/* interrupt mode registers */
case SC0ICR:
case SC1ICR:
case SC2ICR:
HW_TRACE ((me, "write - intmode reg%d has 0x%x, nrbytes=%d.\n",
serial_reg-SC0ICR, *(unsigned8 *)source, nr_bytes));
write_intmode_reg(me, serial, serial_reg-SC0ICR, source, nr_bytes);
break;
/* transmission buffers */
case SC0TXB:
case SC1TXB:
case SC2TXB:
HW_TRACE ((me, "write - txb%d has %c, nrbytes=%d.\n",
serial_reg-SC0TXB, *(char *)source, nr_bytes));
write_txb(me, serial, serial_reg-SC0TXB, source, nr_bytes);
break;
/* reception buffers */
case SC0RXB:
case SC1RXB:
case SC2RXB:
hw_abort(me, "Cannot write to reception buffer.");
break;
/* status registers */
case SC0STR:
case SC1STR:
case SC2STR:
hw_abort(me, "Cannot write to status register.");
break;
case SC2TIM:
HW_TRACE ((me, "read - serial2 timer reg %d (nrbytes=%d)\n",
*(unsigned8 *)source, nr_bytes));
write_serial2_timer_reg(me, serial, source, nr_bytes);
break;
default:
hw_abort(me, "invalid address");
}
return nr_bytes;
}
static unsigned
mn103ser_io_read_buffer (struct hw *me,
void *dest,
int space,
unsigned_word base,
unsigned nr_bytes)
{
struct mn103ser *serial = hw_data (me);
enum serial_register_types serial_reg;
HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
serial_reg = decode_addr (me, serial, base);
switch (serial_reg)
{
/* control registers */
case SC0CTR:
case SC1CTR:
case SC2CTR:
read_control_reg(me, serial, serial_reg-SC0CTR, dest, nr_bytes);
HW_TRACE ((me, "read - ctrl reg%d has 0x%x\n", serial_reg-SC0CTR,
*(unsigned8 *)dest));
break;
/* interrupt mode registers */
case SC0ICR:
case SC1ICR:
case SC2ICR:
read_intmode_reg(me, serial, serial_reg-SC0ICR, dest, nr_bytes);
HW_TRACE ((me, "read - intmode reg%d has 0x%x\n", serial_reg-SC0ICR,
*(unsigned8 *)dest));
break;
/* transmission buffers */
case SC0TXB:
case SC1TXB:
case SC2TXB:
read_txb(me, serial, serial_reg-SC0TXB, dest, nr_bytes);
HW_TRACE ((me, "read - txb%d has %c\n", serial_reg-SC0TXB,
*(char *)dest));
break;
/* reception buffers */
case SC0RXB:
case SC1RXB:
case SC2RXB:
read_rxb(me, serial, serial_reg-SC0RXB, dest, nr_bytes);
HW_TRACE ((me, "read - rxb%d has %c\n", serial_reg-SC0RXB,
*(char *)dest));
break;
/* status registers */
case SC0STR:
case SC1STR:
case SC2STR:
read_status_reg(me, serial, serial_reg-SC0STR, dest, nr_bytes);
HW_TRACE ((me, "read - status reg%d has 0x%x\n", serial_reg-SC0STR,
*(unsigned8 *)dest));
break;
case SC2TIM:
read_serial2_timer_reg(me, serial, dest, nr_bytes);
HW_TRACE ((me, "read - serial2 timer reg %d\n", *(unsigned8 *)dest));
break;
default:
hw_abort(me, "invalid address");
}
return nr_bytes;
}
int
socks_connect (char *host, char *port, struct addrinfo hints,
char *proxyhost, char *proxyport, struct addrinfo proxyhints)
{
int proxyfd;
unsigned char buf[SOCKS_MAXCMDSZ];
ssize_t cnt;
in_addr_t serveraddr;
in_port_t serverport;
if (proxyport)
proxyfd = remote_connect(proxyhost, proxyport, proxyhints);
else
proxyfd = remote_connect(proxyhost, SOCKS_PORT, proxyhints);
if (!proxyfd)
return -1;
serveraddr = decode_addr (host);
serverport = decode_port (port);
/* Version 5, one method: no authentication */
buf[0] = SOCKS_VERSION;
buf[1] = 1;
buf[2] = SOCKS_NOAUTH;
cnt = write (proxyfd, buf, 3);
if (cnt == -1)
err (1, "write failed");
if (cnt != 3)
errx (1, "short write, %d (expected 3)", cnt);
read (proxyfd, buf, 2);
if (buf[1] == SOCKS_NOMETHOD)
errx (1, "authentication method negotiation failed");
/* Version 5, connect: IPv4 address */
buf[0] = SOCKS_VERSION;
buf[1] = SOCKS_CONNECT;
buf[2] = 0;
buf[3] = SOCKS_IPV4;
memcpy (buf + 4, &serveraddr, sizeof serveraddr);
memcpy (buf + 8, &serverport, sizeof serverport);
/* XXX Handle short writes better */
cnt = write (proxyfd, buf, 10);
if (cnt == -1)
err (1, "write failed");
if (cnt != 10)
errx (1, "short write, %d (expected 10)", cnt);
/* XXX Handle short reads better */
cnt = read (proxyfd, buf, sizeof buf);
if (cnt == -1)
err (1, "read failed");
if (cnt != 10)
errx (1, "unexpected reply size %d (expected 10)", cnt);
if (buf[1] != 0)
errx (1, "connection failed, SOCKS error %d", buf[1]);
return proxyfd;
}
