void
sim_resume (SIM_DESC sd, int step, int sig_to_deliver)
{
  check_desc (sd);

  if (sig_to_deliver != 0)
    {
      fprintf (stderr,
	       "Warning: the rx minisim does not implement "
	       "signal delivery yet.\n" "Resuming with no signal.\n");
    }

  execution_error_clear_last_error ();

  if (step)
    handle_step (decode_opcode ());
  else
    {
      /* We don't clear 'stop' here, because then we would miss
         interrupts that arrived on the way here.  Instead, we clear
         the flag in sim_stop_reason, after GDB has disabled the
         interrupt signal handler.  */
      for (;;)
	{
	  if (stop)
	    {
	      stop = 0;
	      reason = sim_stopped;
	      siggnal = TARGET_SIGNAL_INT;
	      break;
	    }

	  int rc = decode_opcode ();

	  if (execution_error_get_last_error () != SIM_ERR_NONE)
	    {
	      reason = sim_stopped;
	      siggnal = TARGET_SIGNAL_SEGV;
	      break;
	    }

	  if (!RX_STEPPED (rc))
	    {
	      handle_step (rc);
	      break;
	    }
	}
    }
}
示例#2
0
/* =============================================================================
 * ud_decode() - Instruction decoder. Returns the number of bytes decoded.
 * =============================================================================
 */
unsigned int
ud_decode(struct ud *u)
{
  inp_start(u);
  clear_insn(u);
  u->le = &ud_lookup_table_list[0];
  u->error = decode_prefixes(u) == -1 || 
             decode_opcode(u)   == -1 ||
             u->error;
  /* Handle decode error. */
  if (u->error) {
    /* clear out the decode data. */
    clear_insn(u);
    /* mark the sequence of bytes as invalid. */
    u->itab_entry = & s_ie__invalid;
    u->mnemonic = u->itab_entry->mnemonic;
  } 

    /* maybe this stray segment override byte
     * should be spewed out?
     */
    if ( !P_SEG( u->itab_entry->prefix ) && 
            u->operand[0].type != UD_OP_MEM &&
            u->operand[1].type != UD_OP_MEM )
        u->pfx_seg = 0;

  u->insn_offset = u->pc; /* set offset of instruction */
  u->insn_fill = 0;   /* set translation buffer index to 0 */
  u->pc += u->inp_ctr;    /* move program counter by bytes decoded */
  gen_hex( u );       /* generate hex code */

  /* return number of bytes disassembled. */
  return u->inp_ctr;
}
示例#3
0
void emulate_cycle(chip8 * cpu) {

	update_timers(cpu);
	//fetch opcode
	cpu->opcode = cpu->memory[cpu->pc] << 8 | cpu->memory[cpu->pc + 1];
	
	decode_opcode(cpu);


}
offs_t mc68hc11_dasm_one(char *buffer, UINT32 pc)
{
	UINT8 opcode;

	output = buffer;
	mem_offset = pc;

	opcode = fetch();
	decode_opcode(pc, &opcode_table[opcode]);

	return mem_offset-pc;
}
示例#5
0
offs_t hc11_disasm(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram)
{
	UINT32 flags = 0;
	UINT8 opcode;

	output = buffer;
	rombase = oprom;

	opcode = fetch();
	flags = decode_opcode(pc, &opcode_table[opcode]);

	return (rombase-oprom) | flags | DASMFLAG_SUPPORTED;
}
示例#6
0
static void decode_instruction(unsigned short *address)
{
	unsigned int opcode;

	if (!get_instruction(&opcode, address))
		return;

	decode_opcode(opcode);

	if ((opcode & 0xc0000000) == 0xc0000000 &&
	    (opcode & BIT_MULTI_INS) &&
	    (opcode & 0xe8000000) != 0xe8000000) {
		pr_cont(" || ");
		if (!get_instruction(&opcode, address + 2))
			return;
		decode_opcode(opcode);
		pr_cont(" || ");
		if (!get_instruction(&opcode, address + 3))
			return;
		decode_opcode(opcode);
	}
}
示例#7
0
文件: usd.C 项目: dberc/tpzsimul.gems
//**************************************************************************
int main( int argc, char *argv[] ) {

  char *s, buf[200], buffer[200];
  long long instr;

  // needed for some translations
  //reg_box_t      rbox;
  //rbox.initializeMappings( );

  // initialize the state
  simstate_init();

  // initialize our module
  hfa_init_local();
  char *ruby_param[] = { "tester.exec",
                         "-p 1",
                         "-l 100000",
                         "-r 256",
  };

  // read the configuration
  attr_value_t val;
  val.kind     = Sim_Val_String;
  val.u.string = "";
  initvar_dispatch_set( (void *) "init", NULL, &val, NULL );

  // make a static instruction
  while (!feof(stdin)) {

    scanf("%s", buf);
    s = NULL;
    instr = strtoll( buf, &s, 0 );
    DEBUG_OUT( "0x%0llx = %lld\n", instr, instr );
    printIBits( instr );
    DEBUG_OUT("\n");
    static_inst_t *sinst = new static_inst_t(0x0ULL, instr);
    DEBUG_OUT("opcode = %s (0x%0x)\n\n",
              decode_opcode( (enum i_opcode) sinst->getOpcode()),
              sinst->getInst() );
    sinst->printDisassemble( buffer );
  }

  // close down our module
  hfa_fini_local();

  simstate_fini();
  exit(0);
}
示例#8
0
void
sim_resume (SIM_DESC sd, int step, int sig_to_deliver)
{
  int rc;

  check_desc (sd);

  if (sig_to_deliver != 0)
    {
      fprintf (stderr,
	       "Warning: the rl78 minisim does not implement "
	       "signal delivery yet.\n" "Resuming with no signal.\n");
    }

      /* We don't clear 'stop' here, because then we would miss
         interrupts that arrived on the way here.  Instead, we clear
         the flag in sim_stop_reason, after GDB has disabled the
         interrupt signal handler.  */
  for (;;)
    {
      if (stop)
	{
	  stop = 0;
	  reason = sim_stopped;
	  siggnal = GDB_SIGNAL_INT;
	  break;
	}

      if (hw_breakpoints[pc >> 3]
          && (hw_breakpoints[pc >> 3] & (1 << (pc & 0x7))))
	{
	  reason = sim_stopped;
	  siggnal = GDB_SIGNAL_TRAP;
	  break;
	}
      rc = setjmp (decode_jmp_buf);
      if (rc == 0)
	rc = decode_opcode ();

      if (!RL78_STEPPED (rc) || step)
	{
	  handle_step (rc);
	  break;
	}
    }
}
示例#9
0
static int
decode_opcode(struct ud *u)
{
  uint16_t ptr;
  UD_ASSERT(u->le->type == UD_TAB__OPC_TABLE);
  UD_RETURN_ON_ERROR(u);
  u->primary_opcode = inp_curr(u);
  ptr = u->le->table[inp_curr(u)];
  if (ptr & 0x8000) {
    u->le = &ud_lookup_table_list[ptr & ~0x8000];
    if (u->le->type == UD_TAB__OPC_TABLE) {
      inp_next(u);
      return decode_opcode(u);
    }
  }
  return decode_ext(u, ptr);
}
示例#10
0
static __inline int
decode_opcode(struct ud *u)
{
  uint16_t ptr;
  assert(u->le->type == UD_TAB__OPC_TABLE);
  inp_next(u); 
  if (u->error) {
    return -1;
  }
  ptr = u->le->table[inp_curr(u)];
  if (ptr & 0x8000) {
    u->le = &ud_lookup_table_list[ptr & ~0x8000];
    if (u->le->type == UD_TAB__OPC_TABLE) {
      return decode_opcode(u);
    }
  }
  return decode_ext(u, ptr);
}
示例#11
0
文件: main.c 项目: cooljeanius/macgdb
int
main (int argc, char **argv)
{
  int o;
  int save_trace;
  bfd *prog;
#ifdef HAVE_networking
  char *console_port_s = 0;
#endif

  setbuf (stdout, 0);

  in_gdb = 0;

  while ((o = getopt (argc, argv, "tc:vdm:C")) != -1)
    switch (o)
      {
      case 't':
	trace++;
	break;
      case 'c':
#ifdef HAVE_networking
	console_port_s = optarg;
#else
	fprintf (stderr, "Nework console not available in this build.\n");
#endif
	break;
      case 'C':
#ifdef HAVE_TERMIOS_H
	m32c_use_raw_console = 1;
#else
	fprintf (stderr, "Raw console not available in this build.\n");
#endif
	break;
      case 'v':
	verbose++;
	break;
      case 'd':
	m32c_disassemble++;
	break;
      case 'm':
	if (strcmp (optarg, "r8c") == 0 || strcmp (optarg, "m16c") == 0)
	  default_machine = bfd_mach_m16c;
	else if (strcmp (optarg, "m32cm") == 0
		 || strcmp (optarg, "m32c") == 0)
	  default_machine = bfd_mach_m32c;
	else
	  {
	    fprintf (stderr, "Invalid machine: %s\n", optarg);
	    exit (1);
	  }
	break;
      case '?':
	fprintf (stderr,
		 "usage: run [-v] [-C] [-c port] [-t] [-d] [-m r8c|m16c|m32cm|m32c]"
		 " program\n");
	exit (1);
      }

  prog = bfd_openr (argv[optind], 0);
  if (!prog)
    {
      fprintf (stderr, "Can't read %s\n", argv[optind]);
      exit (1);
    }

  if (!bfd_check_format (prog, bfd_object))
    {
      fprintf (stderr, "%s not a m32c program\n", argv[optind]);
      exit (1);
    }

  save_trace = trace;
  trace = 0;
  m32c_load (prog);
  trace = save_trace;

#ifdef HAVE_networking
  if (console_port_s)
    setup_tcp_console (console_port_s);
#endif

  sim_disasm_init (prog);

  while (1)
    {
      int rc;

      if (trace)
	printf ("\n");

      if (m32c_disassemble)
	sim_disasm_one ();

      enable_counting = verbose;
      cycles++;
      rc = decode_opcode ();
      enable_counting = 0;

      if (M32C_HIT_BREAK (rc))
	done (1);
      else if (M32C_EXITED (rc))
	done (M32C_EXIT_STATUS (rc));
      else
	assert (M32C_STEPPED (rc));

      trace_register_changes ();

#ifdef TIMER_A
      update_timer_a ();
#endif
    }
}
示例#12
0
static void decode_opcode(UINT32 pc, M68HC11_OPCODE *op_table)
{
	UINT8 imm8, mask;
	INT8 rel8;
	UINT16 imm16;
	UINT8 op2;

	switch(op_table->address_mode)
	{
		case EA_IMM8:
			imm8 = fetch();
			print("%s 0x%02X", op_table->mnemonic, imm8);
			break;

		case EA_IMM16:
			imm16 = fetch16();
			print("%s 0x%04X", op_table->mnemonic, imm16);
			break;

		case EA_DIRECT:
			imm8 = fetch();
			print("%s (0x%04X)", op_table->mnemonic, imm8);
			break;

		case EA_EXT:
			imm16 = fetch16();
			print("%s (0x%04X)", op_table->mnemonic, imm16);
			break;

		case EA_IND_X:
			imm8 = fetch();
			print("%s (X+0x%02X)", op_table->mnemonic, imm8);
			break;

		case EA_REL:
			rel8 = fetch();
			print("%s [0x%04X]", op_table->mnemonic, pc+2+rel8);
			break;

		case EA_DIRECT_IMM8:
			imm8 = fetch();
			mask = fetch();
			print("%s (0x%04X), 0x%02X", op_table->mnemonic, imm8, mask);
			break;

		case EA_IND_X_IMM8:
			imm8 = fetch();
			mask = fetch();
			print("%s (X+0x%02X), 0x%02X", op_table->mnemonic, imm8, mask);
			break;

		case EA_DIRECT_IMM8_REL:
			imm8 = fetch();
			mask = fetch();
			rel8 = fetch();
			print("%s (0x%04X), 0x%02X, [0x%04X]", op_table->mnemonic, imm8, mask, pc+2+rel8);
			break;

		case EA_IND_X_IMM8_REL:
			imm8 = fetch();
			mask = fetch();
			rel8 = fetch();
			print("%s (X+0x%02X), 0x%02X, [0x%04X]", op_table->mnemonic, imm8, mask, pc+2+rel8);
			break;

		case EA_IND_Y:
			imm8 = fetch();
			print("%s (Y+0x%02X)", op_table->mnemonic, imm8);
			break;

		case EA_IND_Y_IMM8:
			imm8 = fetch();
			mask = fetch();
			print("%s (Y+0x%02X), 0x%02X", op_table->mnemonic, imm8, mask);
			break;

		case EA_IND_Y_IMM8_REL:
			imm8 = fetch();
			mask = fetch();
			rel8 = fetch();
			print("%s (Y+0x%02X), 0x%02X, [0x%04X]", op_table->mnemonic, imm8, mask, pc+2+rel8);
			break;

		case PAGE2:
			op2 = fetch();
			decode_opcode(pc, &opcode_table_page2[op2]);
			break;

		case PAGE3:
			op2 = fetch();
			decode_opcode(pc, &opcode_table_page3[op2]);
			break;

		case PAGE4:
			op2 = fetch();
			decode_opcode(pc, &opcode_table_page4[op2]);
			break;

		default:
			print("%s", op_table->mnemonic);
	}
}
int
main (int argc, char **argv)
{
  int o;
  int save_trace;
  bfd *prog;

  while ((o = getopt (argc, argv, "tvdm:")) != -1)
    switch (o)
      {
      case 't':
	trace++;
	break;
      case 'v':
	verbose++;
	break;
      case 'd':
	disassemble++;
	break;
      case 'm':
	if (strcmp (optarg, "r8c") == 0 || strcmp (optarg, "m16c") == 0)
	  default_machine = bfd_mach_m16c;
	else if (strcmp (optarg, "m32cm") == 0
		 || strcmp (optarg, "m32c") == 0)
	  default_machine = bfd_mach_m32c;
	else
	  {
	    fprintf (stderr, "Invalid machine: %s\n", optarg);
	    exit (1);
	  }
	break;
      case '?':
	fprintf (stderr,
                 "usage: run [-v] [-t] [-d] [-m r8c|m16c|m32cm|m32c]"
                 " program\n");
	exit (1);
      }

  prog = bfd_openr (argv[optind], 0);
  if (!prog)
    {
      fprintf (stderr, "Can't read %s\n", argv[optind]);
      exit (1);
    }

  if (!bfd_check_format (prog, bfd_object))
    {
      fprintf (stderr, "%s not a m32c program\n", argv[optind]);
      exit (1);
    }

  save_trace = trace;
  trace = 0;
  m32c_load (prog);
  trace = save_trace;

  if (disassemble)
    sim_disasm_init (prog);

  while (1)
    {
      int rc;

      if (trace)
	printf ("\n");

      if (disassemble)
	sim_disasm_one ();

      enable_counting = verbose;
      cycles++;
      rc = decode_opcode ();
      enable_counting = 0;

      if (M32C_HIT_BREAK (rc))
	done (1);
      else if (M32C_EXITED (rc))
	done (M32C_EXIT_STATUS (rc));
      else
	assert (M32C_STEPPED (rc));

      trace_register_changes ();
    }
}
示例#14
0
static UINT32 decode_opcode(UINT32 pc, const M68HC11_OPCODE *op_table)
{
	UINT8 imm8, mask;
	INT8 rel8;
	UINT16 imm16;
	UINT8 op2;
	UINT32 flags = 0;

	if (!strcmp(op_table->mnemonic, "jsr") || !strcmp(op_table->mnemonic, "bsr"))
		flags = DASMFLAG_STEP_OVER;
	else if (!strcmp(op_table->mnemonic, "rts") || !strcmp(op_table->mnemonic, "rti"))
		flags = DASMFLAG_STEP_OUT;

	switch(op_table->address_mode)
	{
		case EA_IMM8:
			imm8 = fetch();
			print("%s 0x%02X", op_table->mnemonic, imm8);
			break;

		case EA_IMM16:
			imm16 = fetch16();
			print("%s 0x%04X", op_table->mnemonic, imm16);
			break;

		case EA_DIRECT:
			imm8 = fetch();
			print("%s (0x%04X)", op_table->mnemonic, imm8);
			break;

		case EA_EXT:
			imm16 = fetch16();
			print("%s (0x%04X)", op_table->mnemonic, imm16);
			break;

		case EA_IND_X:
			imm8 = fetch();
			print("%s (X+0x%02X)", op_table->mnemonic, imm8);
			break;

		case EA_REL:
			rel8 = fetch();
			print("%s [0x%04X]", op_table->mnemonic, pc+2+rel8);
			break;

		case EA_DIRECT_IMM8:
			imm8 = fetch();
			mask = fetch();
			print("%s (0x%04X), 0x%02X", op_table->mnemonic, imm8, mask);
			break;

		case EA_IND_X_IMM8:
			imm8 = fetch();
			mask = fetch();
			print("%s (X+0x%02X), 0x%02X", op_table->mnemonic, imm8, mask);
			break;

		case EA_DIRECT_IMM8_REL:
			imm8 = fetch();
			mask = fetch();
			rel8 = fetch();
			print("%s (0x%04X), 0x%02X, [0x%04X]", op_table->mnemonic, imm8, mask, pc+4+rel8);
			break;

		case EA_IND_X_IMM8_REL:
			imm8 = fetch();
			mask = fetch();
			rel8 = fetch();
			print("%s (X+0x%02X), 0x%02X, [0x%04X]", op_table->mnemonic, imm8, mask, pc+4+rel8);
			break;

		case EA_IND_Y:
			imm8 = fetch();
			print("%s (Y+0x%02X)", op_table->mnemonic, imm8);
			break;

		case EA_IND_Y_IMM8:
			imm8 = fetch();
			mask = fetch();
			print("%s (Y+0x%02X), 0x%02X", op_table->mnemonic, imm8, mask);
			break;

		case EA_IND_Y_IMM8_REL:
			imm8 = fetch();
			mask = fetch();
			rel8 = fetch();
			print("%s (Y+0x%02X), 0x%02X, [0x%04X]", op_table->mnemonic, imm8, mask, pc+2+rel8);
			break;

		case PAGE2:
			op2 = fetch();
			return decode_opcode(pc, &opcode_table_page2[op2]);

		case PAGE3:
			op2 = fetch();
			return decode_opcode(pc, &opcode_table_page3[op2]);

		case PAGE4:
			op2 = fetch();
			return decode_opcode(pc, &opcode_table_page4[op2]);

		default:
			print("%s", op_table->mnemonic);
	}
	return flags;
}
示例#15
0
文件: main.c 项目: ChrisG0x20/gdb
int
main (int argc, char **argv)
{
  int o;
  int save_trace;
  bfd *prog;
  int rc;

  /* By default, we exit when an execution error occurs.  */
  execution_error_init_standalone ();

  while ((o = getopt_long (argc, argv, "tvdeEwi", sim_options, NULL)) != -1)
    {
      if (o == 'E')
	/* Stop processing the command line. This is so that any remaining
	   words on the command line that look like arguments will be passed
	   on to the program being simulated.  */
	break;

      if (o >= OPT_ACT)
	{
	  int e, a;

	  o -= OPT_ACT;
	  e = o / SIM_ERRACTION_NUM_ACTIONS;
	  a = o % SIM_ERRACTION_NUM_ACTIONS;
	  execution_error_set_action (e, a);
	}
      else switch (o)
	{
	case 't':
	  trace++;
	  break;
	case 'v':
	  verbose++;
	  break;
	case 'd':
	  disassemble++;
	  break;
	case 'e':
	  execution_error_init_standalone ();
	  break;
	case 'w':
	  execution_error_warn_all ();
	  break;
	case 'i':
	  execution_error_ignore_all ();
	  break;
	case '?':
	  {
	    int i;
	    fprintf (stderr,
		     "usage: run [options] program [arguments]\n");
	    fprintf (stderr,
		     "\t-v\t- increase verbosity.\n"
		     "\t-t\t- trace.\n"
		     "\t-d\t- disassemble.\n"
		     "\t-E\t- stop processing sim args\n"
		     "\t-e\t- exit on all execution errors.\n"
		     "\t-w\t- warn (do not exit) on all execution errors.\n"
		     "\t-i\t- ignore all execution errors.\n");
	    for (i=0; sim_options[i].name; i++)
	      fprintf (stderr, "\t--%s\n", sim_options[i].name);
	    exit (1);
	  }
	}
    }

  prog = bfd_openr (argv[optind], 0);
  if (!prog)
    {
      fprintf (stderr, "Can't read %s\n", argv[optind]);
      exit (1);
    }

  if (!bfd_check_format (prog, bfd_object))
    {
      fprintf (stderr, "%s not a rx program\n", argv[optind]);
      exit (1);
    }

  init_regs ();

  rx_in_gdb = 0;
  save_trace = trace;
  trace = 0;
  rx_load (prog, NULL);
  trace = save_trace;

  sim_disasm_init (prog);

  enable_counting = verbose;

  rc = setjmp (decode_jmp_buf);

  if (rc == 0)
    {
      if (!trace && !disassemble)
	{
	  /* This will longjmp to the above if an exception
	     happens.  */
	  for (;;)
	    decode_opcode ();
	}
      else
	while (1)
	  {

	    if (trace)
	      printf ("\n");

	    if (disassemble)
	      {
		enable_counting = 0;
		sim_disasm_one ();
		enable_counting = verbose;
	      }

	    rc = decode_opcode ();

	    if (trace)
	      trace_register_changes ();
	  }
    }

  if (RX_HIT_BREAK (rc))
    done (1);
  else if (RX_EXITED (rc))
    done (RX_EXIT_STATUS (rc));
  else if (RX_STOPPED (rc))
    {
      if (verbose)
	printf("Stopped on signal %d\n", RX_STOP_SIG (rc));
      exit(1);
    }
  done (0);
  exit (0);
}
示例#16
0
int
main (int argc, char **argv)
{
  int o;
  int save_trace;
  bfd *prog;
  int rc;

  xmalloc_set_program_name (argv[0]);

  while ((o = getopt (argc, argv, "tvdr:D:")) != -1)
    {
      switch (o)
	{
	case 't':
	  trace ++;
	  break;
	case 'v':
	  verbose ++;
	  break;
	case 'd':
	  disassemble ++;
	  break;
	case 'r':
	  mem_ram_size (atoi (optarg));
	  break;
	case 'D':
	  dump_counts_filename = optarg;
	  break;
	case '?':
	  {
	    fprintf (stderr,
		     "usage: run [options] program [arguments]\n");
	    fprintf (stderr,
		     "\t-v\t\t- increase verbosity.\n"
		     "\t-t\t\t- trace.\n"
		     "\t-d\t\t- disassemble.\n"
		     "\t-r <bytes>\t- ram size.\n"
		     "\t-D <filename>\t- dump cycle count histogram\n");
	    exit (1);
	  }
	}
    }

  prog = bfd_openr (argv[optind], 0);
  if (!prog)
    {
      fprintf (stderr, "Can't read %s\n", argv[optind]);
      exit (1);
    }

  if (!bfd_check_format (prog, bfd_object))
    {
      fprintf (stderr, "%s not a rl78 program\n", argv[optind]);
      exit (1);
    }

  init_cpu ();

  rl78_in_gdb = 0;
  save_trace = trace;
  trace = 0;
  rl78_load (prog, 0, argv[0]);
  trace = save_trace;

  sim_disasm_init (prog);

  rc = setjmp (decode_jmp_buf);

  if (rc == 0)
    {
      if (!trace && !disassemble)
	{
	  /* This will longjmp to the above if an exception
	     happens.  */
	  for (;;)
	    decode_opcode ();
	}
      else
	while (1)
	  {

	    if (trace)
	      printf ("\n");

	    if (disassemble)
	      sim_disasm_one ();

	    rc = decode_opcode ();

	    if (trace)
	      trace_register_changes ();
	  }
    }

  if (RL78_HIT_BREAK (rc))
    done (1);
  else if (RL78_EXITED (rc))
    done (RL78_EXIT_STATUS (rc));
  else if (RL78_STOPPED (rc))
    {
      if (verbose)
	printf ("Stopped on signal %d\n", RL78_STOP_SIG (rc));
      exit (1);
    }
  done (0);
  exit (0);
}
示例#17
0
文件: decode.C 项目: gedare/GEMS
/// print out table
//***************************************************************************
void    decode_stat_t::print( out_intf_t *io )
{
  int64 total_seen = 0;
  int64 total_succ = 0;
  int64 total_functional = 0;
  int64 total_squash = 0;
  int64 total_noncompliant = 0;
  int64 total_l2miss = 0;
  int64 total_depl2miss = 0;
  int64 total_l2instrmiss = 0;
  char  buf[40], buf1[40], buf2[40], buf3[40], buf4[40], buf5[40], buf6[40], buf7[40], buf8[40], buf9[40], buf10[40], buf11[40], buf12[40], buf13[40];

  io->out_info("###: decode              seen        success function     fail  L2InstrMiss L2DataMiss  Dep_L2DataMiss\n");
  io->out_info( "Unmatched     %lld\n", m_num_unmatched);
  for (int i = 0; i < (int) i_maxcount; i++) {
    if ( m_op_seen[i] || m_op_succ[i] || m_op_functional[i]) {
      io->out_info(  "%03d: %-9.9s %14.14s %14.14s %8.8s %8.8s %8.8s %8.8s %8.8s\n",
               i, 
               decode_opcode((enum i_opcode) i), 
               commafmt( m_op_seen[i], buf, 40 ),
               commafmt( m_op_succ[i] - m_op_noncompliant[i], buf1, 40 ),
               commafmt( m_op_functional[i], buf2, 40 ),
               commafmt( (m_op_seen[i] - m_op_succ[i] + m_op_noncompliant[i]), buf3, 40) ,
               commafmt( m_op_l2instrmiss[i], buf12, 40 ),
               commafmt( m_op_l2miss[i], buf4, 40 ),
               commafmt( m_op_depl2miss[i], buf5, 40 )
              );
      total_seen += m_op_seen[i];
      total_succ += m_op_succ[i];
      total_functional += m_op_functional[i];
      total_noncompliant += m_op_noncompliant[i];
      total_l2miss += m_op_l2miss[i];
      total_depl2miss += m_op_depl2miss[i];
      total_l2instrmiss += m_op_l2instrmiss[i];
    }
  }

  io->out_info( "TOTALI    : %14.14s %14.14s %8.8s %8.8s %8.8s %8.8s %8.8s\n",
                  commafmt( total_seen, buf, 40 ),
                  commafmt( (total_succ - total_noncompliant), buf1, 40 ),
                  commafmt( total_functional, buf2, 40 ),
                  commafmt( (total_seen - total_succ + total_noncompliant),
                            buf3, 40 ), 
                commafmt( total_l2instrmiss, buf12, 40),
                commafmt( total_l2miss, buf4, 40 ),
                commafmt( total_depl2miss, buf5, 40 )
                );
  io->out_info( "NON_COMP  : %14.14s\n",
                  commafmt( total_noncompliant, buf, 40 ) );
  io->out_info( "Percent functional: %f\n",
                  100.0 * ((float) (total_functional) / (float) total_seen));
  io->out_info( "Percent correct      : %f\n",
                  100.0 * ((float) (total_succ - total_noncompliant) / (float) total_seen));
  
  io->out_info( "\n*** Latency and Squashes\n");
  io->out_info( "\n000: %-9.9s %10.10s %10.10s mem latency  min max avg exec\n", "opcode", "# squashed", "# non-comp", "min" );
  for (int i = 0; i < (int) i_maxcount; i++) {
    // 
    if ( m_op_seen[i] &&
         m_op_min_execute[i] != DECODE_DEFAULT_MIN_LATENCY ) {
      double average_mem_latency = 0.0;
      if (m_op_memory_counter[i] != 0) {
        average_mem_latency = (float) m_op_memory_latency[i] / (float) m_op_memory_counter[i];
      }
      double average_exec_latency = 0.0;
      if (m_op_seen[i] != 0) {
        average_exec_latency = ((float) m_op_total_execute[i]/(float)m_op_seen[i]);
      }
      io->out_info(  "%03d: %-9.9s %10.10s %10.10s %6lld %6.1f  %3lld %3lld %6.1f\n",
                       i, decode_opcode((enum i_opcode) i), 
                       commafmt( m_op_squash[i], buf, 40 ),
                       commafmt( m_op_noncompliant[i], buf1, 40 ),
                       m_op_memory_counter[i],
                       average_mem_latency,
                       
                       m_op_min_execute[i],
                       m_op_max_execute[i],
                       average_exec_latency );
      total_squash += m_op_squash[i];
    }
  }
  io->out_info( "SQUASHED  : %14.14s\n", 
                  commafmt( total_squash, buf, 40 ) );

  //***********print out detailed latency for each opcode
  io->out_info("\n***Detailed Latencies\n");
  io->out_info("\n   %-9.9s    %10.10s    %10.10s    %10.10s  %10.10s   %10.10s   %10.10s\n", "opcode", "F->D", "D->Rdy", "Rdy->E", "E->contE", "E->Comp", "Comp->R");
  for (int i = 0; i < (int) i_maxcount; i++) {
    if ( m_op_seen[i] &&
         m_op_min_execute[i] != DECODE_DEFAULT_MIN_LATENCY ) {
      double average_decode_latency = 0.0;
      if (m_op_seen[i] != 0) {
        average_decode_latency = ((float) m_op_total_decode[i]/(float)m_op_seen[i]);
      }
      double average_operandsready_latency = 0.0;
      if (m_op_seen[i] != 0) {
        average_operandsready_latency = ((float) m_op_total_operandsready[i]/(float)m_op_seen[i]);
      }
      double average_scheduler_latency = 0.0;
      if (m_op_seen[i] != 0) {
        average_scheduler_latency = ((float) m_op_total_scheduler[i]/(float)m_op_seen[i]);
      }
      double average_contexec_latency = 0.0;
      if (m_op_seen[i] != 0) {
        average_contexec_latency = ((float) m_op_total_contexecute[i]/(float)m_op_seen[i]);
      }
      double average_exec_latency = 0.0;
      if (m_op_seen[i] != 0) {
        average_exec_latency = ((float) m_op_total_execute[i]/(float)m_op_seen[i]);
      }
      double average_retire_latency = 0.0;
      if (m_op_seen[i] != 0) {
        average_retire_latency = ((float) m_op_total_retire[i]/(float)m_op_seen[i]);
      }
      io->out_info(  "%03d: %-9.9s [ %3lld %3lld %6.3f ]    [ %3lld %3lld %6.3f ]    [ %3lld %3lld %6.3f ]    [ %3lld %3lld %6.3f ]   [ %3lld %3lld %6.3f ]    [ %3lld %3lld %6.3f ]\n",
                     i, decode_opcode((enum i_opcode) i), 
                     m_op_min_decode[i],
                     m_op_max_decode[i],
                     average_decode_latency,
                     m_op_min_operandsready[i],
                     m_op_max_operandsready[i],
                     average_operandsready_latency,
                     m_op_min_scheduler[i],
                     m_op_max_scheduler[i],
                     average_scheduler_latency,
                     m_op_min_contexecute[i],
                     m_op_max_contexecute[i],
                     average_contexec_latency,
                     m_op_min_execute[i],
                     m_op_max_execute[i],
                     average_exec_latency,
                     m_op_min_retire[i],
                     m_op_max_retire[i],
                     average_retire_latency
                     );
    }
  }

  // print out Trap group stats 
  io->out_info("\nTrap Group Stats\n");
  io->out_info("======================\n");
  io->out_info("Trap  <<#LD  #ST  #AT  TotalMemop  TotalInstrs>>  <<#LDL2DataMiss  #STL2DataMiss #ATL2DataMiss  TotalL2DataMiss TotalL2InstrMiss>>\n");
  for(int i=0; i < TRAP_NUM_TRAP_TYPES; ++i){
    if(m_op_trap_seen[i] != 0 || m_op_trap_load[i] != 0 || m_op_trap_store[i] != 0 || m_op_trap_atomic[i] != 0){
      uint64 total_memop = m_op_trap_load[i] + m_op_trap_store[i] + m_op_trap_atomic[i];
      uint64 total_l2miss = m_op_trap_load_l2miss[i] + m_op_trap_store_l2miss[i] + m_op_trap_atomic_l2miss[i];
      io->out_info("%s  <<%lld  %lld  %lld %6lld %lld>>   <<%lld  %lld  %lld %6lld %lld>>\n", pstate_t::trap_num_menomic((trap_type_t) i), m_op_trap_load[i], m_op_trap_store[i], m_op_trap_atomic[i], total_memop, m_op_trap_seen[i], m_op_trap_load_l2miss[i], m_op_trap_store_l2miss[i], m_op_trap_atomic_l2miss[i], total_l2miss, m_op_trap_l2instrmiss[i]);
    }
  }
  
}