static int bcm53xxspi_bcma_probe(struct bcma_device *core) { struct bcm53xxspi *b53spi; struct spi_master *master; int err; if (core->bus->drv_cc.core->id.rev != 42) { pr_err("SPI on SoC with unsupported ChipCommon rev\n"); return -ENOTSUPP; } master = spi_alloc_master(&core->dev, sizeof(*b53spi)); if (!master) return -ENOMEM; b53spi = spi_master_get_devdata(master); b53spi->master = master; b53spi->core = core; master->transfer_one = bcm53xxspi_transfer_one; bcma_set_drvdata(core, b53spi); err = devm_spi_register_master(&core->dev, master); if (err) { spi_master_put(master); bcma_set_drvdata(core, NULL); goto out; } /* Broadcom SoCs (at least with the CC rev 42) use SPI for flash only */ spi_new_device(master, &bcm53xx_info); out: return err; }
static int pic32_spi_probe(struct platform_device *pdev) { struct spi_master *master; struct pic32_spi *pic32s; int ret; master = spi_alloc_master(&pdev->dev, sizeof(*pic32s)); if (!master) return -ENOMEM; pic32s = spi_master_get_devdata(master); pic32s->master = master; ret = pic32_spi_hw_probe(pdev, pic32s); if (ret) goto err_master; master->dev.of_node = pdev->dev.of_node; master->mode_bits = SPI_MODE_3 | SPI_MODE_0 | SPI_CS_HIGH; master->num_chipselect = 1; /* single chip-select */ master->max_speed_hz = clk_get_rate(pic32s->clk); master->setup = pic32_spi_setup; master->cleanup = pic32_spi_cleanup; master->flags = SPI_MASTER_MUST_TX | SPI_MASTER_MUST_RX; master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | SPI_BPW_MASK(32); master->transfer_one = pic32_spi_one_transfer; master->prepare_message = pic32_spi_prepare_message; master->unprepare_message = pic32_spi_unprepare_message; master->prepare_transfer_hardware = pic32_spi_prepare_hardware; master->unprepare_transfer_hardware = pic32_spi_unprepare_hardware; /* optional DMA support */ pic32_spi_dma_prep(pic32s, &pdev->dev); if (test_bit(PIC32F_DMA_PREP, &pic32s->flags)) master->can_dma = pic32_spi_can_dma; init_completion(&pic32s->xfer_done); pic32s->mode = -1; /* install irq handlers (with irq-disabled) */ irq_set_status_flags(pic32s->fault_irq, IRQ_NOAUTOEN); ret = devm_request_irq(&pdev->dev, pic32s->fault_irq, pic32_spi_fault_irq, IRQF_NO_THREAD, dev_name(&pdev->dev), pic32s); if (ret < 0) { dev_err(&pdev->dev, "request fault-irq %d\n", pic32s->rx_irq); goto err_bailout; } /* receive interrupt handler */ irq_set_status_flags(pic32s->rx_irq, IRQ_NOAUTOEN); ret = devm_request_irq(&pdev->dev, pic32s->rx_irq, pic32_spi_rx_irq, IRQF_NO_THREAD, dev_name(&pdev->dev), pic32s); if (ret < 0) { dev_err(&pdev->dev, "request rx-irq %d\n", pic32s->rx_irq); goto err_bailout; } /* transmit interrupt handler */ irq_set_status_flags(pic32s->tx_irq, IRQ_NOAUTOEN); ret = devm_request_irq(&pdev->dev, pic32s->tx_irq, pic32_spi_tx_irq, IRQF_NO_THREAD, dev_name(&pdev->dev), pic32s); if (ret < 0) { dev_err(&pdev->dev, "request tx-irq %d\n", pic32s->tx_irq); goto err_bailout; } /* register master */ ret = devm_spi_register_master(&pdev->dev, master); if (ret) { dev_err(&master->dev, "failed registering spi master\n"); goto err_bailout; } platform_set_drvdata(pdev, pic32s); return 0; err_bailout: clk_disable_unprepare(pic32s->clk); err_master: spi_master_put(master); return ret; }
static int spi_st_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct spi_master *master; struct resource *res; struct spi_st *spi_st; int irq, ret = 0; u32 var; master = spi_alloc_master(&pdev->dev, sizeof(*spi_st)); if (!master) return -ENOMEM; master->dev.of_node = np; master->mode_bits = MODEBITS; master->setup = spi_st_setup; master->cleanup = spi_st_cleanup; master->transfer_one = spi_st_transfer_one; master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); master->auto_runtime_pm = true; master->bus_num = pdev->id; spi_st = spi_master_get_devdata(master); spi_st->clk = devm_clk_get(&pdev->dev, "ssc"); if (IS_ERR(spi_st->clk)) { dev_err(&pdev->dev, "Unable to request clock\n"); ret = PTR_ERR(spi_st->clk); goto put_master; } ret = clk_prepare_enable(spi_st->clk); if (ret) goto put_master; init_completion(&spi_st->done); /* Get resources */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); spi_st->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(spi_st->base)) { ret = PTR_ERR(spi_st->base); goto clk_disable; } /* Disable I2C and Reset SSC */ writel_relaxed(0x0, spi_st->base + SSC_I2C); var = readw_relaxed(spi_st->base + SSC_CTL); var |= SSC_CTL_SR; writel_relaxed(var, spi_st->base + SSC_CTL); udelay(1); var = readl_relaxed(spi_st->base + SSC_CTL); var &= ~SSC_CTL_SR; writel_relaxed(var, spi_st->base + SSC_CTL); /* Set SSC into slave mode before reconfiguring PIO pins */ var = readl_relaxed(spi_st->base + SSC_CTL); var &= ~SSC_CTL_MS; writel_relaxed(var, spi_st->base + SSC_CTL); irq = irq_of_parse_and_map(np, 0); if (!irq) { dev_err(&pdev->dev, "IRQ missing or invalid\n"); ret = -EINVAL; goto clk_disable; } ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0, pdev->name, spi_st); if (ret) { dev_err(&pdev->dev, "Failed to request irq %d\n", irq); goto clk_disable; } /* by default the device is on */ pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); platform_set_drvdata(pdev, master); ret = devm_spi_register_master(&pdev->dev, master); if (ret) { dev_err(&pdev->dev, "Failed to register master\n"); goto clk_disable; } return 0; clk_disable: clk_disable_unprepare(spi_st->clk); put_master: spi_master_put(master); return ret; }
static int rockchip_spi_probe(struct platform_device *pdev) { int ret = 0; struct rockchip_spi *rs; struct spi_master *master; struct resource *mem; master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi)); if (!master) return -ENOMEM; platform_set_drvdata(pdev, master); rs = spi_master_get_devdata(master); memset(rs, 0, sizeof(struct rockchip_spi)); /* Get basic io resource and map it */ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); rs->regs = devm_ioremap_resource(&pdev->dev, mem); if (IS_ERR(rs->regs)) { ret = PTR_ERR(rs->regs); goto err_ioremap_resource; } rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); if (IS_ERR(rs->apb_pclk)) { dev_err(&pdev->dev, "Failed to get apb_pclk\n"); ret = PTR_ERR(rs->apb_pclk); goto err_ioremap_resource; } rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); if (IS_ERR(rs->spiclk)) { dev_err(&pdev->dev, "Failed to get spi_pclk\n"); ret = PTR_ERR(rs->spiclk); goto err_ioremap_resource; } ret = clk_prepare_enable(rs->apb_pclk); if (ret) { dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); goto err_ioremap_resource; } ret = clk_prepare_enable(rs->spiclk); if (ret) { dev_err(&pdev->dev, "Failed to enable spi_clk\n"); goto err_spiclk_enable; } spi_enable_chip(rs, 0); rs->type = SSI_MOTO_SPI; rs->master = master; rs->dev = &pdev->dev; rs->max_freq = clk_get_rate(rs->spiclk); rs->fifo_len = get_fifo_len(rs); if (!rs->fifo_len) { dev_err(&pdev->dev, "Failed to get fifo length\n"); ret = -EINVAL; goto err_get_fifo_len; } spin_lock_init(&rs->lock); pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); master->auto_runtime_pm = true; master->bus_num = pdev->id; master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; master->num_chipselect = 2; master->dev.of_node = pdev->dev.of_node; master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8); master->set_cs = rockchip_spi_set_cs; master->prepare_message = rockchip_spi_prepare_message; master->unprepare_message = rockchip_spi_unprepare_message; master->transfer_one = rockchip_spi_transfer_one; rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx"); if (!rs->dma_tx.ch) dev_warn(rs->dev, "Failed to request TX DMA channel\n"); rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx"); if (!rs->dma_rx.ch) { if (rs->dma_tx.ch) { dma_release_channel(rs->dma_tx.ch); rs->dma_tx.ch = NULL; } dev_warn(rs->dev, "Failed to request RX DMA channel\n"); } if (rs->dma_tx.ch && rs->dma_rx.ch) { rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR); rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR); rs->dma_tx.direction = DMA_MEM_TO_DEV; rs->dma_rx.direction = DMA_DEV_TO_MEM; master->can_dma = rockchip_spi_can_dma; master->dma_tx = rs->dma_tx.ch; master->dma_rx = rs->dma_rx.ch; } ret = devm_spi_register_master(&pdev->dev, master); if (ret) { dev_err(&pdev->dev, "Failed to register master\n"); goto err_register_master; } return 0; err_register_master: if (rs->dma_tx.ch) dma_release_channel(rs->dma_tx.ch); if (rs->dma_rx.ch) dma_release_channel(rs->dma_rx.ch); err_get_fifo_len: clk_disable_unprepare(rs->spiclk); err_spiclk_enable: clk_disable_unprepare(rs->apb_pclk); err_ioremap_resource: spi_master_put(master); return ret; }
static int img_spfi_probe(struct platform_device *pdev) { struct spi_master *master; struct img_spfi *spfi; struct resource *res; int ret; u32 max_speed_hz; master = spi_alloc_master(&pdev->dev, sizeof(*spfi)); if (!master) return -ENOMEM; platform_set_drvdata(pdev, master); spfi = spi_master_get_devdata(master); spfi->dev = &pdev->dev; spfi->master = master; spin_lock_init(&spfi->lock); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); spfi->regs = devm_ioremap_resource(spfi->dev, res); if (IS_ERR(spfi->regs)) { ret = PTR_ERR(spfi->regs); goto put_spi; } spfi->phys = res->start; spfi->irq = platform_get_irq(pdev, 0); if (spfi->irq < 0) { ret = spfi->irq; goto put_spi; } ret = devm_request_irq(spfi->dev, spfi->irq, img_spfi_irq, IRQ_TYPE_LEVEL_HIGH, dev_name(spfi->dev), spfi); if (ret) goto put_spi; spfi->sys_clk = devm_clk_get(spfi->dev, "sys"); if (IS_ERR(spfi->sys_clk)) { ret = PTR_ERR(spfi->sys_clk); goto put_spi; } spfi->spfi_clk = devm_clk_get(spfi->dev, "spfi"); if (IS_ERR(spfi->spfi_clk)) { ret = PTR_ERR(spfi->spfi_clk); goto put_spi; } ret = clk_prepare_enable(spfi->sys_clk); if (ret) goto put_spi; ret = clk_prepare_enable(spfi->spfi_clk); if (ret) goto disable_pclk; spfi_reset(spfi); /* * Only enable the error (IACCESS) interrupt. In PIO mode we'll * poll the status of the FIFOs. */ spfi_writel(spfi, SPFI_INTERRUPT_IACCESS, SPFI_INTERRUPT_ENABLE); master->auto_runtime_pm = true; master->bus_num = pdev->id; master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_TX_DUAL | SPI_RX_DUAL; if (of_property_read_bool(spfi->dev->of_node, "img,supports-quad-mode")) master->mode_bits |= SPI_TX_QUAD | SPI_RX_QUAD; master->dev.of_node = pdev->dev.of_node; master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(8); master->max_speed_hz = clk_get_rate(spfi->spfi_clk) / 4; master->min_speed_hz = clk_get_rate(spfi->spfi_clk) / 512; /* * Maximum speed supported by spfi is limited to the lower value * between 1/4 of the SPFI clock or to "spfi-max-frequency" * defined in the device tree. * If no value is defined in the device tree assume the maximum * speed supported to be 1/4 of the SPFI clock. */ if (!of_property_read_u32(spfi->dev->of_node, "spfi-max-frequency", &max_speed_hz)) { if (master->max_speed_hz > max_speed_hz) master->max_speed_hz = max_speed_hz; } master->setup = img_spfi_setup; master->cleanup = img_spfi_cleanup; master->transfer_one = img_spfi_transfer_one; master->prepare_message = img_spfi_prepare; master->unprepare_message = img_spfi_unprepare; master->handle_err = img_spfi_handle_err; spfi->tx_ch = dma_request_slave_channel(spfi->dev, "tx"); spfi->rx_ch = dma_request_slave_channel(spfi->dev, "rx"); if (!spfi->tx_ch || !spfi->rx_ch) { if (spfi->tx_ch) dma_release_channel(spfi->tx_ch); if (spfi->rx_ch) dma_release_channel(spfi->rx_ch); dev_warn(spfi->dev, "Failed to get DMA channels, falling back to PIO mode\n"); } else { master->dma_tx = spfi->tx_ch; master->dma_rx = spfi->rx_ch; master->can_dma = img_spfi_can_dma; } pm_runtime_set_active(spfi->dev); pm_runtime_enable(spfi->dev); ret = devm_spi_register_master(spfi->dev, master); if (ret) goto disable_pm; return 0; disable_pm: pm_runtime_disable(spfi->dev); if (spfi->rx_ch) dma_release_channel(spfi->rx_ch); if (spfi->tx_ch) dma_release_channel(spfi->tx_ch); clk_disable_unprepare(spfi->spfi_clk); disable_pclk: clk_disable_unprepare(spfi->sys_clk); put_spi: spi_master_put(master); return ret; }
static int xlp_spi_probe(struct platform_device *pdev) { struct spi_master *master; struct xlp_spi_priv *xspi; struct resource *res; struct clk *clk; int irq, err; xspi = devm_kzalloc(&pdev->dev, sizeof(*xspi), GFP_KERNEL); if (!xspi) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); xspi->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(xspi->base)) return PTR_ERR(xspi->base); irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "no IRQ resource found\n"); return -EINVAL; } err = devm_request_irq(&pdev->dev, irq, xlp_spi_interrupt, 0, pdev->name, xspi); if (err) { dev_err(&pdev->dev, "unable to request irq %d\n", irq); return err; } clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(clk)) { dev_err(&pdev->dev, "could not get spi clock\n"); return PTR_ERR(clk); } xspi->spi_clk = clk_get_rate(clk); master = spi_alloc_master(&pdev->dev, 0); if (!master) { dev_err(&pdev->dev, "could not alloc master\n"); return -ENOMEM; } master->bus_num = 0; master->num_chipselect = XLP_SPI_MAX_CS; master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; master->setup = xlp_spi_setup; master->transfer_one = xlp_spi_transfer_one; master->dev.of_node = pdev->dev.of_node; init_completion(&xspi->done); spi_master_set_devdata(master, xspi); xlp_spi_sysctl_setup(xspi); /* register spi controller */ err = devm_spi_register_master(&pdev->dev, master); if (err) { dev_err(&pdev->dev, "spi register master failed!\n"); spi_master_put(master); return err; } return 0; }
static int spi_qup_probe(struct platform_device *pdev) { struct spi_master *master; struct clk *iclk, *cclk; struct spi_qup *controller; struct resource *res; struct device *dev; void __iomem *base; u32 max_freq, iomode, num_cs; int ret, irq, size; dev = &pdev->dev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); base = devm_ioremap_resource(dev, res); if (IS_ERR(base)) return PTR_ERR(base); irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; cclk = devm_clk_get(dev, "core"); if (IS_ERR(cclk)) return PTR_ERR(cclk); iclk = devm_clk_get(dev, "iface"); if (IS_ERR(iclk)) return PTR_ERR(iclk); /* This is optional parameter */ if (of_property_read_u32(dev->of_node, "spi-max-frequency", &max_freq)) max_freq = SPI_MAX_RATE; if (!max_freq || max_freq > SPI_MAX_RATE) { dev_err(dev, "invalid clock frequency %d\n", max_freq); return -ENXIO; } ret = clk_prepare_enable(cclk); if (ret) { dev_err(dev, "cannot enable core clock\n"); return ret; } ret = clk_prepare_enable(iclk); if (ret) { clk_disable_unprepare(cclk); dev_err(dev, "cannot enable iface clock\n"); return ret; } master = spi_alloc_master(dev, sizeof(struct spi_qup)); if (!master) { clk_disable_unprepare(cclk); clk_disable_unprepare(iclk); dev_err(dev, "cannot allocate master\n"); return -ENOMEM; } /* use num-cs unless not present or out of range */ if (of_property_read_u32(dev->of_node, "num-cs", &num_cs) || num_cs > SPI_NUM_CHIPSELECTS) master->num_chipselect = SPI_NUM_CHIPSELECTS; else master->num_chipselect = num_cs; master->bus_num = pdev->id; master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); master->max_speed_hz = max_freq; master->transfer_one = spi_qup_transfer_one; master->dev.of_node = pdev->dev.of_node; master->auto_runtime_pm = true; master->dma_alignment = dma_get_cache_alignment(); master->max_dma_len = SPI_MAX_DMA_XFER; platform_set_drvdata(pdev, master); controller = spi_master_get_devdata(master); controller->dev = dev; controller->base = base; controller->iclk = iclk; controller->cclk = cclk; controller->irq = irq; ret = spi_qup_init_dma(master, res->start); if (ret == -EPROBE_DEFER) goto error; else if (!ret) master->can_dma = spi_qup_can_dma; /* set v1 flag if device is version 1 */ if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1")) controller->qup_v1 = 1; spin_lock_init(&controller->lock); init_completion(&controller->done); iomode = readl_relaxed(base + QUP_IO_M_MODES); size = QUP_IO_M_OUTPUT_BLOCK_SIZE(iomode); if (size) controller->out_blk_sz = size * 16; else controller->out_blk_sz = 4; size = QUP_IO_M_INPUT_BLOCK_SIZE(iomode); if (size) controller->in_blk_sz = size * 16; else controller->in_blk_sz = 4; size = QUP_IO_M_OUTPUT_FIFO_SIZE(iomode); controller->out_fifo_sz = controller->out_blk_sz * (2 << size); size = QUP_IO_M_INPUT_FIFO_SIZE(iomode); controller->in_fifo_sz = controller->in_blk_sz * (2 << size); dev_info(dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", controller->in_blk_sz, controller->in_fifo_sz, controller->out_blk_sz, controller->out_fifo_sz); writel_relaxed(1, base + QUP_SW_RESET); ret = spi_qup_set_state(controller, QUP_STATE_RESET); if (ret) { dev_err(dev, "cannot set RESET state\n"); goto error_dma; } writel_relaxed(0, base + QUP_OPERATIONAL); writel_relaxed(0, base + QUP_IO_M_MODES); if (!controller->qup_v1) writel_relaxed(0, base + QUP_OPERATIONAL_MASK); writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN, base + SPI_ERROR_FLAGS_EN); /* if earlier version of the QUP, disable INPUT_OVERRUN */ if (controller->qup_v1) writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN | QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN, base + QUP_ERROR_FLAGS_EN); writel_relaxed(0, base + SPI_CONFIG); writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL); ret = devm_request_irq(dev, irq, spi_qup_qup_irq, IRQF_TRIGGER_HIGH, pdev->name, controller); if (ret) goto error_dma; pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC); pm_runtime_use_autosuspend(dev); pm_runtime_set_active(dev); pm_runtime_enable(dev); ret = devm_spi_register_master(dev, master); if (ret) goto disable_pm; return 0; disable_pm: pm_runtime_disable(&pdev->dev); error_dma: spi_qup_release_dma(master); error: clk_disable_unprepare(cclk); clk_disable_unprepare(iclk); spi_master_put(master); return ret; }
static int bcm2835aux_spi_probe(struct platform_device *pdev) { struct spi_master *master; struct bcm2835aux_spi *bs; struct resource *res; unsigned long clk_hz; int err; master = spi_alloc_master(&pdev->dev, sizeof(*bs)); if (!master) return -ENOMEM; platform_set_drvdata(pdev, master); master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS); master->bits_per_word_mask = SPI_BPW_MASK(8); /* even though the driver never officially supported native CS * allow a single native CS for legacy DT support purposes when * no cs-gpio is configured. * Known limitations for native cs are: * * multiple chip-selects: cs0-cs2 are all simultaniously asserted * whenever there is a transfer - this even includes SPI_NO_CS * * SPI_CS_HIGH: is ignores - cs are always asserted low * * cs_change: cs is deasserted after each spi_transfer * * cs_delay_usec: cs is always deasserted one SCK cycle after * a spi_transfer */ master->num_chipselect = 1; master->setup = bcm2835aux_spi_setup; master->transfer_one = bcm2835aux_spi_transfer_one; master->handle_err = bcm2835aux_spi_handle_err; master->prepare_message = bcm2835aux_spi_prepare_message; master->unprepare_message = bcm2835aux_spi_unprepare_message; master->dev.of_node = pdev->dev.of_node; bs = spi_master_get_devdata(master); /* the main area */ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); bs->regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(bs->regs)) { err = PTR_ERR(bs->regs); goto out_master_put; } bs->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(bs->clk)) { err = PTR_ERR(bs->clk); dev_err(&pdev->dev, "could not get clk: %d\n", err); goto out_master_put; } bs->irq = platform_get_irq(pdev, 0); if (bs->irq <= 0) { dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq); err = bs->irq ? bs->irq : -ENODEV; goto out_master_put; } /* this also enables the HW block */ err = clk_prepare_enable(bs->clk); if (err) { dev_err(&pdev->dev, "could not prepare clock: %d\n", err); goto out_master_put; } /* just checking if the clock returns a sane value */ clk_hz = clk_get_rate(bs->clk); if (!clk_hz) { dev_err(&pdev->dev, "clock returns 0 Hz\n"); err = -ENODEV; goto out_clk_disable; } /* reset SPI-HW block */ bcm2835aux_spi_reset_hw(bs); err = devm_request_irq(&pdev->dev, bs->irq, bcm2835aux_spi_interrupt, IRQF_SHARED, dev_name(&pdev->dev), master); if (err) { dev_err(&pdev->dev, "could not request IRQ: %d\n", err); goto out_clk_disable; } err = devm_spi_register_master(&pdev->dev, master); if (err) { dev_err(&pdev->dev, "could not register SPI master: %d\n", err); goto out_clk_disable; } bcm2835aux_debugfs_create(bs, dev_name(&pdev->dev)); return 0; out_clk_disable: clk_disable_unprepare(bs->clk); out_master_put: spi_master_put(master); return err; }
static int stm32_qspi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct spi_controller *ctrl; struct reset_control *rstc; struct stm32_qspi *qspi; struct resource *res; int ret, irq; ctrl = spi_alloc_master(dev, sizeof(*qspi)); if (!ctrl) return -ENOMEM; qspi = spi_controller_get_devdata(ctrl); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi"); qspi->io_base = devm_ioremap_resource(dev, res); if (IS_ERR(qspi->io_base)) return PTR_ERR(qspi->io_base); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm"); qspi->mm_base = devm_ioremap_resource(dev, res); if (IS_ERR(qspi->mm_base)) return PTR_ERR(qspi->mm_base); qspi->mm_size = resource_size(res); if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) return -EINVAL; irq = platform_get_irq(pdev, 0); ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0, dev_name(dev), qspi); if (ret) { dev_err(dev, "failed to request irq\n"); return ret; } init_completion(&qspi->data_completion); qspi->clk = devm_clk_get(dev, NULL); if (IS_ERR(qspi->clk)) return PTR_ERR(qspi->clk); qspi->clk_rate = clk_get_rate(qspi->clk); if (!qspi->clk_rate) return -EINVAL; ret = clk_prepare_enable(qspi->clk); if (ret) { dev_err(dev, "can not enable the clock\n"); return ret; } rstc = devm_reset_control_get_exclusive(dev, NULL); if (!IS_ERR(rstc)) { reset_control_assert(rstc); udelay(2); reset_control_deassert(rstc); } qspi->dev = dev; platform_set_drvdata(pdev, qspi); mutex_init(&qspi->lock); ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; ctrl->setup = stm32_qspi_setup; ctrl->bus_num = -1; ctrl->mem_ops = &stm32_qspi_mem_ops; ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP; ctrl->dev.of_node = dev->of_node; ret = devm_spi_register_master(dev, ctrl); if (ret) goto err_spi_register; return 0; err_spi_register: stm32_qspi_release(qspi); return ret; }
static int sun6i_spi_probe(struct platform_device *pdev) { struct spi_master *master; struct sun6i_spi *sspi; struct resource *res; int ret = 0, irq; master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); if (!master) { dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); return -ENOMEM; } platform_set_drvdata(pdev, master); sspi = spi_master_get_devdata(master); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); sspi->base_addr = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(sspi->base_addr)) { ret = PTR_ERR(sspi->base_addr); goto err_free_master; } irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "No spi IRQ specified\n"); ret = -ENXIO; goto err_free_master; } ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, 0, "sun6i-spi", sspi); if (ret) { dev_err(&pdev->dev, "Cannot request IRQ\n"); goto err_free_master; } sspi->master = master; sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); master->max_speed_hz = 100 * 1000 * 1000; master->min_speed_hz = 3 * 1000; master->set_cs = sun6i_spi_set_cs; master->transfer_one = sun6i_spi_transfer_one; master->num_chipselect = 4; master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; master->bits_per_word_mask = SPI_BPW_MASK(8); master->dev.of_node = pdev->dev.of_node; master->auto_runtime_pm = true; master->max_transfer_size = sun6i_spi_max_transfer_size; sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); if (IS_ERR(sspi->hclk)) { dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); ret = PTR_ERR(sspi->hclk); goto err_free_master; } sspi->mclk = devm_clk_get(&pdev->dev, "mod"); if (IS_ERR(sspi->mclk)) { dev_err(&pdev->dev, "Unable to acquire module clock\n"); ret = PTR_ERR(sspi->mclk); goto err_free_master; } init_completion(&sspi->done); sspi->rstc = devm_reset_control_get(&pdev->dev, NULL); if (IS_ERR(sspi->rstc)) { dev_err(&pdev->dev, "Couldn't get reset controller\n"); ret = PTR_ERR(sspi->rstc); goto err_free_master; } /* * This wake-up/shutdown pattern is to be able to have the * device woken up, even if runtime_pm is disabled */ ret = sun6i_spi_runtime_resume(&pdev->dev); if (ret) { dev_err(&pdev->dev, "Couldn't resume the device\n"); goto err_free_master; } pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); pm_runtime_idle(&pdev->dev); ret = devm_spi_register_master(&pdev->dev, master); if (ret) { dev_err(&pdev->dev, "cannot register SPI master\n"); goto err_pm_disable; } return 0; err_pm_disable: pm_runtime_disable(&pdev->dev); sun6i_spi_runtime_suspend(&pdev->dev); err_free_master: spi_master_put(master); return ret; }
static int spi_clps711x_probe(struct platform_device *pdev) { struct spi_clps711x_data *hw; struct spi_clps711x_pdata *pdata = dev_get_platdata(&pdev->dev); struct spi_master *master; struct resource *res; int i, irq, ret; if (!pdata) { dev_err(&pdev->dev, "No platform data supplied\n"); return -EINVAL; } if (pdata->num_chipselect < 1) { dev_err(&pdev->dev, "At least one CS must be defined\n"); return -EINVAL; } irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; master = spi_alloc_master(&pdev->dev, sizeof(*hw)); if (!master) return -ENOMEM; master->cs_gpios = devm_kzalloc(&pdev->dev, sizeof(int) * pdata->num_chipselect, GFP_KERNEL); if (!master->cs_gpios) { ret = -ENOMEM; goto err_out; } master->bus_num = pdev->id; master->mode_bits = SPI_CPHA | SPI_CS_HIGH; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8); master->num_chipselect = pdata->num_chipselect; master->setup = spi_clps711x_setup; master->prepare_message = spi_clps711x_prepare_message; master->transfer_one = spi_clps711x_transfer_one; hw = spi_master_get_devdata(master); for (i = 0; i < master->num_chipselect; i++) { master->cs_gpios[i] = pdata->chipselect[i]; ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i], DRIVER_NAME); if (ret) { dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i); goto err_out; } } hw->spi_clk = devm_clk_get(&pdev->dev, "spi"); if (IS_ERR(hw->spi_clk)) { dev_err(&pdev->dev, "Can't get clocks\n"); ret = PTR_ERR(hw->spi_clk); goto err_out; } master->max_speed_hz = clk_get_rate(hw->spi_clk); platform_set_drvdata(pdev, master); hw->syscon = syscon_regmap_lookup_by_pdevname("syscon.3"); if (IS_ERR(hw->syscon)) { ret = PTR_ERR(hw->syscon); goto err_out; } hw->syscon1 = syscon_regmap_lookup_by_pdevname("syscon.1"); if (IS_ERR(hw->syscon1)) { ret = PTR_ERR(hw->syscon1); goto err_out; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); hw->syncio = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(hw->syncio)) { ret = PTR_ERR(hw->syncio); goto err_out; } /* Disable extended mode due hardware problems */ regmap_update_bits(hw->syscon, SYSCON_OFFSET, SYSCON3_ADCCON, 0); /* Clear possible pending interrupt */ readl(hw->syncio); ret = devm_request_irq(&pdev->dev, irq, spi_clps711x_isr, 0, dev_name(&pdev->dev), master); if (ret) goto err_out; ret = devm_spi_register_master(&pdev->dev, master); if (!ret) { dev_info(&pdev->dev, "SPI bus driver initialized. Master clock %u Hz\n", master->max_speed_hz); return 0; } dev_err(&pdev->dev, "Failed to register master\n"); err_out: spi_master_put(master); return ret; }
int bcm_qspi_probe(struct platform_device *pdev, struct bcm_qspi_soc_intc *soc_intc) { struct device *dev = &pdev->dev; struct bcm_qspi *qspi; struct spi_master *master; struct resource *res; int irq, ret = 0, num_ints = 0; u32 val; const char *name = NULL; int num_irqs = ARRAY_SIZE(qspi_irq_tab); /* We only support device-tree instantiation */ if (!dev->of_node) return -ENODEV; if (!of_match_node(bcm_qspi_of_match, dev->of_node)) return -ENODEV; master = spi_alloc_master(dev, sizeof(struct bcm_qspi)); if (!master) { dev_err(dev, "error allocating spi_master\n"); return -ENOMEM; } qspi = spi_master_get_devdata(master); qspi->pdev = pdev; qspi->trans_pos.trans = NULL; qspi->trans_pos.byte = 0; qspi->trans_pos.mspi_last_trans = true; qspi->master = master; master->bus_num = -1; master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD; master->setup = bcm_qspi_setup; master->transfer_one = bcm_qspi_transfer_one; master->spi_flash_read = bcm_qspi_flash_read; master->cleanup = bcm_qspi_cleanup; master->dev.of_node = dev->of_node; master->num_chipselect = NUM_CHIPSELECT; qspi->big_endian = of_device_is_big_endian(dev->of_node); if (!of_property_read_u32(dev->of_node, "num-cs", &val)) master->num_chipselect = val; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi"); if (!res) res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mspi"); if (res) { qspi->base[MSPI] = devm_ioremap_resource(dev, res); if (IS_ERR(qspi->base[MSPI])) { ret = PTR_ERR(qspi->base[MSPI]); goto qspi_resource_err; } } else { goto qspi_resource_err; } res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bspi"); if (res) { qspi->base[BSPI] = devm_ioremap_resource(dev, res); if (IS_ERR(qspi->base[BSPI])) { ret = PTR_ERR(qspi->base[BSPI]); goto qspi_resource_err; } qspi->bspi_mode = true; } else { qspi->bspi_mode = false; } dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : ""); res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg"); if (res) { qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res); if (IS_ERR(qspi->base[CHIP_SELECT])) { ret = PTR_ERR(qspi->base[CHIP_SELECT]); goto qspi_resource_err; } } qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id), GFP_KERNEL); if (!qspi->dev_ids) { ret = -ENOMEM; goto qspi_resource_err; } for (val = 0; val < num_irqs; val++) { irq = -1; name = qspi_irq_tab[val].irq_name; if (qspi_irq_tab[val].irq_source == SINGLE_L2) { /* get the l2 interrupts */ irq = platform_get_irq_byname(pdev, name); } else if (!num_ints && soc_intc) { /* all mspi, bspi intrs muxed to one L1 intr */ irq = platform_get_irq(pdev, 0); } if (irq >= 0) { ret = devm_request_irq(&pdev->dev, irq, qspi_irq_tab[val].irq_handler, 0, name, &qspi->dev_ids[val]); if (ret < 0) { dev_err(&pdev->dev, "IRQ %s not found\n", name); goto qspi_probe_err; } qspi->dev_ids[val].dev = qspi; qspi->dev_ids[val].irqp = &qspi_irq_tab[val]; num_ints++; dev_dbg(&pdev->dev, "registered IRQ %s %d\n", qspi_irq_tab[val].irq_name, irq); } } if (!num_ints) { dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n"); ret = -EINVAL; goto qspi_probe_err; } /* * Some SoCs integrate spi controller (e.g., its interrupt bits) * in specific ways */ if (soc_intc) { qspi->soc_intc = soc_intc; soc_intc->bcm_qspi_int_set(soc_intc, MSPI_DONE, true); } else { qspi->soc_intc = NULL; } qspi->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(qspi->clk)) { dev_warn(dev, "unable to get clock\n"); ret = PTR_ERR(qspi->clk); goto qspi_probe_err; } ret = clk_prepare_enable(qspi->clk); if (ret) { dev_err(dev, "failed to prepare clock\n"); goto qspi_probe_err; } qspi->base_clk = clk_get_rate(qspi->clk); qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2); bcm_qspi_hw_init(qspi); init_completion(&qspi->mspi_done); init_completion(&qspi->bspi_done); qspi->curr_cs = -1; platform_set_drvdata(pdev, qspi); qspi->xfer_mode.width = -1; qspi->xfer_mode.addrlen = -1; qspi->xfer_mode.hp = -1; ret = devm_spi_register_master(&pdev->dev, master); if (ret < 0) { dev_err(dev, "can't register master\n"); goto qspi_reg_err; } return 0; qspi_reg_err: bcm_qspi_hw_uninit(qspi); clk_disable_unprepare(qspi->clk); qspi_probe_err: kfree(qspi->dev_ids); qspi_resource_err: spi_master_put(master); return ret; }
static int sifive_spi_probe(struct platform_device *pdev) { struct sifive_spi *spi; struct resource *res; int ret, irq, num_cs; u32 cs_bits, max_bits_per_word; struct spi_master *master; master = spi_alloc_master(&pdev->dev, sizeof(struct sifive_spi)); if (!master) { dev_err(&pdev->dev, "out of memory\n"); return -ENOMEM; } spi = spi_master_get_devdata(master); init_completion(&spi->done); platform_set_drvdata(pdev, master); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); spi->regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(spi->regs)) { ret = PTR_ERR(spi->regs); goto put_master; } spi->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(spi->clk)) { dev_err(&pdev->dev, "Unable to find bus clock\n"); ret = PTR_ERR(spi->clk); goto put_master; } irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "Unable to find interrupt\n"); ret = irq; goto put_master; } /* Optional parameters */ ret = of_property_read_u32(pdev->dev.of_node, "sifive,fifo-depth", &spi->fifo_depth); if (ret < 0) spi->fifo_depth = SIFIVE_SPI_DEFAULT_DEPTH; ret = of_property_read_u32(pdev->dev.of_node, "sifive,max-bits-per-word", &max_bits_per_word); if (!ret && max_bits_per_word < 8) { dev_err(&pdev->dev, "Only 8bit SPI words supported by the driver\n"); ret = -EINVAL; goto put_master; } /* Spin up the bus clock before hitting registers */ ret = clk_prepare_enable(spi->clk); if (ret) { dev_err(&pdev->dev, "Unable to enable bus clock\n"); goto put_master; } /* probe the number of CS lines */ spi->cs_inactive = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF); sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU); cs_bits = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF); sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive); if (!cs_bits) { dev_err(&pdev->dev, "Could not auto probe CS lines\n"); ret = -EINVAL; goto put_master; } num_cs = ilog2(cs_bits) + 1; if (num_cs > SIFIVE_SPI_MAX_CS) { dev_err(&pdev->dev, "Invalid number of spi slaves\n"); ret = -EINVAL; goto put_master; } /* Define our master */ master->dev.of_node = pdev->dev.of_node; master->bus_num = pdev->id; master->num_chipselect = num_cs; master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD; /* TODO: add driver support for bits_per_word < 8 * we need to "left-align" the bits (unless SPI_LSB_FIRST) */ master->bits_per_word_mask = SPI_BPW_MASK(8); master->flags = SPI_CONTROLLER_MUST_TX | SPI_MASTER_GPIO_SS; master->prepare_message = sifive_spi_prepare_message; master->set_cs = sifive_spi_set_cs; master->transfer_one = sifive_spi_transfer_one; pdev->dev.dma_mask = NULL; /* Configure the SPI master hardware */ sifive_spi_init(spi); /* Register for SPI Interrupt */ ret = devm_request_irq(&pdev->dev, irq, sifive_spi_irq, 0, dev_name(&pdev->dev), spi); if (ret) { dev_err(&pdev->dev, "Unable to bind to interrupt\n"); goto put_master; } dev_info(&pdev->dev, "mapped; irq=%d, cs=%d\n", irq, master->num_chipselect); ret = devm_spi_register_master(&pdev->dev, master); if (ret < 0) { dev_err(&pdev->dev, "spi_register_master failed\n"); goto put_master; } return 0; put_master: spi_master_put(master); return ret; }
static int bcm2835_spi_probe(struct platform_device *pdev) { struct spi_master *master; struct bcm2835_spi *bs; struct resource *res; int err; master = spi_alloc_master(&pdev->dev, sizeof(*bs)); if (!master) { dev_err(&pdev->dev, "spi_alloc_master() failed\n"); return -ENOMEM; } platform_set_drvdata(pdev, master); master->mode_bits = BCM2835_SPI_MODE_BITS; master->bits_per_word_mask = SPI_BPW_MASK(8); master->num_chipselect = 3; master->setup = bcm2835_spi_setup; master->transfer_one = bcm2835_spi_transfer_one; master->handle_err = bcm2835_spi_handle_err; master->prepare_message = bcm2835_spi_prepare_message; master->dev.of_node = pdev->dev.of_node; bs = spi_master_get_devdata(master); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); bs->regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(bs->regs)) { err = PTR_ERR(bs->regs); goto out_master_put; } bs->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(bs->clk)) { err = PTR_ERR(bs->clk); dev_err(&pdev->dev, "could not get clk: %d\n", err); goto out_master_put; } bs->irq = platform_get_irq(pdev, 0); if (bs->irq <= 0) { dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq); err = bs->irq ? bs->irq : -ENODEV; goto out_master_put; } clk_prepare_enable(bs->clk); bcm2835_dma_init(master, &pdev->dev); /* initialise the hardware with the default polarities */ bcm2835_wr(bs, BCM2835_SPI_CS, BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX); err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0, dev_name(&pdev->dev), master); if (err) { dev_err(&pdev->dev, "could not request IRQ: %d\n", err); goto out_clk_disable; } err = devm_spi_register_master(&pdev->dev, master); if (err) { dev_err(&pdev->dev, "could not register SPI master: %d\n", err); goto out_clk_disable; } return 0; out_clk_disable: clk_disable_unprepare(bs->clk); out_master_put: spi_master_put(master); return err; }
static int spi_clps711x_probe(struct platform_device *pdev) { struct spi_clps711x_data *hw; struct spi_master *master; struct resource *res; int irq, ret; irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; master = spi_alloc_master(&pdev->dev, sizeof(*hw)); if (!master) return -ENOMEM; master->bus_num = -1; master->mode_bits = SPI_CPHA | SPI_CS_HIGH; master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8); master->dev.of_node = pdev->dev.of_node; master->setup = spi_clps711x_setup; master->prepare_message = spi_clps711x_prepare_message; master->transfer_one = spi_clps711x_transfer_one; hw = spi_master_get_devdata(master); hw->spi_clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(hw->spi_clk)) { ret = PTR_ERR(hw->spi_clk); goto err_out; } hw->syscon = syscon_regmap_lookup_by_compatible("cirrus,ep7209-syscon3"); if (IS_ERR(hw->syscon)) { ret = PTR_ERR(hw->syscon); goto err_out; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); hw->syncio = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(hw->syncio)) { ret = PTR_ERR(hw->syncio); goto err_out; } /* Disable extended mode due hardware problems */ regmap_update_bits(hw->syscon, SYSCON_OFFSET, SYSCON3_ADCCON, 0); /* Clear possible pending interrupt */ readl(hw->syncio); ret = devm_request_irq(&pdev->dev, irq, spi_clps711x_isr, 0, dev_name(&pdev->dev), master); if (ret) goto err_out; ret = devm_spi_register_master(&pdev->dev, master); if (!ret) return 0; err_out: spi_master_put(master); return ret; }