int ddrinit(void)
{
printf("Initializing DDR SDRAM...\n");
init_sequence();
dfii_control_write(DFII_CONTROL_SEL|DFII_CONTROL_CKE);
if(!memtest())
return 0;
return 1;
}
int sdrinit(void)
{
printf("Initializing SDRAM...\n");
init_sequence();
#ifdef DDRPHY_BASE
if(!sdrlevel())
return 0;
#endif
dfii_control_write(DFII_CONTROL_SEL);
if(!memtest())
return 0;
return 1;
}
static void init_sequence(void)
{
int i;
/* Bring CKE high */
dfii_pi0_address_write(0x0000);
dfii_pi0_baddress_write(0);
dfii_control_write(DFII_CONTROL_CKE);
/* Precharge All */
dfii_pi0_address_write(0x0400);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* Load Extended Mode Register */
dfii_pi0_baddress_write(1);
dfii_pi0_address_write(0x0000);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
dfii_pi0_baddress_write(0);
/* Load Mode Register */
dfii_pi0_address_write(0x0132); /* Reset DLL, CL=3, BL=4 */
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200);
/* Precharge All */
dfii_pi0_address_write(0x0400);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
/* 2x Auto Refresh */
for(i=0;i<2;i++) {
dfii_pi0_address_write(0);
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS);
cdelay(4);
}
/* Load Mode Register */
dfii_pi0_address_write(0x0032); /* CL=3, BL=4 */
command_p0(DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
cdelay(200);
}
void ddrhw(void)
{
dfii_control_write(DFII_CONTROL_SEL|DFII_CONTROL_CKE);
printf("DDR now under hardware control\n");
}
void ddrsw(void)
{
dfii_control_write(DFII_CONTROL_CKE);
printf("DDR now under software control\n");
}
void sdrhw(void)
{
dfii_control_write(DFII_CONTROL_SEL);
printf("SDRAM now under hardware control\n");
}
void sdrsw(void)
{
dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
printf("SDRAM now under software control\n");
}
