void dfll_enable_config_defaults(unsigned int dfll_id) { struct dfll_config dfllcfg; if (dfll_is_fine_locked(dfll_id)) { return; // DFLL already running } switch (dfll_id) { #ifdef CONFIG_DFLL0_SOURCE case 0: dfll_enable_source(CONFIG_DFLL0_SOURCE); dfll_config_init_closed_loop_mode(&dfllcfg, CONFIG_DFLL0_SOURCE, CONFIG_DFLL0_DIV, CONFIG_DFLL0_MUL); break; #endif default: Assert(false); break; } dfll_enable_closed_loop(&dfllcfg, dfll_id); while (!dfll_is_fine_locked(dfll_id)); }
/** * \brief Test Pll and DFLL (if have) * * This test enables pll/dfll source clock, sets its mul and div * factor, and then enables it. Check if it's locked after max * startup time. * * \param test Current test case. */ static void run_pll_dfll_test(const struct test_case *test) { uint32_t wait; bool status; /* avoid Cppcheck Warning */ UNUSED(wait); UNUSED(status); #if (defined CONFIG_PLL0_SOURCE) || (defined CONFIG_PLL1_SOURCE) struct pll_config pllcfg; #endif #ifdef CONFIG_PLL0_SOURCE pll_enable_source(CONFIG_PLL0_SOURCE); pll_config_defaults(&pllcfg, 0); pll_enable(&pllcfg, PLL0); for (wait = 0; wait < PLL_MAX_STARTUP_CYCLES; wait++) { //waiting PLL0 lock __asm__("nop"); }; status = pll_is_locked(PLL0); test_assert_true(test, status, "PLL0 can't be locked"); #endif #ifdef CONFIG_PLL1_SOURCE pll_enable_source(CONFIG_PLL1_SOURCE); pll_config_defaults(&pllcfg, 1); pll_enable(&pllcfg, PLL1); for (wait = 0; wait < PLL_MAX_STARTUP_CYCLES; wait++) { //waiting PLL1 lock __asm__("nop"); }; status = pll_is_locked(PLL1); test_assert_true(test, status, "PLL1 can't be locked"); #endif #ifdef CONFIG_DFLL0_SOURCE struct dfll_config dfllcfg; osc_enable(OSC_ID_RCSYS); osc_wait_ready(OSC_ID_RCSYS); dfll_config_defaults(&dfllcfg, 0); dfll_enable_closed_loop(&dfllcfg, 0); for (wait = 0; wait < DFLL_MAX_LOCK_CYCLES; wait++) { //waiting DFLL lock __asm__("nop"); }; status = dfll_is_fine_locked(0); test_assert_true(test, status, "DFLL can't be locked"); #endif }
void dfll_enable_config_defaults(uint32_t dfll_id) { #ifdef CONFIG_DFLL0_SOURCE struct dfll_config dfllcfg; #endif static bool open_loop_done = false; if((SCIF->SCIF_DFLL0CONF & SCIF_DFLL0CONF_MODE) && (SCIF->SCIF_DFLL0CONF & SCIF_DFLL0CONF_EN)) { // Closed-loop mode if (dfll_is_fine_locked(dfll_id)) { return; // DFLL already running } } if (open_loop_done == true) { return; } switch (dfll_id) { #ifdef CONFIG_DFLL0_SOURCE case 0: dfll_enable_source(CONFIG_DFLL0_SOURCE); dfll_config_init_closed_loop_mode(&dfllcfg, CONFIG_DFLL0_SOURCE, CONFIG_DFLL0_DIV, CONFIG_DFLL0_MUL); dfll_enable_closed_loop(&dfllcfg, dfll_id); while (!dfll_is_fine_locked(dfll_id)); break; #endif default: Assert(false); break; } }