void __init arch_init_irq(void)
{
int i;
/* CPU level interrupts is still not handled. */
clear_c0_status(0xff04); /* clear ERL */
set_c0_status(0x0400); /* set IP2 */
/* Set up INTC irq
*/
for (i = 0; i < 32; i++) {
disable_intc_irq(i);
set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
}
/* Set up DMAC irq
*/
for (i = 0; i < NUM_DMA; i++) {
disable_dma_irq(IRQ_DMA_0 + i);
set_irq_chip_and_handler(IRQ_DMA_0 + i, &dma_irq_type, handle_level_irq);
}
/* Set up GPIO irq
*/
for (i = 0; i < NUM_GPIO; i++) {
disable_gpio_irq(IRQ_GPIO_0 + i);
set_irq_chip_and_handler(IRQ_GPIO_0 + i, &gpio_irq_type, handle_level_irq);
}
}
static void shutdown_intc_irq(unsigned int irq)
{
disable_intc_irq(irq);
}
