/**
* \brief 32-bit checksum of DMA transfer data
*
* This test sets up DMA to do a data block transfer, and sets up
* the CRC module to do a 32 bit checksum on the data. The checksum
* will then be added to another buffer, the same procedure is setup
* with this new buffer which should result in a checksum = 0.
*
* \param test Current test case
*/
static void run_32bit_dma_test(const struct test_case *test)
{
uint32_t checksum;
bool success;
uint8_t data_buf_8bit[LENGTH(data_8bit) + sizeof(uint32_t)];
uint8_t data_8bit_cpy[LENGTH(data_8bit) + sizeof(uint32_t)];
setup_dma_channel(LENGTH(data_8bit),
(uint8_t *)data_8bit, data_buf_8bit);
crc_dma_checksum_start(CONF_TEST_DMACH, CRC_32BIT);
dma_channel_trigger_block_transfer(CONF_TEST_DMACH);
success = wait_for_dma_transfer(test);
dma_channel_disable(CONF_TEST_DMACH);
dma_disable();
checksum = crc_dma_checksum_stop();
if (!success) {
return;
}
test_assert_true(test, checksum == CRC_CHECKSUM_32BIT,
"Checksum mismatch on DMA CRC-32 test");
memcpy(data_8bit_cpy, data_8bit, LENGTH(data_8bit));
crc32_append_value(checksum,
&data_8bit_cpy[LENGTH(data_8bit_cpy) - sizeof(uint32_t)]);
setup_dma_channel(LENGTH(data_8bit_cpy),
(uint8_t *)data_8bit_cpy, data_buf_8bit);
crc_dma_checksum_start(CONF_TEST_DMACH, CRC_32BIT);
dma_channel_trigger_block_transfer(CONF_TEST_DMACH);
success = wait_for_dma_transfer(test);
dma_channel_disable(CONF_TEST_DMACH);
dma_disable();
checksum = crc_dma_checksum_stop();
if (!success) {
return;
}
test_assert_true(test, checksum == 0,
"Checksum fail check failed on DMA CRC-16 test");
}
/**
* \brief Access AES module with DMA support
*
* \note Read STATE using DMA channel 0.
* Check DMA driver example for more information about DMA usage.
*
*/
static void aes_dma_output(void)
{
// Make sure config is all zeroed out so we don't get any stray bits
memset(&config, 0, sizeof(config));
dma_enable();
dma_channel_set_burst_length(&config, DMA_CH_BURSTLEN_1BYTE_gc);
dma_channel_set_transfer_count(&config, BLOCK_LENGTH);
dma_channel_set_src_reload_mode(&config, DMA_CH_SRCRELOAD_NONE_gc);
dma_channel_set_dest_reload_mode(&config, DMA_CH_DESTRELOAD_NONE_gc);
dma_channel_set_src_dir_mode(&config, DMA_CH_SRCDIR_FIXED_gc);
dma_channel_set_dest_dir_mode(&config, DMA_CH_DESTDIR_INC_gc);
dma_channel_set_source_address(&config, (uint16_t)(uintptr_t)&AES_STATE);
dma_channel_set_destination_address(&config,
(uint16_t)(uintptr_t)single_ans);
dma_channel_write_config(DMA_CHANNEL_N, &config);
// Use the configuration above by enabling the DMA channel in use.
dma_channel_enable(DMA_CHANNEL_N);
/*
* Trigger a manual start since there is no trigger sources used in
* this example.
*/
dma_channel_trigger_block_transfer(DMA_CHANNEL_N);
while (!(DMA_CH0_CTRLB & DMA_CH_TRNIF_bm));
DMA_CH0_CTRLB |= DMA_CH_TRNIF_bm;
dma_disable();
}
/**
* \brief Trigger and wait for a successful transfer
*
* \param channel_num Channel number
*/
static void dma_transfer_block(dma_channel_num_t channel_num)
{
/* Trigger a DMA copy */
dma_channel_trigger_block_transfer(channel_num);
/* Wait for it to finish */
while (dma_get_channel_status(channel_num) !=
DMA_CH_TRANSFER_COMPLETED) {
/* Intentionally left empty */
}
}
/**
* \brief Test the error handling of the module
*
* \note Test error handling by disabling a channel which is in use
*
* \param test Current test
*/
static void run_dma_error_handling_test(const struct test_case *test)
{
/* Enable DMA */
dma_enable();
/* Reset the channel */
dma_channel_reset(DMA_CHANNEL_0);
/* Set up channel 0 to do some work, check that is it busy,
* change some settings and verify a transfer error */
dma_channel_write_burst_length(DMA_CHANNEL_0,
DMA_CH_BURSTLEN_1BYTE_gc);
dma_channel_write_transfer_count(DMA_CHANNEL_0,
MEMORY_BLOCK_SIZE);
dma_channel_write_source(DMA_CHANNEL_0,
(uint16_t)(uintptr_t)memory_block_src);
dma_channel_write_destination(DMA_CHANNEL_0,
(uint16_t)(uintptr_t)memory_block_dest);
/* Enable the channel */
dma_channel_enable(DMA_CHANNEL_0);
/* Start a block transfer */
dma_channel_trigger_block_transfer(DMA_CHANNEL_0);
/* Wait for the channel to become busy */
while (!dma_channel_is_busy(DMA_CHANNEL_0)) {
/* Intentionally left empty */
}
/* Disable the channel while it is busy */
if (dma_channel_is_busy(DMA_CHANNEL_0)) {
dma_channel_disable(DMA_CHANNEL_0);
}
/* Test whether the channel is in error */
test_assert_true(test,
dma_get_channel_status(
DMA_CHANNEL_0) == DMA_CH_TRANSFER_ERROR,
"DMA channel not in error after disabling during transfer"
" write");
dma_disable();
}
/**
* \brief main function
*/
int main(void)
{
struct dma_channel_config config;
uint32_t checksum;
pmic_init();
board_init();
sysclk_init();
sleepmgr_init();
// Randomly selected data
source[0] = 0xAA;
source[1] = 0xBB;
source[2] = 0xCC;
source[3] = 0xDD;
source[4] = 0xEE;
source[5] = 0xFF;
// Calculate checksum for the data
checksum = crc_io_checksum((void*)source, 6, CRC_16BIT);
// Append the checksum to the data, big endian
crc16_append_value(checksum, source+6);
//Enable the CRC module for DMA
crc_dma_checksum_start(DMA_CHANNEL, CRC_16BIT);
// Enable DMA
dma_enable();
// Set callback function for DMA completion
dma_set_callback(DMA_CHANNEL, example_crc_dma_transfer_done);
// Make sure config is all zeroed out so we don't get any stray bits
memset(&config, 0, sizeof(config));
/**
* This example will configure a DMA channel with the following
* settings:
* - Low interrupt priority
* - 1 byte burst length
* - DMA_BUFFER_SIZE bytes for each transfer
* - Reload source and destination address at end of each transfer
* - Increment source and destination address during transfer
* - Source address is set to \ref source
* - Destination address is set to \ref destination
*/
dma_channel_set_interrupt_level(&config, PMIC_LVL_LOW);
dma_channel_set_burst_length(&config, DMA_CH_BURSTLEN_1BYTE_gc);
dma_channel_set_transfer_count(&config, DMA_BUFFER_SIZE);
dma_channel_set_src_reload_mode(&config,
DMA_CH_SRCRELOAD_TRANSACTION_gc);
dma_channel_set_dest_reload_mode(&config,
DMA_CH_DESTRELOAD_TRANSACTION_gc);
dma_channel_set_src_dir_mode(&config, DMA_CH_SRCDIR_INC_gc);
dma_channel_set_dest_dir_mode(&config, DMA_CH_DESTDIR_INC_gc);
dma_channel_set_source_address(&config, (uint16_t)(uintptr_t)source);
dma_channel_set_destination_address(&config,
(uint16_t)(uintptr_t)destination);
dma_channel_write_config(DMA_CHANNEL, &config);
// Use the configuration above by enabling the DMA channel in use.
dma_channel_enable(DMA_CHANNEL);
// Enable interrupts
cpu_irq_enable();
// Trigger the DMA transfer
dma_channel_trigger_block_transfer(DMA_CHANNEL);
// Light the first LED to indicate that the DMA has started.
gpio_set_pin_low(LED0_GPIO);
while (true) {
/*
* Force a NOP instruction for an eventual placement of a debug
* session breakpoint.
*/
asm("nop\n");
}
}
/**
*
* \brief Test double buffering mode
*
* \note This function tests the double buffering feature of the DMA
* controller by configuring channel 0 and 1 to do the same copy,
* and verify that the channels enable each other according to
* the double buffering process.
*
* \param test Current test case
*/
static void run_dma_double_buffering_test(const struct test_case *test)
{
struct dma_channel_config config_params;
bool success = true; /* Assume everything goes well */
/* Fill source block with pattern data */
set_buffer(memory_block_src, 0x00);
block_fill(memory_block_src, MEMORY_BLOCK_SIZE);
/* Null out the destination block */
set_buffer(memory_block_dest, 0x00);
/* Null out the config params */
memset(&config_params, 0, sizeof(config_params));
/* Enable DMA */
dma_enable();
/* Enable double buffering mode on channel 0 and 1 */
dma_set_double_buffer_mode(DMA_DBUFMODE_CH01_gc);
/* Set channel 1 to copy from memory_block_src to memory_block_dest */
dma_channel_set_src_reload_mode(&config_params,
DMA_CH_SRCRELOAD_NONE_gc);
dma_channel_set_src_dir_mode(&config_params,
DMA_CH_SRCDIR_INC_gc);
dma_channel_set_dest_reload_mode(&config_params,
DMA_CH_DESTRELOAD_NONE_gc);
dma_channel_set_dest_dir_mode(&config_params,
DMA_CH_DESTDIR_INC_gc);
dma_channel_set_burst_length(&config_params,
DMA_CH_BURSTLEN_1BYTE_gc);
dma_channel_set_transfer_count(&config_params,
MEMORY_BLOCK_SIZE);
dma_channel_set_source_address(&config_params,
(uint16_t)(uintptr_t)memory_block_src);
dma_channel_set_destination_address(&config_params,
(uint16_t)(uintptr_t)memory_block_dest);
dma_channel_set_repeats(&config_params,
DOUBLE_BUFFER_REPEATS);
/* Write config and enable */
dma_channel_write_config(DMA_CHANNEL_0, &config_params);
dma_channel_write_config(DMA_CHANNEL_1, &config_params);
/* Enable only channel 0 */
dma_channel_enable(DMA_CHANNEL_0);
/* Transfer block and wait for it to finish */
dma_channel_trigger_block_transfer(DMA_CHANNEL_0);
while (dma_get_channel_status(DMA_CHANNEL_0) !=
DMA_CH_TRANSFER_COMPLETED) {
/* Intentionally left empty */
}
/*
* If double buffering is working, channel 1
* will be enabled now by the controller
*/
if (!(dma_channel_is_enabled(DMA_CHANNEL_1))) {
success = false;
}
/*
* Disable channel 0, transfer channel 1,
* and verify that channel 0 is enabled again by the controller
*/
dma_channel_disable(DMA_CHANNEL_0);
/* Transfer block and wait for it to finish */
dma_channel_trigger_block_transfer(DMA_CHANNEL_1);
while (dma_get_channel_status(DMA_CHANNEL_1) !=
DMA_CH_TRANSFER_COMPLETED) {
/* Intentionally left empty */
}
/* Verify that channel 0 is enabled again */
if (!(dma_channel_is_enabled(DMA_CHANNEL_0))) {
success = false;
}
test_assert_true(test, success,
"Double buffering mode did not function properly");
}
