void Vgen::emit(copy2& i) {
PhysReg::Map<PhysReg> moves;
Reg64 d0 = i.d0, d1 = i.d1, s0 = i.s0, s1 = i.s1;
moves[d0] = s0;
moves[d1] = s1;
auto howTo = doRegMoves(moves, rAsm); // rAsm isn't used.
for (auto& how : howTo) {
if (how.m_kind == MoveInfo::Kind::Move) {
a->Mov(X(how.m_dst), X(how.m_src));
} else {
emitXorSwap(*a, X(how.m_dst), X(how.m_src));
}
}
}
void Vgen::emit(const copy2& i) {
MovePlan moves;
Reg64 d0 = i.d0, d1 = i.d1, s0 = i.s0, s1 = i.s1;
moves[d0] = s0;
moves[d1] = s1;
auto howTo = doRegMoves(moves, rAsm); // rAsm isn't used.
for (auto& how : howTo) {
if (how.m_kind == MoveInfo::Kind::Move) {
a->Mov(X(how.m_dst), X(how.m_src));
} else {
auto const d = X(how.m_dst);
auto const s = X(how.m_src);
a->Eor(d, d, s);
a->Eor(s, d, s);
a->Eor(d, d, s);
}
}
}
void Vxls::insertCopiesAt(smart::vector<Vinstr>& code, unsigned& j,
const CopyPlan& copies, MemoryRef slots,
unsigned pos) {
MovePlan moves;
smart::vector<Vinstr> loads;
smart::hash_map<uint64_t,uint64_t*> cpool;
for (auto dst : copies) {
auto ivl = copies[dst];
if (!ivl) continue;
if (ivl->reg != InvalidReg) {
moves[dst] = ivl->reg;
} else if (ivl->cns) {
loads.emplace_back(ldimm{ivl->val, dst});
} else {
assert(ivl->spilled());
MemoryRef ptr{slots.r + PhysLoc::disp(ivl->slot)};
if (dst.isGP()) {
//assert(ptr.r.disp == PhysLoc::disp(ivl->slot));
loads.emplace_back(load{ptr, dst});
} else {
// todo: t4764214: not all xmms are wide
loads.emplace_back(loaddqu{ptr, dst});
}
}
}
auto hows = doRegMoves(moves, xmm15);
auto count = hows.size() + loads.size();
code.insert(code.begin() + j, count, ud2{});
for (auto& how : hows) {
if (how.m_kind == MoveInfo::Kind::Xchg) {
code[j] = copy2{how.m_src, how.m_dst, how.m_dst, how.m_src};
} else {
code[j] = copy{how.m_src, how.m_dst};
}
code[j++].pos = pos;
}
for (auto& inst : loads) {
code[j] = inst;
code[j++].pos = pos;
}
}
