/* Max_instr indicates maximum number of instructions that want to complete during this simulation run. */ static exc_t sim_step_pipe(int max_instr) { exc_t wb_exc = mem_wb_curr->exception; exc_t mem_exc = mem_wb_next->exception; /* How many instructions are ahead of one in wb / ex? */ int ahead_mem = (wb_exc != EXC_BUBBLE); int ahead_ex = ahead_mem + (mem_exc != EXC_BUBBLE); bool_t wb_ok = (wb_exc == EXC_NONE) || (wb_exc == EXC_BUBBLE); bool_t mem_ok = (mem_exc == EXC_NONE) || (mem_exc == EXC_BUBBLE); bool_t update_mem = wb_ok && ahead_mem < max_instr; bool_t update_cc = update_mem && mem_ok && ahead_ex < max_instr; if (!update_mem) { sim_log("Disabling memory write. wb_exc = %s\n", exc_name(wb_exc)); } /* Update program-visible state */ update_state(update_mem, update_cc); /* Update pipe registers */ update_pipes(); if (pc_state->op == P_ERROR) pc_curr->exception = EXC_PIPE; if (if_id_state->op == P_ERROR) if_id_curr->exception = EXC_PIPE; if (id_ex_state->op == P_ERROR) id_ex_curr->exception = EXC_PIPE; if (ex_mem_state->op == P_ERROR) ex_mem_curr->exception = EXC_PIPE; if (mem_wb_state->op == P_ERROR) mem_wb_curr->exception = EXC_PIPE; /* Need to do decode after execute & memory stages, and memory stage before execute, in order to propagate forwarding values properly */ do_if_stage(); do_mem_stage(); do_ex_stage(); do_id_wb_stages(); do_stall_check(); if (id_ex_curr->exception != EXC_NONE && id_ex_curr->exception != EXC_BUBBLE) { if_id_state->op = P_BUBBLE; id_ex_state->op = P_BUBBLE; } /* Performance monitoring */ if (mem_wb_curr->exception != EXC_BUBBLE && mem_wb_curr->icode != I_POP2) { starting_up = 0; instructions++; cycles++; } else { if (!starting_up) cycles++; } sim_report(); return mem_wb_curr->exception; }
/* Max_instr indicates maximum number of instructions that want to complete during this simulation run. */ static byte_t sim_step_pipe(int max_instr, int ccount) { byte_t wb_status = mem_wb_curr->status; byte_t mem_status = mem_wb_next->status; /* How many instructions are ahead of one in wb / ex? */ int ahead_mem = (wb_status != STAT_BUB); int ahead_ex = ahead_mem + (mem_status != STAT_BUB); bool_t update_mem = ahead_mem < max_instr; bool_t update_cc = ahead_ex < max_instr; /* Update program-visible state */ update_state(update_mem, update_cc); /* Update pipe registers */ update_pipes(); tty_report(ccount); if (pc_state->op == P_ERROR) pc_curr->status = STAT_PIP; if (if_id_state->op == P_ERROR) if_id_curr->status = STAT_PIP; if (id_ex_state->op == P_ERROR) id_ex_curr->status = STAT_PIP; if (ex_mem_state->op == P_ERROR) ex_mem_curr->status = STAT_PIP; if (mem_wb_state->op == P_ERROR) mem_wb_curr->status = STAT_PIP; /* Need to do decode after execute & memory stages, and memory stage before execute, in order to propagate forwarding values properly */ do_if_stage(); do_mem_stage(); do_ex_stage(); do_id_wb_stages(); do_stall_check(); #if 0 /* This doesn't seem necessary */ if (id_ex_curr->status != STAT_AOK && id_ex_curr->status != STAT_BUB) { if_id_state->op = P_BUBBLE; id_ex_state->op = P_BUBBLE; } #endif /* Performance monitoring */ if (mem_wb_curr->status != STAT_BUB) { //if (mem_wb_curr->status != STAT_BUB && mem_wb_curr->icode != I_POP2) { starting_up = 0; instructions++; cycles++; } else { if (!starting_up) cycles++; } sim_report(); return status; }