C++ (Cpp) dphy_cfg_start示例

示例#1

文件： csi_driver.c 项目： ShinySide/SM-G361H

static void dphy_init_common(u32 bps_per_lane, u32 phy_id, u32 rx_mode)
{
	u8 temp = 0;
	struct csi_pclk_cfg csi_pclk_cfg_val = {0, 0, 0, 0};

	csi_core_write_part(PHY_SHUTDOWNZ,  0, 0, 1);
	csi_core_write_part(DPHY_RSTZ, 0, 0, 1);
	csi_core_write_part(PHY_TST_CRTL0, 1, PHY_TESTCLR, 1);
	udelay(1);
	csi_core_write_part(PHY_TST_CRTL0, 0, PHY_TESTCLR, 1);
	udelay(1);
	dphy_cfg_start();

#if defined(CONFIG_MACH_SP7720EA)
#if defined(CONFIG_SC_FPGA)
	sci_glb_write(SPRD_GPIO_BASE + 0x0008, 0xd, -1UL);
	dphy_write(0x30, 0xc0, &temp);
#endif
	dphy_write(0x37, 0x03, &temp);
	//LOG_DEBUG2 ("%04x default  reg value: %04x\r\n", 0x37, temp);
	dphy_write(0x47, 0x03, &temp);
	//LOG_DEBUG2 ("%04x default  reg value: %04x\r\n", 0x47, temp);
	dphy_write(0x57, 0x03, &temp);
	//LOG_DEBUG2 ("%04x default  reg value: %04x\r\n", 0x57, temp);
	dphy_write(0x67, 0x03, &temp);
	dphy_write(0x77, 0x03, &temp);
#else
	csi_get_pclk_cfg(bps_per_lane, &csi_pclk_cfg_val);

#if IS_ENABLED(VERSION3L) || IS_ENABLED(VERSION3T) || IS_ENABLED(VERSION3D)
	if (0x03 == phy_id) {
		if (0x00 == rx_mode) {
			dphy_write(0x34, 0x14, &temp);
		} else {
			dphy_write(0x34, 0xA0, &temp);
		}
	} else {
		dphy_write(0x34, 0x14, &temp);
	}
#else
	dphy_write(0x34, 0x14, &temp);
#endif

	dphy_write(0x44, (((csi_pclk_cfg_val.hsfreqrange & 0x3F) << 1) & 0x7E), &temp);
	dphy_write(0x75, (0x80 | (csi_pclk_cfg_val.hsrxthssettle & 0x7F)), &temp);
	dphy_write(0x54, 0x14, &temp);
	dphy_write(0x64, 0x14, &temp);
	dphy_write(0x74, 0x14, &temp);
#endif
	dphy_cfg_done();
}

示例#2

文件： csi_driver.c 项目： FyFyVy/android_kernel_samsung_j13g

static void dphy_init_common(u32 pclk, u32 phy_id, u32 rx_mode)
{
	u8 temp = 0;
	struct csi_pclk_cfg csi_pclk_cfg_val = {0, 0, 0, 0};

	csi_core_write_part(PHY_SHUTDOWNZ,  0, 0, 1);
	csi_core_write_part(DPHY_RSTZ, 0, 0, 1);
	csi_core_write_part(PHY_TST_CRTL0, 1, PHY_TESTCLR, 1);
	udelay(1);
	csi_core_write_part(PHY_TST_CRTL0, 0, PHY_TESTCLR, 1);
	udelay(1);
	dphy_cfg_start();

	csi_get_pclk_cfg(pclk, &csi_pclk_cfg_val);

#if defined(CONFIG_ARCH_SCX30G)
	if (0x03 == phy_id) {
		if (0x00 == rx_mode) {
			dphy_write(0x34, 0xA0, &temp);
		} else {
			dphy_write(0x34, 0x14, &temp);
		}
	} else {
		dphy_write(0x34, 0x14, &temp);
	}
#else
	dphy_write(0x34, 0x14, &temp);
#endif

	dphy_write(0x44, (((csi_pclk_cfg_val.hsfreqrange & 0x3F) << 1) & 0x7E), &temp);
	dphy_write(0x75, (0x80 | (csi_pclk_cfg_val.hsrxthssettle & 0x7F)), &temp);
	dphy_write(0x54, 0x14, &temp);
	dphy_write(0x64, 0x14, &temp);
	dphy_write(0x74, 0x14, &temp);

	dphy_cfg_done();
}