static irqreturn_t hdlcd_irq(int irq, void *arg) { struct drm_device *drm = arg; struct hdlcd_drm_private *hdlcd = drm->dev_private; unsigned long irq_status; irq_status = hdlcd_read(hdlcd, HDLCD_REG_INT_STATUS); #ifdef CONFIG_DEBUG_FS if (irq_status & HDLCD_INTERRUPT_UNDERRUN) atomic_inc(&hdlcd->buffer_underrun_count); if (irq_status & HDLCD_INTERRUPT_DMA_END) atomic_inc(&hdlcd->dma_end_count); if (irq_status & HDLCD_INTERRUPT_BUS_ERROR) atomic_inc(&hdlcd->bus_error_count); if (irq_status & HDLCD_INTERRUPT_VSYNC) atomic_inc(&hdlcd->vsync_count); #endif if (irq_status & HDLCD_INTERRUPT_VSYNC) drm_crtc_handle_vblank(&hdlcd->crtc); /* acknowledge interrupt(s) */ hdlcd_write(hdlcd, HDLCD_REG_INT_CLEAR, irq_status); return IRQ_HANDLED; }
static irqreturn_t decon_irq_handler(int irq, void *dev_id) { struct decon_context *ctx = dev_id; u32 val; int win; if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags)) goto out; val = readl(ctx->addr + DECON_VIDINTCON1); val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND; if (val) { for (win = ctx->first_win; win < WINDOWS_NR ; win++) { struct exynos_drm_plane *plane = &ctx->planes[win]; if (!plane->pending_fb) continue; exynos_drm_crtc_finish_update(ctx->crtc, plane); } /* clear */ writel(val, ctx->addr + DECON_VIDINTCON1); drm_crtc_handle_vblank(&ctx->crtc->base); } out: return IRQ_HANDLED; }
void decon_te_irq_handler(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags)) return; if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags)) decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0); drm_crtc_handle_vblank(&ctx->crtc->base); }
void decon_te_irq_handler(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; u32 val; if (!test_bit(BIT_CLKS_ENABLED, &ctx->enabled)) return; if (atomic_add_unless(&ctx->win_updated, -1, 0)) { /* trigger */ val = readl(ctx->addr + DECON_TRIGCON); val |= TRIGCON_SWTRIGCMD; writel(val, ctx->addr + DECON_TRIGCON); } drm_crtc_handle_vblank(&ctx->crtc->base); }
static irqreturn_t rcar_du_crtc_irq(int irq, void *arg) { struct rcar_du_crtc *rcrtc = arg; irqreturn_t ret = IRQ_NONE; u32 status; status = rcar_du_crtc_read(rcrtc, DSSR); rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK); if (status & DSSR_FRM) { drm_crtc_handle_vblank(&rcrtc->crtc); rcar_du_crtc_finish_page_flip(rcrtc); ret = IRQ_HANDLED; } return ret; }
static irqreturn_t mxsfb_irq_handler(int irq, void *data) { struct drm_device *drm = data; struct mxsfb_drm_private *mxsfb = drm->dev_private; u32 reg; mxsfb_enable_axi_clk(mxsfb); reg = readl(mxsfb->base + LCDC_CTRL1); if (reg & CTRL1_CUR_FRAME_DONE_IRQ) drm_crtc_handle_vblank(&mxsfb->pipe.crtc); writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); mxsfb_disable_axi_clk(mxsfb); return IRQ_HANDLED; }
static irqreturn_t decon_vsync_irq_handler(int irq, void *dev_id) { struct decon_context *ctx = dev_id; u32 val; if (!test_bit(BIT_CLKS_ENABLED, &ctx->enabled)) goto out; val = readl(ctx->addr + DECON_VIDINTCON1); if (val & VIDINTCON1_INTFRMPEND) { drm_crtc_handle_vblank(&ctx->crtc->base); /* clear */ writel(VIDINTCON1_INTFRMPEND, ctx->addr + DECON_VIDINTCON1); } out: return IRQ_HANDLED; }
static irqreturn_t ade_irq_handler(int irq, void *data) { struct ade_crtc *acrtc = data; struct ade_hw_ctx *ctx = acrtc->ctx; struct drm_crtc *crtc = &acrtc->base; void __iomem *base = ctx->base; u32 status; status = readl(base + LDI_MSK_INT); DRM_DEBUG_VBL("LDI IRQ: status=0x%X\n", status); /* vblank irq */ if (status & BIT(FRAME_END_INT_EN_OFST)) { ade_update_bits(base + LDI_INT_CLR, FRAME_END_INT_EN_OFST, MASK(1), 1); drm_crtc_handle_vblank(crtc); } return IRQ_HANDLED; }
irqreturn_t pl111_irq(int irq, void *data) { struct pl111_drm_dev_private *priv = data; u32 irq_stat; irqreturn_t status = IRQ_NONE; irq_stat = readl(priv->regs + CLCD_PL111_MIS); if (!irq_stat) return IRQ_NONE; if (irq_stat & CLCD_IRQ_NEXTBASE_UPDATE) { drm_crtc_handle_vblank(&priv->pipe.crtc); status = IRQ_HANDLED; } /* Clear the interrupt once done */ writel(irq_stat, priv->regs + CLCD_PL111_ICR); return status; }