static void intel_mst_disable_dp(struct intel_encoder *encoder, struct intel_crtc_state *old_crtc_state, struct drm_connector_state *old_conn_state) { struct intel_dp_mst_encoder *intel_mst = enc_to_mst(&encoder->base); struct intel_digital_port *intel_dig_port = intel_mst->primary; struct intel_dp *intel_dp = &intel_dig_port->dp; struct intel_connector *connector = to_intel_connector(old_conn_state->connector); int ret; DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links); drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port); ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); if (ret) { DRM_ERROR("failed to update payload %d\n", ret); } }
/* * Writes payload allocation table in immediate downstream device. */ bool dm_helpers_dp_mst_write_payload_allocation_table( struct dc_context *ctx, const struct dc_stream_state *stream, struct dp_mst_stream_allocation_table *proposed_table, bool enable) { struct amdgpu_dm_connector *aconnector; struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_port *mst_port; int slots = 0; bool ret; int clock; int bpp = 0; int pbn = 0; aconnector = stream->sink->priv; if (!aconnector || !aconnector->mst_port) return false; mst_mgr = &aconnector->mst_port->mst_mgr; if (!mst_mgr->mst_state) return false; mst_port = aconnector->port; if (enable) { clock = stream->timing.pix_clk_khz; switch (stream->timing.display_color_depth) { case COLOR_DEPTH_666: bpp = 6; break; case COLOR_DEPTH_888: bpp = 8; break; case COLOR_DEPTH_101010: bpp = 10; break; case COLOR_DEPTH_121212: bpp = 12; break; case COLOR_DEPTH_141414: bpp = 14; break; case COLOR_DEPTH_161616: bpp = 16; break; default: ASSERT(bpp != 0); break; } bpp = bpp * 3; /* TODO need to know link rate */ pbn = drm_dp_calc_pbn_mode(clock, bpp); slots = drm_dp_find_vcpi_slots(mst_mgr, pbn); ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, slots); if (!ret) return false; } else { drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port); } ret = drm_dp_update_payload_part1(mst_mgr); /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or * AUX message. The sequence is slot 1-63 allocated sequence for each * stream. AMD ASIC stream slot allocation should follow the same * sequence. copy DRM MST allocation to dc */ get_payload_table(aconnector, proposed_table); if (ret) return false; return true; }