static void p088pw_disable(struct intel_dsi_device *dsi) { int val = 0; struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); struct drm_device *dev = intel_dsi->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; DRM_DEBUG_KMS("\n"); printk("p088pw_disable\n"); msleep(200); dsi_vc_dcs_write_0(intel_dsi, 0, 0x28); msleep(80); dsi_vc_dcs_write_0(intel_dsi, 0, 0x10); msleep(34); val = intel_mid_pmic_readb(0x12); val &= ~(1<<5); intel_mid_pmic_writeb(0x12, val); usleep_range(100000, 120000); vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00); vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004); usleep_range(100000, 120000); vlv_gpio_nc_write(dev_priv, GPIO_NC_10_PCONF0, 0x2000CC00); vlv_gpio_nc_write(dev_priv, GPIO_NC_10_PAD, 0x00000004); usleep_range(100000, 120000); vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00); vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000004); }
static void n080ice_gb1_enable(struct intel_dsi_device *dsi) { struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); DRM_DEBUG_KMS("\n"); dsi_vc_dcs_write_0(intel_dsi, 0, 0x35); dsi_vc_dcs_write_0(intel_dsi, 0, 0x11); msleep(5); dsi_vc_dcs_write_0(intel_dsi, 0, 0x29); }
void lpm070w425b_enable(struct intel_dsi_device *dsi) { struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); DRM_DEBUG_KMS("\n"); dsi_vc_dcs_write_0(intel_dsi, 0, 0x11); msleep(120); dsi_vc_dcs_write_0(intel_dsi, 0, 0x29); }
static void bp080wx7_disable(struct intel_dsi_device *dsi) { struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); DRM_DEBUG_KMS("\n"); dsi_vc_dcs_write_0(intel_dsi, 0, 0x28); msleep(30); dsi_vc_dcs_write_0(intel_dsi, 0, 0x10); msleep(30); }
static void n080ice_gb1_disable(struct intel_dsi_device *dsi) { struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); DRM_DEBUG_KMS("\n"); dsi_vc_dcs_write_0(intel_dsi, 0, 0x28); msleep(30); //dsi_vc_dcs_write(intel_dsi, 0, boe_disable_ic_power, sizeof(boe_disable_ic_power)); msleep(15); dsi_vc_dcs_write_0(intel_dsi, 0, 0x10); msleep(30); }
static void p088pw_enable(struct intel_dsi_device *dsi) { struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); DRM_DEBUG_KMS("\n"); //printk("p088pw_enable\n"); dsi_vc_dcs_write_0(intel_dsi, 0, 0x11); msleep(120); dsi_vc_dcs_write_0(intel_dsi, 0, 0x29); msleep(20); }
static void kd080d14_enable(struct intel_dsi_device *dsi) { struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); DRM_DEBUG_KMS("\n"); printk("--->%s\n",__func__); dsi_vc_dcs_write_0(intel_dsi, 0, 0x11); msleep(300); //wait for 30ms dsi_vc_dcs_write(intel_dsi, 0, cpt_enable_ic_power, sizeof(cpt_enable_ic_power)); msleep(150); //wait for 150ms dsi_vc_dcs_write_0(intel_dsi, 0, 0x29); msleep(50); }
void lpm070w425b_disable(struct intel_dsi_device *dsi) { struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); struct drm_device *dev = intel_dsi->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; DRM_DEBUG_KMS("\n"); dsi_vc_dcs_write_0(intel_dsi, 0, 0x28); msleep(20); dsi_vc_dcs_write_0(intel_dsi, 0, 0x10); msleep(80); }
static void auo_disable(struct intel_dsi_device *dsi) { struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); int val = 0; DRM_DEBUG_KMS("\n"); dsi_vc_dcs_write_0(intel_dsi, 0, 0x28); msleep(80); dsi_vc_dcs_write_0(intel_dsi, 0, 0x10); msleep(34); val = intel_mid_pmic_readb(0x12); val &= ~(1<<5); intel_mid_pmic_writeb(0x12, val); }
static void kd080d10_31na_a11_disable(struct intel_dsi_device *dsi) { struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); DRM_DEBUG_KMS("\n"); intel_dsi->hs = 0; dsi_vc_dcs_write_0(intel_dsi, 0, 0x28); msleep(100); dsi_vc_dcs_write_0(intel_dsi, 0, 0x10); msleep(40); intel_dsi->hs = 1; }
void lpm070w425b_dpms(struct intel_dsi_device *dsi, bool enable) { struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); DRM_DEBUG_KMS("\n"); if (enable) { dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_EXIT_SLEEP_MODE); dsi_vc_dcs_write_1(intel_dsi, 0, MIPI_DCS_SET_TEAR_ON, 0x00); dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_ON); dsi_vc_dcs_write_1(intel_dsi, 0, 0x14, 0x55); } else { dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_OFF); dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_ENTER_SLEEP_MODE); } }
static void kd080d14_disable(struct intel_dsi_device *dsi) { struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); struct drm_device *dev = intel_dsi->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; DRM_DEBUG_KMS("\n"); printk("--->%s\n",__func__); msleep(200); dsi_vc_dcs_write_0(intel_dsi, 0, 0x28); msleep(80); //dsi_vc_dcs_write(intel_dsi, 0, cpt_disable_ic_power, sizeof(cpt_disable_ic_power)); dsi_vc_dcs_write_0(intel_dsi, 0, 0x10); msleep(34); vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PCONF0, 0x2000CC00); vlv_gpio_nc_write(dev_priv, GPIO_NC_9_PAD, 0x00000004); usleep_range(100000, 120000); vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PCONF0, 0x2000CC00); vlv_gpio_nc_write(dev_priv, GPIO_NC_11_PAD, 0x00000004); }
static void kd080d10_31na_a11_dpms(struct intel_dsi_device *dsi, bool enable) { #if 0 struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); DRM_DEBUG_KMS("\n"); if (enable) { dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_EXIT_SLEEP_MODE); dsi_vc_dcs_write_1(intel_dsi, 0, MIPI_DCS_SET_TEAR_ON, 0x00); dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_ON); dsi_vc_dcs_write_1(intel_dsi, 0, 0x14, 0x55); } else { dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_OFF); dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_ENTER_SLEEP_MODE); } #endif }
void nt51021_dpms(struct intel_dsi_device *dsi, bool enable) { struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); DRM_DEBUG_KMS("\n"); if (enable) { dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_EXIT_SLEEP_MODE); dsi_vc_dcs_write_1(intel_dsi, 0, MIPI_DCS_SET_TEAR_ON, 0x00); dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_ON); dsi_vc_dcs_write_1(intel_dsi, 0, 0x14, 0x55); //dsi_vc_generic_write_2(intel_dsi, 0, nt51021_soft_reset[0], nt51021_soft_reset[1]); //soft reset } else { dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_OFF); dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_ENTER_SLEEP_MODE); } }
void lpm070w425b_send_otp_cmds(struct intel_dsi_device *dsi) { struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev); DRM_DEBUG_KMS("\n"); dsi_vc_dcs_write_0(intel_dsi, 0, 0x10); msleep(50); dsi_vc_dcs_write_0(intel_dsi, 0, 0x01); usleep_range(5000, 7000); { unsigned char ucData[] = {0xb0, 0x00}; dsi_vc_generic_write(intel_dsi, 0, ucData, 2); } { unsigned char ucData[] = {0xb3, 0x14, 0x08, 0x00, 0x22, 0x00}; dsi_vc_generic_write(intel_dsi, 0, ucData, 6); } { unsigned char ucData[] = {0xb4, 0x0c}; dsi_vc_generic_write(intel_dsi, 0, ucData, 6); } { unsigned char ucData[] = {0xb6, 0x3a, 0xD3}; dsi_vc_generic_write(intel_dsi, 0, ucData, 6); } dsi_vc_dcs_write_1(intel_dsi, 0, 0x3A, 0x77); dsi_vc_dcs_write_1(intel_dsi, 0, 0x36, 0xC0); { unsigned char ucData[] = {0x2A, 0x00, 0x00, 0x04, 0xAF}; dsi_vc_generic_write(intel_dsi, 0, ucData, 6); } { unsigned char ucData[] = {0x2B, 0x00, 0x00, 0x07, 0x7F}; dsi_vc_generic_write(intel_dsi, 0, ucData, 6); } }