void lpm070w425b_dpms(struct intel_dsi_device *dsi, bool enable)
{
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);

	DRM_DEBUG_KMS("\n");
	if (enable) {
		dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_EXIT_SLEEP_MODE);

		dsi_vc_dcs_write_1(intel_dsi, 0, MIPI_DCS_SET_TEAR_ON, 0x00);

		dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_ON);
		dsi_vc_dcs_write_1(intel_dsi, 0, 0x14, 0x55);

	} else {
		dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_OFF);
		dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_ENTER_SLEEP_MODE);
	}
}
static void kd080d10_31na_a11_dpms(struct intel_dsi_device *dsi, bool enable)
{
#if 0
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);

	DRM_DEBUG_KMS("\n");
	if (enable) {
		dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_EXIT_SLEEP_MODE);

		dsi_vc_dcs_write_1(intel_dsi, 0, MIPI_DCS_SET_TEAR_ON, 0x00);

		dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_ON);
		dsi_vc_dcs_write_1(intel_dsi, 0, 0x14, 0x55);

	} else {
		dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_OFF);
		dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_ENTER_SLEEP_MODE);
	}
#endif
}
void nt51021_dpms(struct intel_dsi_device *dsi, bool enable)
{
    struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);

    DRM_DEBUG_KMS("\n");

    if (enable) {

        dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_EXIT_SLEEP_MODE);

        dsi_vc_dcs_write_1(intel_dsi, 0, MIPI_DCS_SET_TEAR_ON, 0x00);

        dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_ON);
        dsi_vc_dcs_write_1(intel_dsi, 0, 0x14, 0x55);
        //dsi_vc_generic_write_2(intel_dsi, 0, nt51021_soft_reset[0], nt51021_soft_reset[1]); //soft reset

    } else {
        dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_SET_DISPLAY_OFF);
        dsi_vc_dcs_write_0(intel_dsi, 0, MIPI_DCS_ENTER_SLEEP_MODE);
    }
}
void lpm070w425b_send_otp_cmds(struct intel_dsi_device *dsi)
{
	struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);

	DRM_DEBUG_KMS("\n");

	dsi_vc_dcs_write_0(intel_dsi, 0, 0x10);
	msleep(50);

	dsi_vc_dcs_write_0(intel_dsi, 0, 0x01);
	usleep_range(5000, 7000);
	{
		unsigned char ucData[] = {0xb0, 0x00};
		dsi_vc_generic_write(intel_dsi, 0, ucData, 2);
	}
	{
		unsigned char ucData[] = {0xb3, 0x14, 0x08, 0x00, 0x22, 0x00};
		dsi_vc_generic_write(intel_dsi, 0, ucData, 6);
	}
	{
		unsigned char ucData[] = {0xb4, 0x0c};
		dsi_vc_generic_write(intel_dsi, 0, ucData, 6);
	}
	{
		unsigned char ucData[] = {0xb6, 0x3a, 0xD3};
		dsi_vc_generic_write(intel_dsi, 0, ucData, 6);
	}
		dsi_vc_dcs_write_1(intel_dsi, 0, 0x3A, 0x77);
		dsi_vc_dcs_write_1(intel_dsi, 0, 0x36, 0xC0);
	{
		unsigned char ucData[] = {0x2A, 0x00, 0x00, 0x04, 0xAF};
		dsi_vc_generic_write(intel_dsi, 0, ucData, 6);
	}
	{
		unsigned char ucData[] = {0x2B, 0x00, 0x00, 0x07, 0x7F};
		dsi_vc_generic_write(intel_dsi, 0, ucData, 6);
	}

}
void nt5102_send_otp_cmds(struct intel_dsi_device *dsi)
{
    struct intel_dsi *intel_dsi = container_of(dsi, struct intel_dsi, dev);
    struct drm_device *dev = intel_dsi->base.base.dev;
    struct drm_i915_private *dev_priv = dev->dev_private;
    DRM_DEBUG_KMS("\n");
    printk("wqf-%s\n",__func__);
    intel_dsi->hs =true;
    //mutex_lock(&(dev_priv->i915_bklt_control_mutex));
    if ((dev_priv->spark_cabc_dpst_on)) {
        /*bl brightness */
        dsi_vc_dcs_write_1(intel_dsi,0,0x01,0x00);
        dsi_vc_dcs_write_1(intel_dsi,0,0x83,0x00);
        dsi_vc_dcs_write_1(intel_dsi,0,0x84,0x00);
        dsi_vc_dcs_write_1(intel_dsi,0,0x9F,0x7F);
        dsi_vc_dcs_write_1(intel_dsi,0,0x97,0xFF);
        /*CABC on moving*/
        dsi_vc_dcs_write_1(intel_dsi,0,0x83,0xBB);
        dsi_vc_dcs_write_1(intel_dsi,0,0x84,0x22);
        dsi_vc_dcs_write_1(intel_dsi,0,0x90,0x00);
        dsi_vc_dcs_write_1(intel_dsi,0,0x91,0xA2);
        dsi_vc_dcs_write_1(intel_dsi,0,0x94,0x2A);
        dsi_vc_dcs_write_1(intel_dsi,0,0x95,0x20);
        dsi_vc_dcs_write_1(intel_dsi,0,0x96,0x01);
        dsi_vc_dcs_write_1(intel_dsi,0,0x9B,0x8C);
    }
    /*mipi yantu*/
    dsi_vc_dcs_write_1(intel_dsi,0,0x83,0xAA);
    dsi_vc_dcs_write_1(intel_dsi,0,0x84,0x11);
    dsi_vc_dcs_write_1(intel_dsi,0,0xA0,0x2D);
    dsi_vc_dcs_write_1(intel_dsi,0,0xA1,0x2D);
    //mutex_unlock(&(dev_priv->i915_bklt_control_mutex));

}