static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save) { u32 gpe0_sts; gpe0_sts = reset_gpe0_status(); dump_gpe0_status(gpe0_sts); }
static void smm_relocate(void) { u32 smi_en; printk(BIOS_DEBUG, "Initializing SMM handler..."); pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } /* copy the SMM relocation code */ memcpy((void *)0x38000, &smm_relocation_start, &smm_relocation_end - &smm_relocation_start); printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); dump_gpe0_status(reset_gpe0_status()); dump_tco_status(reset_tco_status()); /* Enable SMI generation: * - on TCO events * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) * No SMIs: * - on microcontroller writes (io 0x62/0x66) */ outl(smi_en | (TCO_EN | APMC_EN | SLP_SMI_EN | BIOS_EN | EOS | GBL_SMI_EN), pmbase + SMI_EN); /** * There are several methods of raising a controlled SMI# via * software, among them: * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * * Using the local apic is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so * I'm not too worried about the better of the methods at the moment */ /* raise an SMI interrupt */ printk(BIOS_SPEW, " ... raise SMI#\n"); outb(0x00, 0xb2); }
static void smm_relocate(void) { u32 smi_en; u16 pm1_en; printk(BIOS_DEBUG, "Initializing SMM handler..."); pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), D31F0_PMBASE) & 0xfffc; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN); if (smi_en & GBL_SMI_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } /* copy the SMM relocation code */ memcpy((void *)0x38000, &smm_relocation_start, &smm_relocation_end - &smm_relocation_start); wbinvd(); printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); dump_gpe0_status(reset_gpe0_status()); dump_alt_gp_smi_status(reset_alt_gp_smi_status()); dump_tco_status(reset_tco_status()); /* Enable SMI generation: * - on TCO events * - on APMC writes (io 0xb2) * - on writes to GBL_RLS (bios commands) * No SMIs: * - on microcontroller writes (io 0x62/0x66) */ smi_en = 0; /* reset SMI enables */ smi_en |= TCO_EN; smi_en |= APMC_EN; #if DEBUG_PERIODIC_SMIS /* Set DEBUG_PERIODIC_SMIS in i82801ix.h to debug using * periodic SMIs. */ smi_en |= PERIODIC_EN; #endif smi_en |= BIOS_EN; /* The following need to be on for SMIs to happen */ smi_en |= EOS | GBL_SMI_EN; outl(smi_en, pmbase + SMI_EN); pm1_en = 0; pm1_en |= PWRBTN_EN; pm1_en |= GBL_EN; outw(pm1_en, pmbase + PM1_EN); /** * There are several methods of raising a controlled SMI# via * software, among them: * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * * Using the local apic is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so * I'm not too worried about the better of the methods at the moment */ /* raise an SMI interrupt */ printk(BIOS_SPEW, " ... raise SMI#\n"); outb(0x00, 0xb2); }
void southbridge_smm_init(void) { u32 smi_en; u16 pm1_en; u32 gpe0_en; #if CONFIG_ELOG /* Log events from chipset before clearing */ pch_log_state(); #endif printk(BIOS_DEBUG, "Initializing southbridge SMI..."); pmbase = pci_read_config32(PCI_DEV(0, 0x1f, 0), PMBASE) & 0xff80; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); smi_en = inl(pmbase + SMI_EN); if (smi_en & APMC_EN) { printk(BIOS_INFO, "SMI# handler already enabled?\n"); return; } printk(BIOS_DEBUG, "\n"); dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); dump_gpe0_status(reset_gpe0_status()); dump_alt_gp_smi_status(reset_alt_gp_smi_status()); dump_tco_status(reset_tco_status()); /* Disable GPE0 PME_B0 */ gpe0_en = inl(pmbase + GPE0_EN); gpe0_en &= ~PME_B0_EN; outl(gpe0_en, pmbase + GPE0_EN); pm1_en = 0; pm1_en |= PWRBTN_EN; pm1_en |= GBL_EN; outw(pm1_en, pmbase + PM1_EN); /* Enable SMI generation: * - on TCO events * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) * No SMIs: * - on microcontroller writes (io 0x62/0x66) */ smi_en = 0; /* reset SMI enables */ #if 0 smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; #endif smi_en |= TCO_EN; smi_en |= APMC_EN; #if DEBUG_PERIODIC_SMIS /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using * periodic SMIs. */ smi_en |= PERIODIC_EN; #endif smi_en |= SLP_SMI_EN; #if 0 smi_en |= BIOS_EN; #endif /* The following need to be on for SMIs to happen */ smi_en |= EOS | GBL_SMI_EN; outl(smi_en, pmbase + SMI_EN); }