eMBMasterReqErrCode eMBMasterReqReadHoldingRegister(uint8_t ucSndAddr, uint16_t usRegAddr, uint16_t usNRegs, uint32_t lTimeOut) { uint8_t *ucMBFrame; eMBMasterReqErrCode eErrStatus = MB_MRE_NO_ERR; if (ucSndAddr > CONFIG_MB_MASTER_TOTAL_SLAVE_NUM) { eErrStatus = MB_MRE_ILL_ARG; } else if (xMBMasterRunResTake(lTimeOut) == false) { eErrStatus = MB_MRE_MASTER_BUSY; } else { vMBMasterGetPDUSndBuf(&ucMBFrame); vMBMasterSetDestAddress(ucSndAddr); ucMBFrame[MB_PDU_FUNC_OFF] = MB_FUNC_READ_HOLDING_REGISTER; ucMBFrame[MB_PDU_REQ_READ_ADDR_OFF] = usRegAddr >> 8; ucMBFrame[MB_PDU_REQ_READ_ADDR_OFF + 1] = usRegAddr; ucMBFrame[MB_PDU_REQ_READ_REGCNT_OFF] = usNRegs >> 8; ucMBFrame[MB_PDU_REQ_READ_REGCNT_OFF + 1] = usNRegs; vMBMasterSetPDUSndLength(MB_PDU_SIZE_MIN + MB_PDU_REQ_READ_SIZE); (void)xMBMasterPortEventPost(EV_MASTER_FRAME_SENT); eErrStatus = eMBMasterWaitRequestFinish(); } return eErrStatus; }
/** * This function will request write multiple holding register. * * @param ucSndAddr salve address * @param usRegAddr register start address * @param usNRegs register total number * @param pusDataBuffer data to be written * @param lTimeOut timeout (-1 will waiting forever) * * @return error code */ eMBMasterReqErrCode eMBMasterReqWriteMultipleHoldingRegister( UCHAR ucSndAddr, USHORT usRegAddr, USHORT usNRegs, USHORT * pusDataBuffer, LONG lTimeOut ) { UCHAR *ucMBFrame; USHORT usRegIndex = 0; eMBMasterReqErrCode eErrStatus = MB_MRE_NO_ERR; if ( ucSndAddr > MB_MASTER_TOTAL_SLAVE_NUM ) eErrStatus = MB_MRE_ILL_ARG; else if ( xMBMasterRunResTake( lTimeOut ) == FALSE ) eErrStatus = MB_MRE_MASTER_BUSY; else { vMBMasterGetPDUSndBuf(&ucMBFrame); vMBMasterSetDestAddress(ucSndAddr); ucMBFrame[MB_PDU_FUNC_OFF] = MB_FUNC_WRITE_MULTIPLE_REGISTERS; ucMBFrame[MB_PDU_REQ_WRITE_MUL_ADDR_OFF] = usRegAddr >> 8; ucMBFrame[MB_PDU_REQ_WRITE_MUL_ADDR_OFF + 1] = usRegAddr; ucMBFrame[MB_PDU_REQ_WRITE_MUL_REGCNT_OFF] = usNRegs >> 8; ucMBFrame[MB_PDU_REQ_WRITE_MUL_REGCNT_OFF + 1] = usNRegs ; ucMBFrame[MB_PDU_REQ_WRITE_MUL_BYTECNT_OFF] = usNRegs * 2; ucMBFrame += MB_PDU_REQ_WRITE_MUL_VALUES_OFF; while( usNRegs > usRegIndex) { *ucMBFrame++ = pusDataBuffer[usRegIndex] >> 8; *ucMBFrame++ = pusDataBuffer[usRegIndex++] ; } vMBMasterSetPDUSndLength( MB_PDU_SIZE_MIN + MB_PDU_REQ_WRITE_MUL_SIZE_MIN + 2*usNRegs ); ( void ) xMBMasterPortEventPost( EV_MASTER_FRAME_SENT ); eErrStatus = eMBMasterWaitRequestFinish( ); } return eErrStatus; }
/** * This function will request write holding register. * * @param ucSndAddr slave address * @param usRegAddr register start address * @param usRegData register data to be written * @param lTimeOut timeout (-1 will waiting forever) * * @return error code */ eMBMasterReqErrCode eMBMasterReqWriteHoldingRegister( UCHAR ucSndAddr, USHORT usRegAddr, USHORT usRegData, LONG lTimeOut ) { UCHAR *ucMBFrame; eMBMasterReqErrCode eErrStatus = MB_MRE_NO_ERR; //chprintf((BaseSequentialStream *)&itm_port, "Resource Taken %s\n", xMBMasterRunResTake( lTimeOut ) ? "true" : "false"); if ( ucSndAddr > MB_MASTER_TOTAL_SLAVE_NUM ) eErrStatus = MB_MRE_ILL_ARG; else if ( xMBMasterRunResTake( lTimeOut ) == FALSE ) eErrStatus = MB_MRE_MASTER_BUSY; else { vMBMasterGetPDUSndBuf(&ucMBFrame); vMBMasterSetDestAddress(ucSndAddr); ucMBFrame[MB_PDU_FUNC_OFF] = MB_FUNC_WRITE_REGISTER; ucMBFrame[MB_PDU_REQ_WRITE_ADDR_OFF] = usRegAddr >> 8; ucMBFrame[MB_PDU_REQ_WRITE_ADDR_OFF + 1] = usRegAddr; ucMBFrame[MB_PDU_REQ_WRITE_VALUE_OFF] = usRegData >> 8; ucMBFrame[MB_PDU_REQ_WRITE_VALUE_OFF + 1] = usRegData ; vMBMasterSetPDUSndLength( MB_PDU_SIZE_MIN + MB_PDU_REQ_WRITE_SIZE ); ( void ) xMBMasterPortEventPost( EV_MASTER_FRAME_SENT ); eErrStatus = eMBMasterWaitRequestFinish( ); } return eErrStatus; }
eMBMasterReqErrCode eMBMasterReqWriteMultipleCoils(uint8_t ucSndAddr, uint16_t usCoilAddr, uint16_t usNCoils, uint8_t *pucDataBuffer, uint32_t lTimeOut) { uint8_t *ucMBFrame; uint16_t usRegIndex = 0; uint8_t ucByteCount; eMBMasterReqErrCode eErrStatus = MB_MRE_NO_ERR; if (ucSndAddr > CONFIG_MB_MASTER_TOTAL_SLAVE_NUM) { eErrStatus = MB_MRE_ILL_ARG; } else if (usNCoils > MB_PDU_REQ_WRITE_MUL_COILCNT_MAX) { eErrStatus = MB_MRE_ILL_ARG; } else if (xMBMasterRunResTake(lTimeOut) == false) { eErrStatus = MB_MRE_MASTER_BUSY; } else { vMBMasterGetPDUSndBuf(&ucMBFrame); vMBMasterSetDestAddress(ucSndAddr); ucMBFrame[MB_PDU_FUNC_OFF] = MB_FUNC_WRITE_MULTIPLE_COILS; ucMBFrame[MB_PDU_REQ_WRITE_MUL_ADDR_OFF] = usCoilAddr >> 8; ucMBFrame[MB_PDU_REQ_WRITE_MUL_ADDR_OFF + 1] = usCoilAddr; ucMBFrame[MB_PDU_REQ_WRITE_MUL_COILCNT_OFF] = usNCoils >> 8; ucMBFrame[MB_PDU_REQ_WRITE_MUL_COILCNT_OFF + 1] = usNCoils; if ((usNCoils & 0x0007) != 0) { ucByteCount = (uint8_t) (usNCoils / 8 + 1); } else { ucByteCount = (uint8_t) (usNCoils / 8); } ucMBFrame[MB_PDU_REQ_WRITE_MUL_BYTECNT_OFF] = ucByteCount; ucMBFrame += MB_PDU_REQ_WRITE_MUL_VALUES_OFF; while (ucByteCount > usRegIndex) { *ucMBFrame++ = pucDataBuffer[usRegIndex++]; } vMBMasterSetPDUSndLength(MB_PDU_SIZE_MIN + MB_PDU_REQ_WRITE_MUL_SIZE_MIN + ucByteCount); (void)xMBMasterPortEventPost(EV_MASTER_FRAME_SENT); eErrStatus = eMBMasterWaitRequestFinish(); } return eErrStatus; }
eMBMasterReqErrCode eMBMasterReqReadWriteMultipleHoldingRegister(uint8_t ucSndAddr, uint16_t usReadRegAddr, uint16_t usNReadRegs, uint16_t *pusDataBuffer, uint16_t usWriteRegAddr, uint16_t usNWriteRegs, uint32_t lTimeOut) { uint8_t *ucMBFrame; uint16_t usRegIndex = 0; eMBMasterReqErrCode eErrStatus = MB_MRE_NO_ERR; if (ucSndAddr > CONFIG_MB_MASTER_TOTAL_SLAVE_NUM) { eErrStatus = MB_MRE_ILL_ARG; } else if (xMBMasterRunResTake(lTimeOut) == false) { eErrStatus = MB_MRE_MASTER_BUSY; } else { vMBMasterGetPDUSndBuf(&ucMBFrame); vMBMasterSetDestAddress(ucSndAddr); ucMBFrame[MB_PDU_FUNC_OFF] = MB_FUNC_READWRITE_MULTIPLE_REGISTERS; ucMBFrame[MB_PDU_REQ_READWRITE_READ_ADDR_OFF] = usReadRegAddr >> 8; ucMBFrame[MB_PDU_REQ_READWRITE_READ_ADDR_OFF + 1] = usReadRegAddr; ucMBFrame[MB_PDU_REQ_READWRITE_READ_REGCNT_OFF] = usNReadRegs >> 8; ucMBFrame[MB_PDU_REQ_READWRITE_READ_REGCNT_OFF + 1] = usNReadRegs; ucMBFrame[MB_PDU_REQ_READWRITE_WRITE_ADDR_OFF] = usWriteRegAddr >> 8; ucMBFrame[MB_PDU_REQ_READWRITE_WRITE_ADDR_OFF + 1] = usWriteRegAddr; ucMBFrame[MB_PDU_REQ_READWRITE_WRITE_REGCNT_OFF] = usNWriteRegs >> 8; ucMBFrame[MB_PDU_REQ_READWRITE_WRITE_REGCNT_OFF + 1] = usNWriteRegs; ucMBFrame[MB_PDU_REQ_READWRITE_WRITE_BYTECNT_OFF] = usNWriteRegs * 2; ucMBFrame += MB_PDU_REQ_READWRITE_WRITE_VALUES_OFF; while (usNWriteRegs > usRegIndex) { *ucMBFrame++ = pusDataBuffer[usRegIndex] >> 8; *ucMBFrame++ = pusDataBuffer[usRegIndex++]; } vMBMasterSetPDUSndLength(MB_PDU_SIZE_MIN + MB_PDU_REQ_READWRITE_SIZE_MIN + 2 * usNWriteRegs); (void)xMBMasterPortEventPost(EV_MASTER_FRAME_SENT); eErrStatus = eMBMasterWaitRequestFinish(); } return eErrStatus; }
eMBMasterReqErrCode eMBMasterReqWriteCoil(uint8_t ucSndAddr, uint16_t usCoilAddr, uint16_t usCoilData, uint32_t lTimeOut) { uint8_t *ucMBFrame; eMBMasterReqErrCode eErrStatus = MB_MRE_NO_ERR; if (ucSndAddr > CONFIG_MB_MASTER_TOTAL_SLAVE_NUM) { eErrStatus = MB_MRE_ILL_ARG; } else if ((usCoilData != 0xFF00) && (usCoilData != 0x0000)) { eErrStatus = MB_MRE_ILL_ARG; } else if (xMBMasterRunResTake(lTimeOut) == false) { eErrStatus = MB_MRE_MASTER_BUSY; } else { vMBMasterGetPDUSndBuf(&ucMBFrame); vMBMasterSetDestAddress(ucSndAddr); ucMBFrame[MB_PDU_FUNC_OFF] = MB_FUNC_WRITE_SINGLE_COIL; ucMBFrame[MB_PDU_REQ_WRITE_ADDR_OFF] = usCoilAddr >> 8; ucMBFrame[MB_PDU_REQ_WRITE_ADDR_OFF + 1] = usCoilAddr; ucMBFrame[MB_PDU_REQ_WRITE_VALUE_OFF] = usCoilData >> 8; ucMBFrame[MB_PDU_REQ_WRITE_VALUE_OFF + 1] = usCoilData; vMBMasterSetPDUSndLength(MB_PDU_SIZE_MIN + MB_PDU_REQ_WRITE_SIZE); (void)xMBMasterPortEventPost(EV_MASTER_FRAME_SENT); eErrStatus = eMBMasterWaitRequestFinish(); } return eErrStatus; }
/** * This function will request read coil. * * @param ucSndAddr salve address * @param usCoilAddr coil start address * @param usNCoils coil total number * @param lTimeOut timeout (-1 will waiting forever) * * @return error code */ eMBMasterReqErrCode eMBMasterReqReadCoils( UCHAR ucSndAddr, USHORT usCoilAddr, USHORT usNCoils ,LONG lTimeOut ) { UCHAR *ucMBFrame; eMBMasterReqErrCode eErrStatus = MB_MRE_NO_ERR; if ( ucSndAddr > MB_MASTER_TOTAL_SLAVE_NUM ) eErrStatus = MB_MRE_ILL_ARG; //else if ( xMBMasterRunResTake( lTimeOut ) == FALSE ) eErrStatus = MB_MRE_MASTER_BUSY; else { vMBMasterGetPDUSndBuf(&ucMBFrame); vMBMasterSetDestAddress(ucSndAddr); ucMBFrame[MB_PDU_FUNC_OFF] = MB_FUNC_READ_COILS; ucMBFrame[MB_PDU_REQ_READ_ADDR_OFF] = usCoilAddr >> 8; ucMBFrame[MB_PDU_REQ_READ_ADDR_OFF + 1] = usCoilAddr; ucMBFrame[MB_PDU_REQ_READ_COILCNT_OFF ] = usNCoils >> 8; ucMBFrame[MB_PDU_REQ_READ_COILCNT_OFF + 1] = usNCoils; vMBMasterSetPDUSndLength( MB_PDU_SIZE_MIN + MB_PDU_REQ_READ_SIZE ); ( void ) xMBMasterPortEventPost( EV_MASTER_FRAME_SENT ); eErrStatus = eMBMasterWaitRequestFinish( ); } return eErrStatus; }