void __init pplus_set_VIA_IDE_legacy(void)
{
unsigned short vend, dev;
early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
if ((vend == PCI_VENDOR_ID_VIA) &&
(dev == PCI_DEVICE_ID_VIA_82C586_1)) {
unsigned char temp;
/* put back original "standard" port base addresses */
early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
PCI_BASE_ADDRESS_0, 0x1f1);
early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
PCI_BASE_ADDRESS_1, 0x3f5);
early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
PCI_BASE_ADDRESS_2, 0x171);
early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
PCI_BASE_ADDRESS_3, 0x375);
early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
PCI_BASE_ADDRESS_4, 0xcc01);
/* put into legacy mode */
early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
&temp);
temp &= ~0x05;
early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
temp);
}
}
void __init pplus_pcibios_fixup(void)
{
unsigned char reg;
unsigned short devid;
unsigned char base_mod;
printk(KERN_INFO "Setting PCI interrupts for a \"%s\"\n",
Motherboard_map_name);
/* Setup the Winbond or Via PIB */
pplus_pib_init();
/* Set up floppy in PS/2 mode */
outb(0x09, SIO_CONFIG_RA);
reg = inb(SIO_CONFIG_RD);
reg = (reg & 0x3F) | 0x40;
outb(reg, SIO_CONFIG_RD);
outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
/* This is a hack. If this is a 2300 or 2400 mot board then there is
* no keyboard controller and we have to indicate that.
*/
early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
base_mod = inb(MOTOROLA_BASETYPE_REG);
if ((devid == PCI_DEVICE_ID_MOTOROLA_HAWK) ||
(base_mod == 0xF9) || (base_mod == 0xFA) || (base_mod == 0xE1))
prep_keybd_present = 0;
}
int __init raven_init(void)
{
unsigned short devid;
unsigned char base_mod;
/* set the MPIC base address */
early_write_config_dword(0, 0, 0, PCI_BASE_ADDRESS_1, 0x3cfc0000);
pplus_mpic_init(PREP_ISA_MEM_BASE);
OpenPIC_InitSenses = pplus_openpic_initsenses;
OpenPIC_NumInitSenses = sizeof(pplus_openpic_initsenses);
ppc_md.get_irq = openpic_get_irq;
/* This is a hack. If this is a 2300 or 2400 mot board then there is
* no keyboard controller and we have to indicate that.
*/
early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
base_mod = inb(MOTOROLA_BASETYPE_REG);
if ((devid == PCI_DEVICE_ID_MOTOROLA_HAWK) ||
(base_mod == 0xF9) ||
(base_mod == 0xFA) || (base_mod == 0xE1))
prep_keybd_present = 0;
return 1;
}
static void __init
mpc85xx_setup_pci1(struct pci_controller *hose)
{
volatile struct ccsr_pci *pci;
volatile struct ccsr_guts *guts;
unsigned short temps;
bd_t *binfo = (bd_t *) __res;
pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET,
MPC85xx_PCI1_SIZE);
guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET,
MPC85xx_GUTS_SIZE);
early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
if (guts->pordevsr & PORDEVSR_PCI) {
early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
} else {
/* PCI-X init */
temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps);
}
/* Disable all windows (except powar0 since its ignored) */
pci->powar1 = 0;
pci->powar2 = 0;
pci->powar3 = 0;
pci->powar4 = 0;
pci->piwar1 = 0;
pci->piwar2 = 0;
pci->piwar3 = 0;
/* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI1_LOWER_MEM */
pci->potar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
pci->potear1 = 0x00000000;
pci->powbar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
/* Enable, Mem R/W */
pci->powar1 = 0x80044000 |
(__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);
/* Setup outbound IO windows @ MPC85XX_PCI1_IO_BASE */
pci->potar2 = (MPC85XX_PCI1_LOWER_IO >> 12) & 0x000fffff;
pci->potear2 = 0x00000000;
pci->powbar2 = (MPC85XX_PCI1_IO_BASE >> 12) & 0x000fffff;
/* Enable, IO R/W */
pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);
/* Setup 2G inbound Memory Window @ 0 */
pci->pitar1 = 0x00000000;
pci->piwbar1 = 0x00000000;
pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local
Mem, Snoop R/W, 2G */
}
void __init
mpc83xx_setup_pci2(struct pci_controller *hose)
{
u16 reg16;
volatile immr_pcictrl_t * pci_ctrl;
volatile immr_ios_t * ios;
bd_t *binfo = (bd_t *) __res;
pci_ctrl = ioremap(binfo->bi_immr_base + 0x8600, sizeof(immr_pcictrl_t));
ios = ioremap(binfo->bi_immr_base + 0x8400, sizeof(immr_ios_t));
/*
* Configure PCI Outbound Translation Windows
*/
ios->potar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POTAR_TA_MASK;
ios->pobar3 = (MPC83xx_PCI2_LOWER_MEM >> 12) & POBAR_BA_MASK;
ios->pocmr3 = POCMR_EN | POCMR_DST |
(((0xffffffff - (MPC83xx_PCI2_UPPER_MEM -
MPC83xx_PCI2_LOWER_MEM)) >> 12) & POCMR_CM_MASK);
/* mapped to PCI2 IO space */
ios->potar4 = (MPC83xx_PCI2_LOWER_IO >> 12) & POTAR_TA_MASK;
ios->pobar4 = (MPC83xx_PCI2_IO_BASE >> 12) & POBAR_BA_MASK;
ios->pocmr4 = POCMR_EN | POCMR_DST | POCMR_IO |
(((0xffffffff - (MPC83xx_PCI2_UPPER_IO -
MPC83xx_PCI2_LOWER_IO)) >> 12) & POCMR_CM_MASK);
/*
* Configure PCI Inbound Translation Windows
*/
pci_ctrl->pitar1 = 0x0;
pci_ctrl->pibar1 = 0x0;
pci_ctrl->piebar1 = 0x0;
pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
/*
* Release PCI RST signal
*/
pci_ctrl->gcr = 0;
udelay(2000);
pci_ctrl->gcr = 1;
udelay(2000);
reg16 = 0xff;
early_read_config_word(hose, hose->first_busno, 0, PCI_COMMAND, ®16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
early_write_config_word(hose, hose->first_busno, 0, PCI_COMMAND, reg16);
/*
* Clear non-reserved bits in status register.
*/
early_write_config_word(hose, hose->first_busno, 0, PCI_STATUS, 0xffff);
early_write_config_byte(hose, hose->first_busno, 0, PCI_LATENCY_TIMER, 0x80);
iounmap(pci_ctrl);
iounmap(ios);
}
void pplus_set_VIA_IDE_native(void)
{
unsigned short vend, dev;
early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
if ((vend == PCI_VENDOR_ID_VIA) &&
(dev == PCI_DEVICE_ID_VIA_82C586_1)) {
unsigned char temp;
/* put into native mode */
early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
&temp);
temp |= 0x05;
early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
temp);
}
}
int __init pci_is_66mhz_capable(struct pci_channel *hose,
int top_bus, int current_bus)
{
u32 pci_devfn;
unsigned short vid;
int cap66 = -1;
u16 stat;
printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n");
for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
if (PCI_FUNC(pci_devfn))
continue;
if (early_read_config_word(hose, top_bus, current_bus,
pci_devfn, PCI_VENDOR_ID, &vid) !=
PCIBIOS_SUCCESSFUL)
continue;
if (vid == 0xffff)
continue;
/* check 66MHz capability */
if (cap66 < 0)
cap66 = 1;
if (cap66) {
early_read_config_word(hose, top_bus, current_bus,
pci_devfn, PCI_STATUS, &stat);
if (!(stat & PCI_STATUS_66MHZ)) {
printk(KERN_DEBUG
"PCI: %02x:%02x not 66MHz capable.\n",
current_bus, pci_devfn);
cap66 = 0;
break;
}
}
}
return cap66 > 0;
}
static void __init
mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 lower_mem,
u32 upper_mem, u32 io_base)
{
volatile struct ccsr_pcie *pcie;
u16 cmd;
bd_t *binfo = (bd_t *) __res;
pcie = ioremap(binfo->bi_immr_base + pcie_offset,
MPC86xx_PCIE_SIZE);
early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
/* Disable all windows (except pcieowar0 since its ignored) */
pcie->pcieowar1 = 0;
pcie->pcieowar2 = 0;
pcie->pcieowar3 = 0;
pcie->pcieowar4 = 0;
pcie->pcieiwar1 = 0;
pcie->pcieiwar1 = 0;
pcie->pcieiwar2 = 0;
pcie->pcieiwar3 = 0;
/* Setup Phys:PCIE 1:1 outbound mem window @ MPC86XX_PCIEn_LOWER_MEM */
pcie->pcieotar1 = (lower_mem >> 12) & 0x000fffff;
pcie->pcieotear1 = 0x00000000;
pcie->pcieowbar1 = (lower_mem >> 12) & 0x000fffff;
/* Enable, Mem R/W */
pcie->pcieowar1 = 0x80044000 |
(__ilog2(upper_mem - lower_mem + 1) - 1);
/* Setup outbound IO windows @ MPC86XX_PCIEn_IO_BASE */
pcie->pcieotar2 = (MPC86XX_PCIE_LOWER_IO >> 12) & 0x000fffff;
pcie->pcieotear2 = 0x00000000;
pcie->pcieowbar2 = (io_base >> 12) & 0x000fffff;
/* Enable, IO R/W */
pcie->pcieowar2 = 0x80088000 | (__ilog2(MPC86XX_PCIE_IO_SIZE) - 1);
/* Setup 2G inbound Memory Window @ 0 */
pcie->pcieitar1 = 0x00000000;
pcie->pcieiwbar1 = 0x00000000;
/* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
pcie->pcieiwar1 = 0xa0f5501e;
}
static void __init
mpc85xx_setup_pci2(struct pci_controller *hose)
{
volatile struct ccsr_pci *pci;
unsigned short temps;
bd_t *binfo = (bd_t *) __res;
pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI2_OFFSET,
MPC85xx_PCI2_SIZE);
early_read_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, &temps);
temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
early_write_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, temps);
early_write_config_byte(hose, hose->bus_offset, 0, PCI_LATENCY_TIMER, 0x80);
/* Disable all windows (except powar0 since its ignored) */
pci->powar1 = 0;
pci->powar2 = 0;
pci->powar3 = 0;
pci->powar4 = 0;
pci->piwar1 = 0;
pci->piwar2 = 0;
pci->piwar3 = 0;
/* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI2_LOWER_MEM */
pci->potar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
pci->potear1 = 0x00000000;
pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
/* Enable, Mem R/W */
pci->powar1 = 0x80044000 |
(__ilog2(MPC85XX_PCI2_UPPER_MEM - MPC85XX_PCI2_LOWER_MEM + 1) - 1);
/* Setup outbound IO windows @ MPC85XX_PCI2_IO_BASE */
pci->potar2 = (MPC85XX_PCI2_LOWER_IO >> 12) & 0x000fffff;
pci->potear2 = 0x00000000;
pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff;
/* Enable, IO R/W */
pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI2_IO_SIZE) - 1);
/* Setup 2G inbound Memory Window @ 0 */
pci->pitar1 = 0x00000000;
pci->piwbar1 = 0x00000000;
pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local
Mem, Snoop R/W, 2G */
}
int __init
katana_get_proc_num(void)
{
u16 val;
u8 save_exclude;
static int proc = -1;
static u8 first_time = 1;
if (first_time) {
if (katana_id != KATANA_ID_3750)
proc = 0;
else {
save_exclude = mv64x60_pci_exclude_bridge;
mv64x60_pci_exclude_bridge = 0;
early_read_config_word(bh.hose_b, 0,
PCI_DEVFN(0,0), PCI_DEVICE_ID, &val);
mv64x60_pci_exclude_bridge = save_exclude;
switch(val) {
case PCI_DEVICE_ID_KATANA_3750_PROC0:
proc = 0;
break;
case PCI_DEVICE_ID_KATANA_3750_PROC1:
proc = 1;
break;
case PCI_DEVICE_ID_KATANA_3750_PROC2:
proc = 2;
break;
default:
printk(KERN_ERR "Bogus Device ID\n");
}
}
first_time = 0;
}
return proc;
}
static int __init mvme5100_add_bridge(struct device_node *dev)
{
const int *bus_range;
int len;
struct pci_controller *hose;
unsigned short devid;
pr_info("Adding PCI host bridge %s\n", dev->full_name);
bus_range = of_get_property(dev, "bus-range", &len);
hose = pcibios_alloc_controller(dev);
if (hose == NULL)
return -ENOMEM;
hose->first_busno = bus_range ? bus_range[0] : 0;
hose->last_busno = bus_range ? bus_range[1] : 0xff;
setup_indirect_pci(hose, 0xfe000cf8, 0xfe000cfc, 0);
pci_process_bridge_OF_ranges(hose, dev, 1);
early_read_config_word(hose, 0, 0, PCI_DEVICE_ID, &devid);
if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK) {
pr_err("HAWK PHB not present?\n");
return 0;
}
early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase);
if (pci_membase == 0) {
pr_err("HAWK PHB mibar not correctly set?\n");
return 0;
}
pr_info("mvme5100_pic_init: pci_membase: %x\n", pci_membase);
return 0;
}
static void __init
katana_setup_bridge(void)
{
struct pci_controller hose;
struct mv64x60_setup_info si;
void __iomem *vaddr;
int i;
u32 v;
u16 val, type;
u8 save_exclude;
/*
* Some versions of the Katana firmware mistakenly change the vendor
* & device id fields in the bridge's pci device (visible via pci
* config accesses). This breaks mv64x60_init() because those values
* are used to identify the type of bridge that's there. Artesyn
* claims that the subsystem vendor/device id's will have the correct
* Marvell values so this code puts back the correct values from there.
*/
memset(&hose, 0, sizeof(hose));
vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE);
setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR,
vaddr + MV64x60_PCI0_CONFIG_DATA);
save_exclude = mv64x60_pci_exclude_bridge;
mv64x60_pci_exclude_bridge = 0;
early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
if (val != PCI_VENDOR_ID_MARVELL) {
early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
PCI_SUBSYSTEM_VENDOR_ID, &val);
early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
PCI_VENDOR_ID, val);
early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
PCI_SUBSYSTEM_ID, &val);
early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
PCI_DEVICE_ID, val);
}
/*
* While we're in here, set the hotswap register correctly.
* Turn off blue LED; mask ENUM#, clear insertion & extraction bits.
*/
early_read_config_dword(&hose, 0, PCI_DEVFN(0, 0),
MV64360_PCICFG_CPCI_HOTSWAP, &v);
v &= ~(1<<19);
v |= ((1<<17) | (1<<22) | (1<<23));
early_write_config_dword(&hose, 0, PCI_DEVFN(0, 0),
MV64360_PCICFG_CPCI_HOTSWAP, v);
/* While we're at it, grab the bridge type for later */
early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &type);
mv64x60_pci_exclude_bridge = save_exclude;
iounmap(vaddr);
memset(&si, 0, sizeof(si));
si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
si.pci_1.enable_bus = 1;
si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
si.pci_1.pci_io.pci_base_hi = 0;
si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
si.pci_1.pci_cmd_bits = 0;
si.pci_1.latency_timer = 0x80;
for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
#if defined(CONFIG_NOT_COHERENT_CACHE)
si.cpu_prot_options[i] = 0;
si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
si.pci_1.acc_cntl_options[i] =
MV64360_PCI_ACC_CNTL_SNOOP_NONE |
MV64360_PCI_ACC_CNTL_SWAP_NONE |
MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
#else
si.cpu_prot_options[i] = 0;
si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;
si.pci_1.acc_cntl_options[i] =
MV64360_PCI_ACC_CNTL_SNOOP_WB |
MV64360_PCI_ACC_CNTL_SWAP_NONE |
MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
((type == PCI_DEVICE_ID_MARVELL_MV64360) ?
MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES :
MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES);
#endif
}
/* Lookup PCI host bridges */
if (mv64x60_init(&bh, &si))
printk(KERN_WARNING "Bridge initialization failed.\n");
pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = katana_map_irq;
ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
mv64x60_set_bus(&bh, 1, 0);
bh.hose_b->first_busno = 0;
bh.hose_b->last_busno = 0xff;
/*
* Need to access hotswap reg which is in the pci config area of the
* bridge's hose 0. Note that pcibios_alloc_controller() can't be used
* to alloc hose_a b/c that would make hose 0 known to the generic
* pci code which we don't want.
*/
bh.hose_a = &katana_hose_a;
setup_indirect_pci_nomap(bh.hose_a,
bh.v_base + MV64x60_PCI0_CONFIG_ADDR,
bh.v_base + MV64x60_PCI0_CONFIG_DATA);
}
void __init pplus_set_board_type(void)
{
unsigned char cpu_type;
unsigned char base_mod;
int entry;
unsigned short devid;
unsigned long *ProcInfo = NULL;
cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0;
base_mod = inb(MOTOROLA_BASETYPE_REG);
early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
for (entry = 0; mot_info[entry].cpu_type != 0; entry++) {
/* Check for Hawk chip */
if (mot_info[entry].cpu_type & 0x200) {
if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK)
continue;
} else {
/* store the system config register for later use. */
ProcInfo =
(unsigned long *)ioremap(PPLUS_SYS_CONFIG_REG, 4);
/* Check non hawk boards */
if ((mot_info[entry].cpu_type & 0xff) != cpu_type)
continue;
if (mot_info[entry].base_type == 0) {
mot_entry = entry;
break;
}
if (mot_info[entry].base_type != base_mod)
continue;
}
if (!(mot_info[entry].max_cpu & 0x80)) {
mot_entry = entry;
break;
}
/* processor 1 not present and max processor zero indicated */
if ((*ProcInfo & MOT_PROC2_BIT)
&& !(mot_info[entry].max_cpu & 0x7f)) {
mot_entry = entry;
break;
}
/* processor 1 present and max processor zero indicated */
if (!(*ProcInfo & MOT_PROC2_BIT)
&& (mot_info[entry].max_cpu & 0x7f)) {
mot_entry = entry;
break;
}
/* Indicate to system if this is a multiprocessor board */
if (!(*ProcInfo & MOT_PROC2_BIT))
mot_multi = 1;
}
if (mot_entry == -1)
/* No particular cpu type found - assume Mesquite (MCP750) */
mot_entry = 1;
Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name;
ppc_md.pci_map_irq = mot_info[mot_entry].map_irq;
}
static void __init
katana_setup_bridge(void)
{
struct pci_controller hose;
struct mv64x60_setup_info si;
void __iomem *vaddr;
int i;
u16 val;
u8 save_exclude;
/*
* Some versions of the Katana firmware mistakenly change the vendor
* & device id fields in the bridge's pci device (visible via pci
* config accesses). This breaks mv64x60_init() because those values
* are used to identify the type of bridge that's there. Artesyn
* claims that the subsystem vendor/device id's will have the correct
* Marvell values so this code puts back the correct values from there.
*/
memset(&hose, 0, sizeof(hose));
vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE);
setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR,
vaddr + MV64x60_PCI0_CONFIG_DATA);
save_exclude = mv64x60_pci_exclude_bridge;
mv64x60_pci_exclude_bridge = 0;
early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
if (val != PCI_VENDOR_ID_MARVELL) {
early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
PCI_SUBSYSTEM_VENDOR_ID, &val);
early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
PCI_VENDOR_ID, val);
early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
PCI_SUBSYSTEM_ID, &val);
early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
PCI_DEVICE_ID, val);
}
mv64x60_pci_exclude_bridge = save_exclude;
iounmap(vaddr);
memset(&si, 0, sizeof(si));
si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
si.pci_1.enable_bus = 1;
si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
si.pci_1.pci_io.pci_base_hi = 0;
si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
si.pci_1.pci_cmd_bits = 0;
si.pci_1.latency_timer = 0x80;
for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
#if defined(CONFIG_NOT_COHERENT_CACHE)
si.cpu_prot_options[i] = 0;
si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
si.pci_1.acc_cntl_options[i] =
MV64360_PCI_ACC_CNTL_SNOOP_NONE |
MV64360_PCI_ACC_CNTL_SWAP_NONE |
MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
#else
si.cpu_prot_options[i] = 0;
si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
si.pci_1.acc_cntl_options[i] =
MV64360_PCI_ACC_CNTL_SNOOP_WB |
MV64360_PCI_ACC_CNTL_SWAP_NONE |
MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
#endif
}
/* Lookup PCI host bridges */
if (mv64x60_init(&bh, &si))
printk(KERN_WARNING "Bridge initialization failed.\n");
pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
ppc_md.pci_swizzle = common_swizzle;
ppc_md.pci_map_irq = katana_map_irq;
ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
mv64x60_set_bus(&bh, 1, 0);
bh.hose_b->first_busno = 0;
bh.hose_b->last_busno = 0xff;
}
