static void __init
chestnut_early_serial_map(void)
{
struct uart_port port;
/* Setup serial port access */
memset(&port, 0, sizeof(port));
port.uartclk = BASE_BAUD * 16;
port.irq = UART0_INT;
port.flags = STD_COM_FLAGS | UPF_IOREMAP;
port.iotype = UPIO_MEM;
port.mapbase = CHESTNUT_UART0_IO_BASE;
port.regshift = 0;
if (early_serial_setup(&port) != 0)
printk("Early serial init of port 0 failed\n");
/* Assume early_serial_setup() doesn't modify serial_req */
port.line = 1;
port.irq = UART1_INT;
port.mapbase = CHESTNUT_UART1_IO_BASE;
if (early_serial_setup(&port) != 0)
printk("Early serial init of port 1 failed\n");
}
static void __init ppc7d_early_serial_map(void)
{
#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
#elif defined(CONFIG_SERIAL_8250)
struct uart_port serial_req;
/* Setup serial port access */
memset(&serial_req, 0, sizeof(serial_req));
serial_req.uartclk = UART_CLK;
serial_req.irq = 4;
serial_req.flags = STD_COM_FLAGS;
serial_req.iotype = UPIO_MEM;
serial_req.membase = (u_char *) PPC7D_SERIAL_0;
gen550_init(0, &serial_req);
if (early_serial_setup(&serial_req) != 0)
printk(KERN_ERR "Early serial init of port 0 failed\n");
/* Assume early_serial_setup() doesn't modify serial_req */
serial_req.line = 1;
serial_req.irq = 3;
serial_req.membase = (u_char *) PPC7D_SERIAL_1;
gen550_init(1, &serial_req);
if (early_serial_setup(&serial_req) != 0)
printk(KERN_ERR "Early serial init of port 1 failed\n");
#else
#error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX
#endif
}
static void __init
sbc8560_early_serial_map(void)
{
struct uart_port uart_req;
/* Setup serial port access */
memset(&uart_req, 0, sizeof (uart_req));
uart_req.irq = MPC85xx_IRQ_EXT9;
uart_req.flags = STD_COM_FLAGS;
uart_req.uartclk = BASE_BAUD * 16;
uart_req.iotype = UPIO_MEM;
uart_req.mapbase = UARTA_ADDR;
uart_req.membase = ioremap(uart_req.mapbase, MPC85xx_UART0_SIZE);
uart_req.type = PORT_16650;
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
gen550_init(0, &uart_req);
#endif
if (early_serial_setup(&uart_req) != 0)
printk("Early serial init of port 0 failed\n");
/* Assume early_serial_setup() doesn't modify uart_req */
uart_req.line = 1;
uart_req.mapbase = UARTB_ADDR;
uart_req.membase = ioremap(uart_req.mapbase, MPC85xx_UART1_SIZE);
uart_req.irq = MPC85xx_IRQ_EXT10;
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
gen550_init(1, &uart_req);
#endif
if (early_serial_setup(&uart_req) != 0)
printk("Early serial init of port 1 failed\n");
}
static void __init jz_serial_setup(void)
{
#ifdef CONFIG_SERIAL_8250
struct uart_port s;
REG8(UART0_FCR) |= UARTFCR_UUE; /* enable UART module */
memset(&s, 0, sizeof(s));
s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
s.iotype = SERIAL_IO_MEM;
s.regshift = 2;
s.uartclk = jz4740_clock_bdata.ext_rate;
s.line = 0;
s.membase = (u8 *)UART0_BASE;
s.irq = JZ_IRQ_UART0;
if (early_serial_setup(&s) != 0) {
printk(KERN_ERR "Serial ttyS0 setup failed!\n");
}
s.line = 1;
s.membase = (u8 *)UART1_BASE;
s.irq = JZ_IRQ_UART1;
if (early_serial_setup(&s) != 0) {
printk(KERN_ERR "Serial ttyS1 setup failed!\n");
}
#endif
}
static void __init ixdp2x01_map_io(void)
{
ixp2000_map_io();
iotable_init(&ixdp2x01_io_desc, 1);
early_serial_setup(&ixdp2x01_serial_ports[0]);
early_serial_setup(&ixdp2x01_serial_ports[1]);
}
void __init
mpc83xx_early_serial_map(void)
{
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_8250)
struct uart_port serial_req;
#endif
struct plat_serial8250_port *pdata;
bd_t *binfo = (bd_t *) __res;
pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC83xx_DUART);
/* Setup serial port access */
pdata[0].uartclk = binfo->bi_busfreq;
pdata[0].mapbase += binfo->bi_immr_base;
pdata[0].membase = ioremap(pdata[0].mapbase, 0x100);
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_8250)
memset(&serial_req, 0, sizeof (serial_req));
serial_req.iotype = SERIAL_IO_MEM;
serial_req.mapbase = pdata[0].mapbase;
serial_req.membase = pdata[0].membase;
serial_req.regshift = 0;
serial_req.uartclk = pdata[0].uartclk;
serial_req.irq = pdata[0].irq;
serial_req.line = pdata[0].line;
serial_req.flags = pdata[0].flags;
if (early_serial_setup(&serial_req) != 0)
printk("Early serial init of port 0 failed\n");
#if defined(CONFIG_SERIAL_TEXT_DEBUG)
gen550_init(0, &serial_req);
#endif
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(0, &serial_req);
#endif
#endif
pdata[1].uartclk = binfo->bi_busfreq;
pdata[1].mapbase += binfo->bi_immr_base;
pdata[1].membase = ioremap(pdata[1].mapbase, 0x100);
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_8250)
/* Assume gen550_init() doesn't modify serial_req */
serial_req.mapbase = pdata[1].mapbase;
serial_req.membase = pdata[1].membase;
serial_req.line = pdata[1].line;
if (early_serial_setup(&serial_req) != 0)
printk("Early serial init of port 1 failed\n");
#if defined(CONFIG_SERIAL_TEXT_DEBUG)
gen550_init(1, &serial_req);
#endif
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(1, &serial_req);
#endif
#endif
}
void __init serial_init(void)
{
#ifdef CONFIG_SERIAL_8250
struct uart_port s, u, k;
memset(&s, 0, sizeof(s));
s.type = PORT_16550;
s.iobase = 0xFD201300; //virtual RIU_BASE = 0xFD000000
s.irq = E_IRQ_UART0;
#ifdef CONFIG_MSTAR_ARM_BD_FPGA
s.uartclk = 12000000; //FPGA
#elif defined(CONFIG_MSTAR_ARM_BD_GENERIC)
s.uartclk = 123000000; //real chip
#endif
s.iotype = 0;
s.regshift = 0;
s.fifosize = 16 ; // use the 8 byte depth FIFO well
s.line = 0;
if (early_serial_setup(&s) != 0) {
printk(KERN_ERR "Serial(0) setup failed!\n");
}
memset(&u, 0, sizeof(u));
u.type = PORT_16550;
u.iobase = 0xFD220C00;
u.irq = E_IRQEXPL_UART1;
u.uartclk = 108000000;
u.iotype = 0;
u.regshift = 0;
u.fifosize = 16 ; // use the 8 byte depth FIFO well
u.line = 1;
if (early_serial_setup(&u) != 0) {
printk(KERN_ERR "Serial piu_uart1 setup failed!\n");
}
memset(&k, 0, sizeof(k));
k.type = PORT_16550;
k.iobase = 0xFD220D00;
k.irq = E_IRQEXPH_UART2MCU;
k.uartclk = 123000000;
k.iotype = 0;
k.regshift = 0;
k.fifosize = 16 ; // use the 8 byte depth FIFO well
k.line = 2;
if (early_serial_setup(&k) != 0) {
printk(KERN_ERR "Serial fuart setup failed!\n");
}
#endif
}
static void __init
ebony_early_serial_map(void)
{
struct uart_port port;
/* Setup ioremapped serial port access */
memset(&port, 0, sizeof(port));
port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
port.irq = 0;
port.uartclk = clocks.uart0;
port.regshift = 0;
port.iotype = SERIAL_IO_MEM;
port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
port.line = 0;
#ifdef CONFIG_SERIAL_8250
if (early_serial_setup(&port) != 0)
printk("Early serial init of port 0 failed\n");
#endif
#ifdef CONFIG_SERIAL_TEXT_DEBUG
/* Configure debug serial access */
gen550_init(0, &port);
#endif
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(0, &port);
#endif
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_8250)
/* Purge TLB entry added in head_44x.S for early serial access */
_tlbie(UART0_IO_BASE);
#endif
port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
port.irq = 1;
port.uartclk = clocks.uart1;
port.line = 1;
#ifdef CONFIG_SERIAL_8250
if (early_serial_setup(&port) != 1)
printk("Early serial init of port 1 failed\n");
#endif
#ifdef CONFIG_SERIAL_TEXT_DEBUG
/* Configure debug serial access */
gen550_init(1, &port);
#endif
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(1, &port);
#endif
}
static void __init ixdp2x01_map_io(void)
{
ixp2000_map_io();
iotable_init(&ixdp2x01_io_desc, 1);
early_serial_setup(&ixdp2x01_serial_ports[0]);
early_serial_setup(&ixdp2x01_serial_ports[1]);
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(0, &ixdp2x01_serial_ports[0]);
kgdb8250_add_port(1, &ixdp2x01_serial_ports[1]);
#endif
}
void __init serial_init(void)
{
#ifdef CONFIG_SERIAL_8250
struct uart_port s;
struct uart_port u1;
memset(&s, 0, sizeof(s));
s.type = PORT_16550;
s.iobase = 0xFD201300; //virtual RIU_BASE = 0xFD000000
s.membase = (unsigned char __iomem *) 0xFD201300;
s.mapbase = 0xFD201300;
s.irq = E_IRQ_UART0;
#ifdef CONFIG_MSTAR_EAGLE_BD_FPGA
s.uartclk = 12000000; //FPGA
#else
s.uartclk = 123000000; //real chip
#endif
s.iotype = 0;
s.regshift = 0;
s.fifosize = 16 ; // use the 8 byte depth FIFO well
s.line = 0;
if (early_serial_setup(&s) != 0) {
printk(KERN_ERR "Serial(0) setup failed!\n");
}
//UART1
memset(&u1, 0, sizeof(u1));
u1.type = PORT_16550;
u1.iobase = 0xFD220c00; //virtual RIU_BASE = 0xFD000000
u1.membase = (unsigned char __iomem *) 0xFD220c00;
u1.mapbase = 0xFD220c00;
u1.irq = E_IRQEXPL_UART1;
u1.uartclk = 123000000; //real chip
u1.iotype = 0;
u1.regshift = 0;
u1.fifosize = 16 ; // use the 8 byte depth FIFO well
u1.line = 1;
if (early_serial_setup(&u1) != 0) {
printk(KERN_ERR "Serial(0) uart1 setup failed!\n");
}
#endif
}
static void __init
luan_early_serial_map(void)
{
struct uart_port port;
/* Setup ioremapped serial port access */
memset(&port, 0, sizeof(port));
port.membase = ioremap64(PPC440SP_UART0_ADDR, 8);
port.irq = UART0_INT;
port.uartclk = clocks.uart0;
port.regshift = 0;
port.iotype = SERIAL_IO_MEM;
port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 0 failed\n");
}
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(0, &port);
#endif
port.membase = ioremap64(PPC440SP_UART1_ADDR, 8);
port.irq = UART1_INT;
port.uartclk = clocks.uart1;
port.line = 1;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 1 failed\n");
}
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(1, &port);
#endif
/* Enable UART2 */
SDR_WRITE(DCRN_SDR_PFC1, SDR_READ(DCRN_SDR_PFC1) | 0x01000000);
port.membase = ioremap64(PPC440SP_UART2_ADDR, 8);
port.irq = UART2_INT;
port.uartclk = clocks.uart2;
port.line = 2;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 2 failed\n");
}
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(2, &port);
#endif
}
static int __init excite_init_console(void)
{
#if defined(CONFIG_SERIAL_8250)
static __initdata char serr[] =
KERN_ERR "Serial port #%u setup failed\n";
struct uart_port up;
/* Take the DUART out of reset */
titan_writel(0x00ff1cff, CPRR);
#if defined(CONFIG_KGDB) || (CONFIG_SERIAL_8250_NR_UARTS > 1)
/* Enable both ports */
titan_writel(MASK_SER0 | MASK_SER1, UACFG);
#else
/* Enable port #0 only */
titan_writel(MASK_SER0, UACFG);
#endif /* defined(CONFIG_KGDB) */
/*
* Set up serial port #0. Do not use autodetection; the result is
* not what we want.
*/
memset(&up, 0, sizeof(up));
up.membase = (char *) titan_addr(REGBASE_SER0);
up.irq = TITAN_IRQ;
up.uartclk = TITAN_UART_CLK;
up.regshift = 0;
up.iotype = UPIO_RM9000;
up.type = PORT_RM9000;
up.flags = UPF_SHARE_IRQ;
up.line = 0;
if (early_serial_setup(&up))
printk(serr, up.line);
#if CONFIG_SERIAL_8250_NR_UARTS > 1
/* And now for port #1. */
up.membase = (char *) titan_addr(REGBASE_SER1);
up.line = 1;
if (early_serial_setup(&up))
printk(serr, up.line);
#endif /* CONFIG_SERIAL_8250_NR_UARTS > 1 */
#else
/* Leave the DUART in reset */
titan_writel(0x00ff3cff, CPRR);
#endif /* defined(CONFIG_SERIAL_8250) */
return 0;
}
static void
do_serial_add(serial_port *port)
{
void *regs;
uint irq;
uint baud_base;
uint reg_shift;
struct serial_struct s;
regs = port->regs;
irq = port->irq;
baud_base = port->baud_base;
reg_shift = port->reg_shift;
memset(&s, 0, sizeof(s));
s.line = ser_line++;
s.iomem_base = regs;
s.irq = irq + 2;
s.baud_base = baud_base / 16;
s.flags = ASYNC_BOOT_AUTOCONF;
s.io_type = SERIAL_IO_MEM;
s.iomem_reg_shift = reg_shift;
if (early_serial_setup(&s) != 0) {
printk(KERN_ERR "Serial setup failed!\n");
}
}
void __init bsp_serial_init(void)
{
struct uart_port s;
/* clear memory */
memset(&s, 0, sizeof(s));
/*
* UART0
*/
s.line = 0;
s.type = PORT_16550A;
s.irq = BSP_UART0_IRQ;
s.iotype = UPIO_MEM;
s.regshift = 2;
#if 1
s.uartclk = BSP_SYS_CLK_RATE;
s.fifosize = 16;
s.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY;
s.mapbase = BSP_UART0_MAP_BASE;
//s.membase = ioremap_nocache(s.mapbase, BSP_UART0_MAPSIZE);
s.membase = ioremap_nocache(s.mapbase, 0x20);
#else
s.uartclk = BSP_SYS_CLK_RATE - BSP_BAUDRATE * 24; //???
s.fifosize = 1; //???
s.flags = UPF_SKIP_TEST | UPF_LOW_LATENCY | UPF_SPD_CUST;
s.membase = (unsigned char *)BSP_UART0_BASE;
s.custom_divisor = BSP_SYS_CLK_RATE / (BSP_BAUDRATE * 16) - 1;
#endif
if (early_serial_setup(&s) != 0) {
panic("RTL8196B: bsp_serial_init failed!");
}
}
/*
* UART
*/
static void __init cns3420_early_serial_setup(void)
{
#ifdef CONFIG_SERIAL_8250_CONSOLE
static struct uart_port cns3420_serial_port = {
.membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
.mapbase = CNS3XXX_UART0_BASE,
.irq = IRQ_CNS3XXX_UART0,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
.regshift = 2,
.uartclk = 24000000,
.line = 0,
.type = PORT_16550A,
.fifosize = 16,
};
early_serial_setup(&cns3420_serial_port);
#endif
}
/*
* Initialization
*/
static struct platform_device *cns3420_pdevs[] __initdata = {
&cns3420_nor_pdev,
};
static void __init cns3420_init(void)
{
platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
pm_power_off = cns3xxx_power_off;
}
/*
* UART
*/
static void __init cns3420_early_serial_setup(void)
{
#ifdef CONFIG_SERIAL_8250_CONSOLE
static struct uart_port cns3420_serial_port = {
.membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
.mapbase = CNS3XXX_UART0_BASE,
.irq = IRQ_CNS3XXX_UART0,
.iotype = UPIO_MEM,
.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
.regshift = 2,
.uartclk = 24000000,
.line = 0,
.type = PORT_16550A,
.fifosize = 16,
};
early_serial_setup(&cns3420_serial_port);
#endif
}
/*
* USB
*/
static struct resource cns3xxx_usb_ehci_resources[] = {
[0] = {
.start = CNS3XXX_USB_BASE,
.end = CNS3XXX_USB_BASE + SZ_16M - 1,
.flags = IORESOURCE_MEM,
},
void __init ixp2000_map_io(void)
{
extern unsigned int processor_id;
/*
* On IXP2400 CPUs we need to use MT_IXP2000_DEVICE for
* tweaking the PMDs so XCB=101. On IXP2800s we use the normal
* PMD flags.
*/
if ((processor_id & 0xfffffff0) == 0x69054190) {
int i;
printk(KERN_INFO "Enabling IXP2400 erratum #66 workaround\n");
for(i=0;i<ARRAY_SIZE(ixp2000_io_desc);i++)
ixp2000_io_desc[i].type = MT_IXP2000_DEVICE;
}
iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc));
early_serial_setup(&ixp2000_serial_port);
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(0, &ixp2000_serial_port);
#endif
/* Set slowport to 8-bit mode. */
ixp2000_reg_write(IXP2000_SLOWPORT_FRM, 1);
}
/* The serial clock for the chip is an internal clock determined by
* different clock speeds/dividers.
* Calculate the proper input baud rate and setup the serial driver.
*/
static void __init
bubinga_early_serial_map(void)
{
u32 uart_div;
int uart_clock;
struct uart_port port;
/* Calculate the serial clock input frequency
*
* The base baud is the PLL OUTA (provided in the board info
* structure) divided by the external UART Divisor, divided
* by 16.
*/
uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
uart_clock = __res.bi_procfreq / uart_div;
/* Setup serial port access */
memset(&port, 0, sizeof(port));
port.membase = (void*)ACTING_UART0_IO_BASE;
port.irq = ACTING_UART0_INT;
port.uartclk = uart_clock;
port.regshift = 0;
port.iotype = UPIO_MEM;
port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
port.line = 0;
#ifdef CONFIG_SERIAL_8250
if (early_serial_setup(&port) != 0)
printk("Early serial init of port 0 failed\n");
#endif
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(0, &port);
#endif
port.membase = (void*)ACTING_UART1_IO_BASE;
port.irq = ACTING_UART1_INT;
port.line = 1;
#ifdef CONFIG_SERIAL_8250
if (early_serial_setup(&port) != 0)
printk("Early serial init of port 1 failed\n");
#endif
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(1, &port);
#endif
}
void __init str9100_map_io(void)
{
iotable_init(str9100_std_desc, ARRAY_SIZE(str9100_std_desc));
str9100_register_map_desc(str9100_std_desc, ARRAY_SIZE(str9100_std_desc));
#ifdef EARLY_REGISTER_CONSOLE
early_serial_setup(&str9100_serial_ports[0]);
#endif
}
static void __init
yosemite_early_serial_map(void)
{
struct uart_port port;
/* Setup ioremapped serial port access */
memset(&port, 0, sizeof(port));
port.mapbase = PPC440EP_UART0_ADDR;
port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
port.irq = 0;
port.uartclk = clocks.uart0;
port.regshift = 0;
port.iotype = SERIAL_IO_MEM;
port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 0 failed\n");
}
#if defined(CONFIG_SERIAL_TEXT_DEBUG)
/* Configure debug serial access */
gen550_init(0, &port);
#endif
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(0, &port);
#endif
port.mapbase = PPC440EP_UART1_ADDR;
port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
port.irq = 1;
port.uartclk = clocks.uart1;
port.line = 1;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 1 failed\n");
}
#if defined(CONFIG_SERIAL_TEXT_DEBUG)
/* Configure debug serial access */
gen550_init(1, &port);
#endif
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(1, &port);
#endif
}
static int __init early_serial_dev_init(void)
{
int i, res;
for (i = res = 0; i < ARRAY_SIZE(early_uarts) && !res; ++i) {
struct uart_port *port = early_uarts + i;
port->irq = __uart_irq();
res = early_serial_setup(port);
}
return res;
}
/*****************************************************************************
* Init
****************************************************************************/
static int __init ar7_register_uarts(void)
{
#ifdef CONFIG_SERIAL_8250
static struct uart_port uart_port __initdata;
struct clk *bus_clk;
int res;
memset(&uart_port, 0, sizeof(struct uart_port));
bus_clk = clk_get(NULL, "bus");
if (IS_ERR(bus_clk))
panic("unable to get bus clk");
uart_port.type = PORT_AR7;
uart_port.uartclk = clk_get_rate(bus_clk) / 2;
uart_port.iotype = UPIO_MEM32;
uart_port.regshift = 2;
uart_port.line = 0;
uart_port.irq = AR7_IRQ_UART0;
uart_port.mapbase = AR7_REGS_UART0;
uart_port.membase = ioremap(uart_port.mapbase, 256);
res = early_serial_setup(&uart_port);
if (res)
return res;
/* Only TNETD73xx have a second serial port */
if (ar7_has_second_uart()) {
uart_port.line = 1;
uart_port.irq = AR7_IRQ_UART1;
uart_port.mapbase = UR8_REGS_UART1;
uart_port.membase = ioremap(uart_port.mapbase, 256);
res = early_serial_setup(&uart_port);
if (res)
return res;
}
#endif
return 0;
}
static void __init jz_serial_setup(void)
{
#ifdef CONFIG_SERIAL_8250
struct uart_port s;
memset(&s, 0, sizeof(s));
s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
s.iotype = UPIO_MEM;
s.regshift = 2;
s.uartclk = jz_clocks.uartclk;
s.line = 0;
s.membase = (u8 *)UART0_BASE;
s.irq = IRQ_UART0;
if (early_serial_setup(&s) != 0) {
printk(KERN_ERR "Serial ttyS0 setup failed!\n");
}
s.line = 1;
s.membase = (u8 *)UART1_BASE;
s.irq = IRQ_UART1;
if (early_serial_setup(&s) != 0) {
printk(KERN_ERR "Serial ttyS1 setup failed!\n");
}
s.line = 2;
s.membase = (u8 *)UART2_BASE;
s.irq = IRQ_UART2;
if (early_serial_setup(&s) != 0) {
printk(KERN_ERR "Serial ttyS2 setup failed!\n");
}
s.line = 3;
s.membase = (u8 *)UART3_BASE;
s.irq = IRQ_UART3;
if (early_serial_setup(&s) != 0) {
printk(KERN_ERR "Serial ttyS3 setup failed!\n");
}
#endif
}
static void __init
ocotea_early_serial_map(void)
{
struct uart_port port;
/* Setup ioremapped serial port access */
memset(&port, 0, sizeof(port));
port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
port.irq = UART0_INT;
port.uartclk = clocks.uart0;
port.regshift = 0;
port.iotype = UPIO_MEM;
port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
port.line = 0;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 0 failed\n");
}
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
/* Configure debug serial access */
gen550_init(0, &port);
/* Purge TLB entry added in head_44x.S for early serial access */
_tlbie(UART0_IO_BASE, 0);
#endif
port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
port.irq = UART1_INT;
port.uartclk = clocks.uart1;
port.line = 1;
if (early_serial_setup(&port) != 0) {
printk("Early serial init of port 1 failed\n");
}
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
/* Configure debug serial access */
gen550_init(1, &port);
#endif
}
static void __init
serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
{
rs.membase = regs;
rs.irq = irq + 2;
rs.uartclk = baud_base;
rs.regshift = reg_shift;
early_serial_setup(&rs);
rs.line++;
}
static void __init
ocotea_early_serial_map(void)
{
struct serial_struct serial_req;
/* Setup ioremapped serial port access */
memset(&serial_req, 0, sizeof(serial_req));
serial_req.line = 0;
serial_req.baud_base = BASE_BAUD;
serial_req.port = 0;
serial_req.irq = 0;
serial_req.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
serial_req.io_type = SERIAL_IO_MEM;
serial_req.iomem_base = ioremap64(PPC440GX_UART0_ADDR, 8);
serial_req.iomem_reg_shift = 0;
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
/* Configure debug serial access */
gen550_init(0, &serial_req);
#endif
if (early_serial_setup(&serial_req) != 0) {
printk("Early serial init of port 0 failed\n");
}
/* Assume early_serial_setup() doesn't modify serial_req */
serial_req.line = 1;
serial_req.port = 1;
serial_req.irq = 1;
serial_req.iomem_base = ioremap64(PPC440GX_UART1_ADDR, 8);
#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
/* Configure debug serial access */
gen550_init(1, &serial_req);
#endif
if (early_serial_setup(&serial_req) != 0) {
printk("Early serial init of port 1 failed\n");
}
}
void __init plat_mem_setup(void)
{
int i, err;
char *s;
struct ssb_mipscore *mcore;
err = ssb_bus_ssbbus_register(&ssb, SSB_ENUM_BASE, bcm47xx_fill_sprom);
if (err) {
const char *msg = "Failed to initialize SSB bus (err %d)\n";
cfe_printk(msg, err); /* Make sure the message gets out of the box. */
panic(msg, err);
}
mcore = &ssb.mipscore;
/* FIXME: the nvram init depends on the ssb being fully initializes,
* can't use the fill_sprom callback yet! */
bcm47xx_fill_sprom_nvram(&ssb.sprom);
s = nvram_get("kernel_args");
if (s && !strncmp(s, "console=ttyS1", 13)) {
struct ssb_serial_port port;
cfe_printk("Swapping serial ports!\n");
/* swap serial ports */
memcpy(&port, &mcore->serial_ports[0], sizeof(port));
memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1], sizeof(port));
memcpy(&mcore->serial_ports[1], &port, sizeof(port));
}
for (i = 0; i < mcore->nr_serial_ports; i++) {
struct ssb_serial_port *port = &(mcore->serial_ports[i]);
struct uart_port s;
memset(&s, 0, sizeof(s));
s.line = i;
s.membase = port->regs;
s.irq = port->irq + 2;//FIXME?
s.uartclk = port->baud_base;
s.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
s.iotype = SERIAL_IO_MEM;
s.regshift = port->reg_shift;
early_serial_setup(&s);
}
cfe_printk("Serial init done.\n");
_machine_restart = bcm47xx_machine_restart;
_machine_halt = bcm47xx_machine_halt;
pm_power_off = bcm47xx_machine_halt;
board_time_init = bcm47xx_time_init;//FIXME move into ssb
}
static void __init taiga_early_serial_map(void)
{
struct uart_port serial_req;
/* Setup serial port access */
memset(&serial_req, 0, sizeof(serial_req));
serial_req.uartclk = UART_CLK;
serial_req.irq = IRQ_TSI108_UART0;
serial_req.flags = STD_COM_FLAGS;
serial_req.iotype = SERIAL_IO_MEM;
/* CONFIG_TAIGA: remapped */
serial_req.membase = (u_char *) (TAIGA_SERIAL_0 | TSI108_CSR_ADDR_VIRT);
#ifdef CONFIG_SERIAL_TEXT_DEBUG
gen550_init(0, &serial_req);
#endif
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(0, &serial_req);
#endif
if (early_serial_setup(&serial_req) != 0)
printk(KERN_ERR "Early serial init of port 0 failed\n");
/* Assume early_serial_setup() doesn't modify serial_req */
serial_req.line = 1;
serial_req.irq = IRQ_TSI108_UART1;
/* CONFIG_TAIGA: remapped */
serial_req.membase = (u_char *) (TAIGA_SERIAL_1 | TSI108_CSR_ADDR_VIRT);
#ifdef CONFIG_SERIAL_TEXT_DEBUG
gen550_init(1, &serial_req);
#endif
#ifdef CONFIG_KGDB_8250
kgdb8250_add_port(1, &serial_req);
#endif
if (early_serial_setup(&serial_req) != 0)
printk(KERN_ERR "Early serial init of port 1 failed\n");
}
static void __init
davinci_map_io(void)
{
davinci_map_common_io();
#ifdef CONFIG_KGDB_8250
early_serial_setup((struct uart_port *)&serial_platform_data[kgdb8250_ttyS]);
kgdb8250_add_platform_port(kgdb8250_ttyS, &serial_platform_data[kgdb8250_ttyS]);
#endif
/* Board-specific initialization */
board_init ();
}
void __init plat_mem_setup(void)
{
static struct uart_port uart;
unsigned int devfn = PCI_DEVFN(COBALT_PCICONF_VIA, 0);
int i;
_machine_restart = cobalt_machine_restart;
_machine_halt = cobalt_machine_halt;
pm_power_off = cobalt_machine_power_off;
set_io_port_base(CKSEG1ADDR(GT64111_IO_BASE));
/* I/O port resource must include UART and LCD/buttons */
ioport_resource.end = 0x0fffffff;
/* request I/O space for devices used on all i[345]86 PCs */
for (i = 0; i < COBALT_IO_RESOURCES; i++)
request_resource(&ioport_resource, cobalt_io_resources + i);
/* Read the cobalt id register out of the PCI config space */
PCI_CFG_SET(devfn, (VIA_COBALT_BRD_ID_REG & ~0x3));
cobalt_board_id = GALILEO_INL(GT_PCI0_CFGDATA_OFS);
cobalt_board_id >>= ((VIA_COBALT_BRD_ID_REG & 3) * 8);
cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(cobalt_board_id);
printk("Cobalt board ID: %d\n", cobalt_board_id);
#ifdef CONFIG_PCI
register_pci_controller(&cobalt_pci_controller);
#endif
#ifdef CONFIG_SERIAL_8250
if (cobalt_board_id > COBALT_BRD_ID_RAQ1) {
#ifdef CONFIG_EARLY_PRINTK
cobalt_early_console();
#endif
uart.line = 0;
uart.type = PORT_UNKNOWN;
uart.uartclk = 18432000;
uart.irq = COBALT_SERIAL_IRQ;
uart.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
uart.iobase = 0xc800000;
uart.iotype = UPIO_PORT;
early_serial_setup(&uart);
}
#endif
}
