C++ (Cpp) ec_clr_bit示例

示例#1

文件： smihandler.c 项目： tidatida/coreboot

int mainboard_io_trap_handler(int smif)
{
	static int smm_initialized;

	if (!smm_initialized) {
		mainboard_smm_init();
		smm_initialized = 1;
	}

	switch (smif) {
	case SMI_DOCK_CONNECT:
		ec_clr_bit(0x03, 2);
		udelay(250000);
		dock_connect();
		ec_set_bit(0x03, 2);
		/* set dock LED to indicate status */
		ec_write(0x0c, 0x09);
		ec_write(0x0c, 0x88);
		break;

	case SMI_DOCK_DISCONNECT:
		ec_clr_bit(0x03, 2);
		dock_disconnect();
		break;

	default:
		return 0;
	}

	/* On success, the IO Trap Handler returns 1
	 * On failure, the IO Trap Handler returns a value != 1 */
	return 1;
}

示例#2

void dock_disconnect(void)
{
	u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;

	ec_clr_bit(0x02, 0);
	ec_clr_bit(0x1a, 0);
	ec_clr_bit(0xfe, 4);

	outl(inl(gpiobase + 0x0c) & ~(1 << 28), gpiobase + 0x0c);
}

示例#3

文件： mainboard.c 项目： Godkey/coreboot

static void mainboard_init(device_t dev)
{
	device_t dev0, idedev, sdhci_dev;

	ec_clr_bit(0x03, 2);

	if (inb(0x164c) & 0x08) {
		ec_set_bit(0x03, 2);
		ec_write(0x0c, 0x88);
	}

#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
	/* Install custom int15 handler for VGA OPROM */
	mainboard_interrupt_handlers(0x15, &int15_handler);
#endif

	/* If we're resuming from suspend, blink suspend LED */
	dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
	if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
		ec_write(0x0c, 0xc7);

	idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
	if (idedev && idedev->chip_info && dock_ultrabay_device_present()) {
		struct southbridge_intel_i82801gx_config *config = idedev->chip_info;
		config->ide_enable_primary = 1;
		/* enable Ultrabay power */
		outb(inb(0x1628) | 0x01, 0x1628);
		ec_write(0x0c, 0x84);
	} else {
		/* disable Ultrabay power */
		outb(inb(0x1628) & ~0x01, 0x1628);
		ec_write(0x0c, 0x04);
	}

	/* Set SDHCI write protect polarity "SDWPPol" */
	sdhci_dev = dev_find_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C822, 0);
	if (sdhci_dev) {
		if (pci_read_config8(sdhci_dev, 0xfa) != 0x20) {
			/* unlock */
			pci_write_config8(sdhci_dev, 0xf9, 0xfc);
			/* set SDWPPol, keep CLKRUNDis, SDPWRPol clear */
			pci_write_config8(sdhci_dev, 0xfa, 0x20);
			/* restore lock */
			pci_write_config8(sdhci_dev, 0xf9, 0x00);
		}
	}
}

示例#4

文件： mainboard.c 项目： XVilka/coreboot

static void mainboard_enable(device_t dev)
{
    device_t dev0, idedev;
    u8 defaults_loaded = 0;

    ec_clr_bit(0x03, 2);

    if (inb(0x164c) & 0x08) {
        ec_set_bit(0x03, 2);
        ec_write(0x0c, 0x88);
    }
    /* If we're resuming from suspend, blink suspend LED */
    dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
    if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
        ec_write(0x0c, 0xc7);

    idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
    if (idedev && idedev->chip_info && dock_ultrabay_device_present()) {
        struct southbridge_intel_i82801gx_config *config = idedev->chip_info;
        config->ide_enable_primary = 1;
        /* enable Ultrabay power */
        outb(inb(0x1628) | 0x01, 0x1628);
        ec_write(0x0c, 0x84);
    } else {
        /* disable Ultrabay power */
        outb(inb(0x1628) & ~0x01, 0x1628);
        ec_write(0x0c, 0x04);
    }

    if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) {
        printk(BIOS_INFO, "failed to get cmos_defaults_loaded");
        defaults_loaded = 0;
    }

    if (!defaults_loaded) {
        printk(BIOS_INFO, "Restoring CMOS defaults\n");
        set_option("tft_brightness", &(u8[]) {
            0xff
        });
        set_option("volume", &(u8[]) {
            0x03
        });
        set_option("cmos_defaults_loaded", &(u8[]) {
            0x01
        });
    }

示例#5

文件： mainboard.c 项目： kmalkki/coreboot

static void mainboard_init(device_t dev)
{
	device_t dev0, idedev, sdhci_dev;

	ec_clr_bit(0x03, 2);

	if (inb(0x164c) & 0x08) {
		ec_set_bit(0x03, 2);
		ec_write(0x0c, 0x88);
	}

	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3);

	/* If we're resuming from suspend, blink suspend LED */
	dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
	if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
		ec_write(0x0c, 0xc7);

	idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
	if (idedev && idedev->chip_info && dock_ultrabay_device_present()) {
		struct southbridge_intel_i82801gx_config *config = idedev->chip_info;
		config->ide_enable_primary = 1;
		/* enable Ultrabay power */
		outb(inb(0x1628) | 0x01, 0x1628);
		ec_write(0x0c, 0x84);
	} else {
		/* disable Ultrabay power */
		outb(inb(0x1628) & ~0x01, 0x1628);
		ec_write(0x0c, 0x04);
	}

	/* Set SDHCI write protect polarity "SDWPPol" */
	sdhci_dev = dev_find_device(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C822, 0);
	if (sdhci_dev) {
		if (pci_read_config8(sdhci_dev, 0xfa) != 0x20) {
			/* unlock */
			pci_write_config8(sdhci_dev, 0xf9, 0xfc);
			/* set SDWPPol, keep CLKRUNDis, SDPWRPol clear */
			pci_write_config8(sdhci_dev, 0xfa, 0x20);
			/* restore lock */
			pci_write_config8(sdhci_dev, 0xf9, 0x00);
		}
	}
}