static int ed_isa_attach(device_t dev) { struct ed_softc *sc = device_get_softc(dev); int error; if (sc->port_used > 0) ed_alloc_port(dev, 0, sc->port_used); if (sc->mem_used) ed_alloc_memory(dev, 0, sc->mem_used); ed_alloc_irq(dev, 0, 0); if (sc->sc_media_ioctl == NULL) ed_gen_ifmedia_init(sc); error = ed_attach(dev); if (error) { ed_release_resources(dev); return (error); } error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, NULL, edintr, sc, &sc->irq_handle); if (error) ed_release_resources(dev); return (error); }
int ed_probe_Novell(device_t dev, int port_rid, int flags) { struct ed_softc *sc = device_get_softc(dev); int error; error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS); if (error) return (error); sc->asic_offset = ED_NOVELL_ASIC_OFFSET; sc->nic_offset = ED_NOVELL_NIC_OFFSET; return ed_probe_Novell_generic(dev, flags); }
/* * Probe and vendor-specific initialization routine for SIC boards */ int ed_probe_SIC(device_t dev, int port_rid, int flags) { struct ed_softc *sc = device_get_softc(dev); int error; int i; u_int memsize; u_long pmem; u_char sum; error = ed_alloc_port(dev, 0, ED_SIC_IO_PORTS); if (error) return (error); sc->asic_offset = ED_SIC_ASIC_OFFSET; sc->nic_offset = ED_SIC_NIC_OFFSET; memsize = 16384; /* XXX Needs to allow different msize */ error = ed_alloc_memory(dev, 0, memsize); if (error) return (error); sc->mem_start = 0; sc->mem_size = memsize; pmem = rman_get_start(sc->mem_res); error = ed_isa_mem_ok(dev, pmem, memsize); if (error) return (error); /* Reset card to force it into a known state. */ ed_asic_outb(sc, 0, 0x00); DELAY(100); /* * Here we check the card ROM, if the checksum passes, and the * type code and ethernet address check out, then we know we have * an SIC card. */ ed_asic_outb(sc, 0, 0x81); DELAY(100); sum = bus_space_read_1(sc->mem_bst, sc->mem_bsh, 6); for (i = 0; i < ETHER_ADDR_LEN; i++) sum ^= (sc->enaddr[i] = bus_space_read_1(sc->mem_bst, sc->mem_bsh, i)); #ifdef ED_DEBUG device_printf(dev, "ed_probe_sic: got address %6D\n", sc->enaddr, ":"); #endif if (sum != 0) return (ENXIO); if ((sc->enaddr[0] | sc->enaddr[1] | sc->enaddr[2]) == 0) return (ENXIO); sc->vendor = ED_VENDOR_SIC; sc->type_str = "SIC"; sc->isa16bit = 0; sc->cr_proto = 0; /* * SIC RAM page 0x0000-0x3fff(or 0x7fff) */ ed_asic_outb(sc, 0, 0x80); DELAY(100); error = ed_clear_memory(dev); if (error) return (error); sc->mem_shared = 1; sc->mem_end = sc->mem_start + sc->mem_size; /* * allocate one xmit buffer if < 16k, two buffers otherwise */ if ((sc->mem_size < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) sc->txb_cnt = 1; else sc->txb_cnt = 2; sc->tx_page_start = 0; sc->rec_page_start = sc->tx_page_start + ED_TXBUF_SIZE * sc->txb_cnt; sc->rec_page_stop = sc->tx_page_start + sc->mem_size / ED_PAGE_SIZE; sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; sc->sc_write_mbufs = ed_shmem_write_mbufs; return (0); }
int ed_probe_RTL80x9(device_t dev, int port_rid, int flags) { struct ed_softc *sc = device_get_softc(dev); char *ts; int error; if ((error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS))) return (error); sc->asic_offset = ED_NOVELL_ASIC_OFFSET; sc->nic_offset = ED_NOVELL_NIC_OFFSET; if (ed_nic_inb(sc, ED_P0_CR) & (ED_CR_PS0 | ED_CR_PS1)) ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP); if (ed_nic_inb(sc, ED_RTL80X9_80X9ID0) != ED_RTL80X9_ID0) return (ENXIO); switch (ed_nic_inb(sc, ED_RTL80X9_80X9ID1)) { case ED_RTL8019_ID1: sc->chip_type = ED_CHIP_TYPE_RTL8019; ts = "RTL8019"; break; case ED_RTL8029_ID1: sc->chip_type = ED_CHIP_TYPE_RTL8029; ts = "RTL8029"; break; default: return (ENXIO); } if ((error = ed_probe_Novell_generic(dev, flags))) return (error); sc->type_str = ts; sc->sc_media_ioctl = &ed_rtl80x9_media_ioctl; ifmedia_init(&sc->ifmedia, 0, ed_rtl_set_media, ed_rtl_get_media); ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, 0); ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, 0); ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_2, 0, 0); ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_5, 0, 0); ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, 0); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_PAGE_3 | ED_CR_STP); ed_nic_barrier(sc, ED_P0_CR, 1, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); switch (ed_nic_inb(sc, ED_RTL80X9_CONFIG2) & ED_RTL80X9_CF2_MEDIA) { case ED_RTL80X9_CF2_AUTO: ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_AUTO); break; case ED_RTL80X9_CF2_10_5: ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_10_5); break; case ED_RTL80X9_CF2_10_2: ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_10_2); break; case ED_RTL80X9_CF2_10_T: ifmedia_set(&sc->ifmedia, IFM_ETHER | IFM_10_T | ((ed_nic_inb(sc, ED_RTL80X9_CONFIG3) & ED_RTL80X9_CF3_FUDUP) ? IFM_FDX : 0)); break; } return (0); }
static int ed_pccard_attach(device_t dev) { u_char sum; u_char enaddr[ETHER_ADDR_LEN]; const struct ed_product *pp; int error, i, flags, port_rid, modem_rid; struct ed_softc *sc = device_get_softc(dev); u_long size; static uint16_t *intr_vals[] = {NULL, NULL}; sc->dev = dev; if ((pp = (const struct ed_product *) pccard_product_lookup(dev, (const struct pccard_product *) ed_pccard_products, sizeof(ed_pccard_products[0]), NULL)) == NULL) { printf("Can't find\n"); return (ENXIO); } modem_rid = port_rid = -1; if (pp->flags & NE2000DVF_MODEM) { for (i = 0; i < 4; i++) { size = bus_get_resource_count(dev, SYS_RES_IOPORT, i); if (size == ED_NOVELL_IO_PORTS) port_rid = i; else if (size == 8) modem_rid = i; } if (port_rid == -1) { device_printf(dev, "Cannot locate my ports!\n"); return (ENXIO); } } else { port_rid = 0; } /* Allocate the port resource during setup. */ error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS); if (error) { printf("alloc_port failed\n"); return (error); } if (rman_get_size(sc->port_res) == ED_NOVELL_IO_PORTS / 2) { port_rid++; sc->port_res2 = bus_alloc_resource(dev, SYS_RES_IOPORT, &port_rid, 0ul, ~0ul, 1, RF_ACTIVE); if (sc->port_res2 == NULL || rman_get_size(sc->port_res2) != ED_NOVELL_IO_PORTS / 2) { error = ENXIO; goto bad; } } error = ed_alloc_irq(dev, 0, 0); if (error) goto bad; /* * Determine which chipset we are. Almost all the PC Card chipsets * have the Novel ASIC and NIC offsets. There's 2 known cards that * follow the WD80x3 conventions, which are handled as a special case. */ sc->asic_offset = ED_NOVELL_ASIC_OFFSET; sc->nic_offset = ED_NOVELL_NIC_OFFSET; error = ENXIO; flags = device_get_flags(dev); if (error != 0) error = ed_pccard_dl100xx(dev, pp); if (error != 0) error = ed_pccard_ax88x90(dev, pp); if (error != 0) error = ed_pccard_tc5299j(dev, pp); if (error != 0) { error = ed_probe_Novell_generic(dev, flags); printf("Novell generic probe failed: %d\n", error); } if (error != 0 && (pp->flags & NE2000DVF_TOSHIBA)) { flags |= ED_FLAGS_TOSH_ETHER; flags |= ED_FLAGS_PCCARD; sc->asic_offset = ED_WD_ASIC_OFFSET; sc->nic_offset = ED_WD_NIC_OFFSET; error = ed_probe_WD80x3_generic(dev, flags, intr_vals); } if (error) goto bad; /* * There are several ways to get the MAC address for the card. * Some of the above probe routines can fill in the enaddr. If * not, we run through a number of 'well known' locations: * (1) From the PC Card FUNCE * (2) From offset 0 in the shared memory * (3) From a hinted offset in attribute memory * (4) From 0xff0 in attribute memory * If we can't get a non-zero MAC address from this list, we fail. */ for (i = 0, sum = 0; i < ETHER_ADDR_LEN; i++) sum |= sc->enaddr[i]; if (sum == 0) { pccard_get_ether(dev, enaddr); if (bootverbose) device_printf(dev, "CIS MAC %6D\n", enaddr, ":"); for (i = 0, sum = 0; i < ETHER_ADDR_LEN; i++) sum |= enaddr[i]; if (sum == 0 && ed_pccard_rom_mac(dev, enaddr)) { if (bootverbose) device_printf(dev, "ROM mac %6D\n", enaddr, ":"); sum++; } if (sum == 0 && pp->flags & NE2000DVF_ENADDR) { for (i = 0; i < ETHER_ADDR_LEN; i++) { pccard_attr_read_1(dev, pp->enoff + i * 2, enaddr + i); sum |= enaddr[i]; } if (bootverbose) device_printf(dev, "Hint %x MAC %6D\n", pp->enoff, enaddr, ":"); } if (sum == 0) { for (i = 0; i < ETHER_ADDR_LEN; i++) { pccard_attr_read_1(dev, ED_DEFAULT_MAC_OFFSET + i * 2, enaddr + i); sum |= enaddr[i]; } if (bootverbose) device_printf(dev, "Fallback MAC %6D\n", enaddr, ":"); } if (sum == 0) { device_printf(dev, "Cannot extract MAC address.\n"); ed_release_resources(dev); return (ENXIO); } bcopy(enaddr, sc->enaddr, ETHER_ADDR_LEN); } error = ed_attach(dev); if (error) goto bad; if (sc->chip_type == ED_CHIP_TYPE_DL10019 || sc->chip_type == ED_CHIP_TYPE_DL10022) { /* Try to attach an MII bus, but ignore errors. */ ed_pccard_dl100xx_mii_reset(sc); (void)mii_attach(dev, &sc->miibus, sc->ifp, ed_ifmedia_upd, ed_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); } else if (sc->chip_type == ED_CHIP_TYPE_AX88190 || sc->chip_type == ED_CHIP_TYPE_AX88790 || sc->chip_type == ED_CHIP_TYPE_TC5299J) { error = mii_attach(dev, &sc->miibus, sc->ifp, ed_ifmedia_upd, ed_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, MIIF_FORCEANEG); if (error != 0) { device_printf(dev, "attaching PHYs failed\n"); goto bad; } } if (sc->miibus != NULL) { sc->sc_tick = ed_pccard_tick; sc->sc_mediachg = ed_pccard_mediachg; sc->sc_media_ioctl = ed_pccard_media_ioctl; ed_pccard_kick_phy(sc); } else { ed_gen_ifmedia_init(sc); } if (modem_rid != -1) ed_pccard_add_modem(dev); error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, NULL, edintr, sc, &sc->irq_handle); if (error) { device_printf(dev, "setup intr failed %d \n", error); goto bad; } return (0); bad: ed_detach(dev); return (error); }
/* * Probe and vendor specific initialization for the HP PC Lan+ Cards. * (HP Part nos: 27247B and 27252A). * * The card has an asic wrapper around a DS8390 core. The asic handles * host accesses and offers both standard register IO and memory mapped * IO. Memory mapped I/O allows better performance at the expense of greater * chance of an incompatibility with existing ISA cards. * * The card has a few caveats: it isn't tolerant of byte wide accesses, only * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions * don't allow 32 bit accesses; these are indicated by a bit in the software * ID register (see if_edreg.h). * * Other caveats are: we should read the MAC address only when the card * is inactive. * * For more information; please consult the CRYNWR packet driver. * * The AUI port is turned on using the "link2" option on the ifconfig * command line. */ int ed_probe_HP_pclanp(device_t dev, int port_rid, int flags) { struct ed_softc *sc = device_get_softc(dev); int error; int n; /* temp var */ int memsize; /* mem on board */ u_char checksum; /* checksum of board address */ u_char irq; /* board configured IRQ */ uint8_t test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */ uint8_t test_buffer[ED_HPP_TEST_SIZE]; /* probing card */ rman_res_t conf_maddr, conf_msize, conf_irq, junk; error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS); if (error) return (error); /* Fill in basic information */ sc->asic_offset = ED_HPP_ASIC_OFFSET; sc->nic_offset = ED_HPP_NIC_OFFSET; sc->chip_type = ED_CHIP_TYPE_DP8390; sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */ /* * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" */ if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) || (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) || ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) || (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53)) return (ENXIO); /* * Read the MAC address and verify checksum on the address. */ ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC); for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++) checksum += (sc->enaddr[n] = ed_asic_inb(sc, ED_HPP_MAC_ADDR + n)); checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN); if (checksum != 0xFF) return (ENXIO); /* * Verify that the software model number is 0. */ ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID); if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) & ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000) return (ENXIO); /* * Read in and save the current options configured on card. */ sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION); sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | ED_HPP_OPTION_CHIP_RESET | ED_HPP_OPTION_ENABLE_IRQ); /* * Reset the chip. This requires writing to the option register * so take care to preserve the other bits. */ ed_asic_outw(sc, ED_HPP_OPTION, (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | ED_HPP_OPTION_CHIP_RESET))); DELAY(5000); /* wait for chip reset to complete */ ed_asic_outw(sc, ED_HPP_OPTION, (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET | ED_HPP_OPTION_CHIP_RESET | ED_HPP_OPTION_ENABLE_IRQ))); DELAY(5000); if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST)) return (ENXIO); /* reset did not complete */ /* * Read out configuration information. */ ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW); irq = ed_asic_inb(sc, ED_HPP_HW_IRQ); /* * Check for impossible IRQ. */ if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0]))) return (ENXIO); /* * If the kernel IRQ was specified with a '?' use the cards idea * of the IRQ. If the kernel IRQ was explicitly specified, it * should match that of the hardware. */ error = bus_get_resource(dev, SYS_RES_IRQ, 0, &conf_irq, &junk); if (error) bus_set_resource(dev, SYS_RES_IRQ, 0, ed_hpp_intr_val[irq], 1); else { if (conf_irq != ed_hpp_intr_val[irq]) return (ENXIO); } /* * Fill in softconfig info. */ sc->vendor = ED_VENDOR_HP; sc->type = ED_TYPE_HP_PCLANPLUS; sc->type_str = "HP-PCLAN+"; sc->mem_shared = 0; /* we DON'T have dual ported RAM */ sc->mem_start = 0; /* we use offsets inside the card RAM */ sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */ /* * The board has 32KB of memory. Is there a way to determine * this programmatically? */ memsize = 32768; /* * Check if memory mapping of the I/O registers possible. */ if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) { u_long mem_addr; /* * determine the memory address from the board. */ ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW); mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8); /* * Check that the kernel specified start of memory and * hardware's idea of it match. */ error = bus_get_resource(dev, SYS_RES_MEMORY, 0, &conf_maddr, &conf_msize); if (error) return (error); if (mem_addr != conf_maddr) return (ENXIO); error = ed_alloc_memory(dev, 0, memsize); if (error) return (error); sc->hpp_mem_start = rman_get_virtual(sc->mem_res); } /* * Fill in the rest of the soft config structure. */ /* * The transmit page index. */ sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET; if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING) sc->txb_cnt = 1; else sc->txb_cnt = 2; /* * Memory description */ sc->mem_size = memsize; sc->mem_ring = sc->mem_start + (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE); sc->mem_end = sc->mem_start + sc->mem_size; /* * Receive area starts after the transmit area and * continues till the end of memory. */ sc->rec_page_start = sc->tx_page_start + (sc->txb_cnt * ED_TXBUF_SIZE); sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE); sc->cr_proto = 0; /* value works */ /* * Set the wrap registers for string I/O reads. */ ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW); ed_asic_outw(sc, ED_HPP_HW_WRAP, ((sc->rec_page_start / ED_PAGE_SIZE) | (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8))); /* * Reset the register page to normal operation. */ ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF); /* * Verify that we can read/write from adapter memory. * Create test pattern. */ for (n = 0; n < ED_HPP_TEST_SIZE; n++) test_pattern[n] = (n*n) ^ ~n; #undef ED_HPP_TEST_SIZE /* * Check that the memory is accessible thru the I/O ports. * Write out the contents of "test_pattern", read back * into "test_buffer" and compare the two for any * mismatch. */ for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) { ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), sizeof(test_pattern)); ed_hpp_readmem(sc, (n * ED_PAGE_SIZE), test_buffer, sizeof(test_pattern)); if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) return (ENXIO); } sc->sc_mediachg = ed_hpp_set_physical_link; sc->sc_write_mbufs = ed_hpp_write_mbufs; sc->readmem = ed_hpp_readmem; return (0); }
/* * Probe and vendor-specific initialization routine for 3Com 3c503 boards */ int ed_probe_3Com(device_t dev, int port_rid, int flags) { struct ed_softc *sc = device_get_softc(dev); int error; int i; u_int memsize; u_char isa16bit; u_long conf_maddr, conf_msize, irq, junk, pmem; error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS); if (error) return (error); sc->asic_offset = ED_3COM_ASIC_OFFSET; sc->nic_offset = ED_3COM_NIC_OFFSET; /* * Verify that the kernel configured I/O address matches the board * configured address */ switch (ed_asic_inb(sc, ED_3COM_BCFR)) { case ED_3COM_BCFR_300: if (rman_get_start(sc->port_res) != 0x300) return (ENXIO); break; case ED_3COM_BCFR_310: if (rman_get_start(sc->port_res) != 0x310) return (ENXIO); break; case ED_3COM_BCFR_330: if (rman_get_start(sc->port_res) != 0x330) return (ENXIO); break; case ED_3COM_BCFR_350: if (rman_get_start(sc->port_res) != 0x350) return (ENXIO); break; case ED_3COM_BCFR_250: if (rman_get_start(sc->port_res) != 0x250) return (ENXIO); break; case ED_3COM_BCFR_280: if (rman_get_start(sc->port_res) != 0x280) return (ENXIO); break; case ED_3COM_BCFR_2A0: if (rman_get_start(sc->port_res) != 0x2a0) return (ENXIO); break; case ED_3COM_BCFR_2E0: if (rman_get_start(sc->port_res) != 0x2e0) return (ENXIO); break; default: return (ENXIO); } error = bus_get_resource(dev, SYS_RES_MEMORY, 0, &conf_maddr, &conf_msize); if (error) return (error); /* * Verify that the kernel shared memory address matches the board * configured address. */ switch (ed_asic_inb(sc, ED_3COM_PCFR)) { case ED_3COM_PCFR_DC000: if (conf_maddr != 0xdc000) return (ENXIO); break; case ED_3COM_PCFR_D8000: if (conf_maddr != 0xd8000) return (ENXIO); break; case ED_3COM_PCFR_CC000: if (conf_maddr != 0xcc000) return (ENXIO); break; case ED_3COM_PCFR_C8000: if (conf_maddr != 0xc8000) return (ENXIO); break; default: return (ENXIO); } /* * Reset NIC and ASIC. Enable on-board transceiver throughout reset * sequence because it'll lock up if the cable isn't connected if we * don't. */ ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); /* * Wait for a while, then un-reset it */ DELAY(50); /* * The 3Com ASIC defaults to rather strange settings for the CR after * a reset - it's important to set it again after the following outb * (this is done when we map the PROM below). */ ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); /* * Wait a bit for the NIC to recover from the reset */ DELAY(5000); sc->vendor = ED_VENDOR_3COM; sc->type_str = "3c503"; sc->mem_shared = 1; sc->cr_proto = ED_CR_RD2; /* * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window * to it. */ memsize = 8192; /* * Get station address from on-board ROM */ /* * First, map ethernet address PROM over the top of where the NIC * registers normally appear. */ ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); for (i = 0; i < ETHER_ADDR_LEN; ++i) sc->enaddr[i] = ed_nic_inb(sc, i); /* * Unmap PROM - select NIC registers. The proper setting of the * tranceiver is set in ed_init so that the attach code is given a * chance to set the default based on a compile-time config option */ ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); /* * Determine if this is an 8bit or 16bit board */ /* * select page 0 registers */ ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP); /* * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit * board. */ ed_nic_outb(sc, ED_P0_DCR, 0); /* * select page 2 registers */ ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); /* * The 3c503 forces the WTS bit to a one if this is a 16bit board */ if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS) isa16bit = 1; else isa16bit = 0; /* * select page 0 registers */ ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP); error = ed_alloc_memory(dev, 0, memsize); if (error) return (error); pmem = rman_get_start(sc->mem_res); error = ed_isa_mem_ok(dev, pmem, memsize); if (error) return (error); sc->mem_start = 0; sc->mem_size = memsize; sc->mem_end = sc->mem_start + memsize; /* * We have an entire 8k window to put the transmit buffers on the * 16bit boards. But since the 16bit 3c503's shared memory is only * fast enough to overlap the loading of one full-size packet, trying * to load more than 2 buffers can actually leave the transmitter idle * during the load. So 2 seems the best value. (Although a mix of * variable-sized packets might change this assumption. Nonetheless, * we optimize for linear transfers of same-size packets.) */ if (isa16bit) { if (flags & ED_FLAGS_NO_MULTI_BUFFERING) sc->txb_cnt = 1; else sc->txb_cnt = 2; sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; sc->rec_page_stop = memsize / ED_PAGE_SIZE + ED_3COM_RX_PAGE_OFFSET_16BIT; sc->mem_ring = sc->mem_start; } else { sc->txb_cnt = 1; sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; sc->rec_page_stop = memsize / ED_PAGE_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); } sc->isa16bit = isa16bit; /* * Initialize GA page start/stop registers. Probably only needed if * doing DMA, but what the hell. */ ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start); ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop); /* * Set IRQ. 3c503 only allows a choice of irq 2-5. */ error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk); if (error) return (error); switch (irq) { case 2: case 9: ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); break; case 3: ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); break; case 4: ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); break; case 5: ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); break; default: device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n", irq); return (ENXIO); } /* * Initialize GA configuration register. Set bank and enable shared * mem. */ ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); /* * Initialize "Vector Pointer" registers. These gawd-awful things are * compared to 20 bits of the address on ISA, and if they match, the * shared memory is disabled. We set them to 0xffff0...allegedly the * reset vector. */ ed_asic_outb(sc, ED_3COM_VPTR2, 0xff); ed_asic_outb(sc, ED_3COM_VPTR1, 0xff); ed_asic_outb(sc, ED_3COM_VPTR0, 0x00); error = ed_clear_memory(dev); if (error == 0) { sc->sc_mediachg = ed_3c503_mediachg; sc->sc_write_mbufs = ed_shmem_write_mbufs; } return (error); }