示例#1
0
文件: mpc85xx_edac.c 项目: E-LLP/n900
static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci)
{
	struct mpc85xx_pci_pdata *pdata = pci->pvt_info;
	u32 err_detect;

	err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR);

	/* master aborts can happen during PCI config cycles */
	if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) {
		out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);
		return;
	}

	printk(KERN_ERR "PCI error(s) detected\n");
	printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect);

	printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n",
	       in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB));
	printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n",
	       in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR));
	printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n",
	       in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR));
	printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n",
	       in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL));
	printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n",
	       in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH));

	/* clear error bits */
	out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect);

	if (err_detect & PCI_EDE_PERR_MASK)
		edac_pci_handle_pe(pci, pci->ctl_name);

	if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK)
		edac_pci_handle_npe(pci, pci->ctl_name);
}
示例#2
0
static void amd8131_pcix_check(struct edac_pci_ctl_info *edac_dev)
{
	struct amd8131_dev_info *dev_info = edac_dev->pvt_info;
	struct pci_dev *dev = dev_info->dev;
	u32 val32;

	
	edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
	if (val32 & MEM_LIMIT_MASK) {
		printk(KERN_INFO "Error(s) in mem limit register "
			"on %s bridge\n", dev_info->ctl_name);
		printk(KERN_INFO "DPE: %d, RSE: %d, RMA: %d\n"
			"RTA: %d, STA: %d, MDPE: %d\n",
			val32 & MEM_LIMIT_DPE,
			val32 & MEM_LIMIT_RSE,
			val32 & MEM_LIMIT_RMA,
			val32 & MEM_LIMIT_RTA,
			val32 & MEM_LIMIT_STA,
			val32 & MEM_LIMIT_MDPE);

		val32 |= MEM_LIMIT_MASK;
		edac_pci_write_dword(dev, REG_MEM_LIM, val32);

		edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
	}

	
	edac_pci_read_dword(dev, REG_INT_CTLR, &val32);
	if (val32 & INT_CTLR_DTS) {
		printk(KERN_INFO "Error(s) in interrupt and control register "
			"on %s bridge\n", dev_info->ctl_name);
		printk(KERN_INFO "DTS: %d\n", val32 & INT_CTLR_DTS);

		val32 |= INT_CTLR_DTS;
		edac_pci_write_dword(dev, REG_INT_CTLR, val32);

		edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
	}

	
	edac_pci_read_dword(dev, REG_LNK_CTRL_A, &val32);
	if (val32 & LNK_CTRL_CRCERR_A) {
		printk(KERN_INFO "Error(s) in link conf and control register "
			"on %s bridge\n", dev_info->ctl_name);
		printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_A);

		val32 |= LNK_CTRL_CRCERR_A;
		edac_pci_write_dword(dev, REG_LNK_CTRL_A, val32);

		edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
	}

	
	edac_pci_read_dword(dev, REG_LNK_CTRL_B, &val32);
	if (val32 & LNK_CTRL_CRCERR_B) {
		printk(KERN_INFO "Error(s) in link conf and control register "
			"on %s bridge\n", dev_info->ctl_name);
		printk(KERN_INFO "CRCERR: %d\n", val32 & LNK_CTRL_CRCERR_B);

		val32 |= LNK_CTRL_CRCERR_B;
		edac_pci_write_dword(dev, REG_LNK_CTRL_B, val32);

		edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
	}
}
static void amd8111_pci_bridge_check(struct edac_pci_ctl_info *edac_dev)
{
	struct amd8111_pci_info *pci_info = edac_dev->pvt_info;
	struct pci_dev *dev = pci_info->dev;
	u32 val32;

	/* Check out PCI Bridge Status and Command Register */
	edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
	if (val32 & PCI_STSCMD_CLEAR_MASK) {
		printk(KERN_INFO "Error(s) in PCI bridge status and command"
			"register on device %s\n", pci_info->ctl_name);
		printk(KERN_INFO "SSE: %d, RMA: %d, RTA: %d\n",
			(val32 & PCI_STSCMD_SSE) != 0,
			(val32 & PCI_STSCMD_RMA) != 0,
			(val32 & PCI_STSCMD_RTA) != 0);

		val32 |= PCI_STSCMD_CLEAR_MASK;
		edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);

		edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
	}

	/* Check out HyperTransport Link Control Register */
	edac_pci_read_dword(dev, REG_HT_LINK, &val32);
	if (val32 & HT_LINK_LKFAIL) {
		printk(KERN_INFO "Error(s) in hypertransport link control"
			"register on device %s\n", pci_info->ctl_name);
		printk(KERN_INFO "LKFAIL: %d\n",
			(val32 & HT_LINK_LKFAIL) != 0);

		val32 |= HT_LINK_LKFAIL;
		edac_pci_write_dword(dev, REG_HT_LINK, val32);

		edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
	}

	/* Check out PCI Interrupt and Bridge Control Register */
	edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
	if (val32 & PCI_INTBRG_CTRL_DTSTAT) {
		printk(KERN_INFO "Error(s) in PCI interrupt and bridge control"
			"register on device %s\n", pci_info->ctl_name);
		printk(KERN_INFO "DTSTAT: %d\n",
			(val32 & PCI_INTBRG_CTRL_DTSTAT) != 0);

		val32 |= PCI_INTBRG_CTRL_DTSTAT;
		edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);

		edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
	}

	/* Check out PCI Bridge Memory Base-Limit Register */
	edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
	if (val32 & MEM_LIMIT_CLEAR_MASK) {
		printk(KERN_INFO
			"Error(s) in mem limit register on %s device\n",
			pci_info->ctl_name);
		printk(KERN_INFO "DPE: %d, RSE: %d, RMA: %d\n"
			"RTA: %d, STA: %d, MDPE: %d\n",
			(val32 & MEM_LIMIT_DPE)  != 0,
			(val32 & MEM_LIMIT_RSE)  != 0,
			(val32 & MEM_LIMIT_RMA)  != 0,
			(val32 & MEM_LIMIT_RTA)  != 0,
			(val32 & MEM_LIMIT_STA)  != 0,
			(val32 & MEM_LIMIT_MDPE) != 0);

		val32 |= MEM_LIMIT_CLEAR_MASK;
		edac_pci_write_dword(dev, REG_MEM_LIM, val32);

		edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
	}
}