double X(elapsed_since)(const planner *plnr, const problem *p, crude_time t0) { double t = elapsed_since(t0); if (plnr->cost_hook) t = plnr->cost_hook(p, t, COST_MAX); return t; }
void game_tick(Game *game) { int ch = 0, move_result = BALL_MOVED; long elapsed = elapsed_since(&game->start_time); static long last_event = 0; if ((elapsed - last_event) >= (BALL_DELAY * MICROSECONDS_PER_SECOND)) { move_result = ball_move(game->ball, game->field, game->player); if (move_result == BALL_SCORE) { game->player->score += 1; } else if (move_result == BALL_MISS) { game->player->score = 0; ball_reset(game->ball, game->field); } last_event = elapsed; } if ((ch = getch()) != ERR) { if (ch == MOVE_UP) { player_move(game->field, game->player, -1); } if (ch == MOVE_DOWN) { player_move(game->field, game->player, 1); } } // field_refresh(game->field); field_redraw(game->field); wclear(game->field->game); field_draw_score(game->field, game->player); wrefresh(game->field->score); player_draw(game->player, game->field); ball_draw(game->ball, game->field); wrefresh(game->field->game); }
/** * Periodic task */ static void masterHandler(void) { static twiRequestT req; static enum { idleTS = 0, queryRegulatorTemperature1TS, waitForRegulatorTemperature1TS, queryRegulatorTemperature2TS, waitForRegulatorTemperature2TS, queryRegulatorFailCodesTS, waitForRegulatorFailCodesTS, queryRegulatorCurrentFaultTS, waitForRegulatorCurrentFaultTS, queryRegulatorPhaseFaultTS, waitForRegulatorPhaseFaultTS, queryInputVoltageTS, waitForInputVoltageTS, queryOutputVoltageTS, waitForOutputVoltageTS, queryBoardTempsTS, waitForBoardTempsTS, queryTachsTS, waitForTachsTS, queryPowerStatusTS, waitForPowerStatusTS } state; static enum { resetBS = 0, idleBS, retrySubmitBS, busyBS } busState[TWI_BUS_COUNT]; static uint16_t lastModulePoll; static uint16_t lastIRPoll; static uint16_t watchdog[TWI_BUS_COUNT]; static uint8_t txBuffer[16]; static uint8_t rxBuffer[32]; static uint8_t slave; static uint8_t ir; static int16_t temperature; int status; uint16_t v; uint8_t i; spiFpgaTwiMasterHandler(); for (i = 0; i < TWI_BUS_COUNT; i++) { if (masterRequestHead[i]) { switch (busState[i]) { case resetBS: switch (i) { case TWI_BUS_UC: twiReset(); twi_master_setup(); break; case TWI_BUS_FPGA: spiFpgaTwiReset(); break; } busState[i] = idleBS; break; case idleBS: /* fall through */ case retrySubmitBS: switch (i) { case TWI_BUS_UC: status = twiMasterWriteRead(masterRequestHead[TWI_BUS_UC]->addr, masterRequestHead[TWI_BUS_UC]->tx, masterRequestHead[TWI_BUS_UC]->txLength, masterRequestHead[TWI_BUS_UC]->rx, masterRequestHead[TWI_BUS_UC]->rxLength); break; case TWI_BUS_FPGA: status = spiFpgaTwiMasterWriteRead(masterRequestHead[TWI_BUS_FPGA]->addr, masterRequestHead[TWI_BUS_FPGA]->tx, masterRequestHead[TWI_BUS_FPGA]->txLength, masterRequestHead[TWI_BUS_FPGA]->rx, masterRequestHead[TWI_BUS_FPGA]->rxLength); break; } if (status == TWI_SUCCESS) { busState[i] = busyBS; watchdog[i] = msec_ticker; } else { if (busState[i] == idleBS) { watchdog[i] = msec_ticker; busState[i] = retrySubmitBS; } else if (elapsed_since(watchdog[i]) > TWI_TIME_MAX) { masterRequestHead[i]->result = status; masterRequestHead[i]->pending = 0; masterRequestHead[i] = masterRequestHead[i]->next; busState[i] = resetBS; } } break; case busyBS: switch (i) { case TWI_BUS_UC: status = twiStatus(); break; case TWI_BUS_FPGA: status = spiFpgaTwiStatus(); break; } if (status != TWI_BUSY) { masterRequestHead[i]->result = status; masterRequestHead[i]->pending = 0; masterRequestHead[i] = masterRequestHead[i]->next; busState[i] = idleBS; } else if (elapsed_since(watchdog[i]) > TWI_TIME_MAX) { masterRequestHead[i]->result = TWI_TIMEOUT; masterRequestHead[i]->pending = 0; masterRequestHead[i] = masterRequestHead[i]->next; busState[i] = resetBS; } break; } } } switch (state) { case idleTS: if (boardid == iraBID && elapsed_since(lastIRPoll) >= TWI_IR_POLLING_INTERVAL) { lastIRPoll = msec_ticker; ir = 0; state = queryRegulatorTemperature1TS; } else if (ucinfo.master && ucinfo.num_slaves && elapsed_since(lastModulePoll) >= TWI_MODULE_POLLING_INTERVAL) { lastModulePoll = msec_ticker; slave = 0; state = queryBoardTempsTS; } break; /* * Regulator Temperature 1 */ case queryRegulatorTemperature1TS: txBuffer[0] = IR3566B_REG_TEMP1; req.addr = TWI_IR3566B_STARTADDR + ir; req.tx = txBuffer; req.txLength = 1; req.rx = rxBuffer; req.rxLength = 1; twiQueueRequest(TWI_BUS_IR3566B, &req); state = waitForRegulatorTemperature1TS; break; case waitForRegulatorTemperature1TS: if (!req.pending) { if (req.result == TWI_SUCCESS) temperature = rxBuffer[0]; else temperature = -1; state = queryRegulatorTemperature2TS; } break; /* * Regulator Temperature 2 */ case queryRegulatorTemperature2TS: txBuffer[0] = IR3566B_REG_TEMP2; req.addr = TWI_IR3566B_STARTADDR + ir; req.tx = txBuffer; req.txLength = 1; req.rx = rxBuffer; req.rxLength = 1; twiQueueRequest(TWI_BUS_IR3566B, &req); state = waitForRegulatorTemperature2TS; break; case waitForRegulatorTemperature2TS: if (!req.pending) { if (req.result == TWI_SUCCESS) { if ((int16_t) rxBuffer[0] > temperature) temperature = rxBuffer[0]; } if (temperature >= 0) gwq_update_board_temperature(ir, 0x1000 | (uint16_t) temperature); state = queryRegulatorFailCodesTS; } break; /* * Regulator Fail Codes */ case queryRegulatorFailCodesTS: txBuffer[0] = IR3566B_REG_L1_FAIL; req.addr = TWI_IR3566B_STARTADDR + ir; req.tx = txBuffer; req.txLength = 1; req.rx = rxBuffer; req.rxLength = 1; twiQueueRequest(TWI_BUS_IR3566B, &req); state = waitForRegulatorFailCodesTS; break; case waitForRegulatorFailCodesTS: if (!req.pending) { if (req.result == TWI_SUCCESS) { if (rxBuffer[0]) { /* a failure code is pending */ if (rxBuffer[0] & IR3566B_REG_L1_FAIL_OVER_TEMP) usbctrlDebugStreamPrintf("Regulator %d Fail: Over Temp\n", ir); if (rxBuffer[0] & IR3566B_REG_L1_FAIL_OVER_CURRENT) usbctrlDebugStreamPrintf("Regulator %d Fail: Over Current\n", ir); if (rxBuffer[0] & IR3566B_REG_L1_FAIL_VCPU_HIGH) usbctrlDebugStreamPrintf("Regulator %d Fail: VCPU High\n", ir); if (rxBuffer[0] & IR3566B_REG_L1_FAIL_VCPU_LOW) usbctrlDebugStreamPrintf("Regulator %d Fail: VCPU Low\n", ir); if (rxBuffer[0] & IR3566B_REG_L1_FAIL_V12_LOW) usbctrlDebugStreamPrintf("Regulator %d Fail: V12 Low\n", ir); if (rxBuffer[0] & IR3566B_REG_L1_FAIL_V3_LOW) usbctrlDebugStreamPrintf("Regulator %d Fail: V3 Low\n", ir); if (rxBuffer[0] & IR3566B_REG_L1_FAIL_PHASE_FAULT) usbctrlDebugStreamPrintf("Regulator %d Fail: Phase Fault\n", ir); if (rxBuffer[0] & IR3566B_REG_L1_FAIL_SLOW_OVER_CURRENT) usbctrlDebugStreamPrintf("Regulator %d Fail: Slow Over Current\n", ir); /* clear sticky codes */ txBuffer[0] = IR3566B_REG_CLEAR_FAIL; txBuffer[1] = IR3566B_REG_CLEAR_FAIL_L1_STICKY; req.addr = TWI_IR3566B_STARTADDR + ir; req.tx = txBuffer; req.txLength = 2; req.rx = rxBuffer; req.rxLength = 0; twiQueueRequest(TWI_BUS_IR3566B, &req); } } state = queryRegulatorCurrentFaultTS; } break; /* * Regulator Current Fault */ case queryRegulatorCurrentFaultTS: txBuffer[0] = IR3566B_REG_L1_CURRENT_FAULT; req.addr = TWI_IR3566B_STARTADDR + ir; req.tx = txBuffer; req.txLength = 1; req.rx = rxBuffer; req.rxLength = 1; twiQueueRequest(TWI_BUS_IR3566B, &req); state = waitForRegulatorCurrentFaultTS; break; case waitForRegulatorCurrentFaultTS: if (!req.pending) { if (req.result == TWI_SUCCESS) { if ((rxBuffer[0] & IR3566B_REG_L1_CURRENT_FAULT_MAX) || (rxBuffer[0] & IR3566B_REG_L1_CURRENT_FAULT_MIN)) { /* a failure code is pending */ if (rxBuffer[0] & IR3566B_REG_L1_CURRENT_FAULT_MIN) usbctrlDebugStreamPrintf("Regulator %d Current Fault: Min\n", ir); if (rxBuffer[0] & IR3566B_REG_L1_CURRENT_FAULT_MAX) usbctrlDebugStreamPrintf("Regulator %d Current Fault: Max\n", ir); /* read the phase that is generating the fault */ state = queryRegulatorPhaseFaultTS; } else { /* move to next statistic */ state = queryInputVoltageTS; } } } break; /* * Regulator Phase Fault */ case queryRegulatorPhaseFaultTS: txBuffer[0] = IR3566B_REG_PHASE_FAULT; req.addr = TWI_IR3566B_STARTADDR + ir; req.tx = txBuffer; req.txLength = 1; req.rx = rxBuffer; req.rxLength = 1; twiQueueRequest(TWI_BUS_IR3566B, &req); state = waitForRegulatorPhaseFaultTS; break; case waitForRegulatorPhaseFaultTS: if (!req.pending) { if (req.result == TWI_SUCCESS) { /* report which phase is generating the fault */ if (rxBuffer[0] == IR3566B_REG_PHASE_FAULT_PHASE1) usbctrlDebugStreamWriteStr("Fault in Phase 1\n"); if (rxBuffer[0] == IR3566B_REG_PHASE_FAULT_PHASE2) usbctrlDebugStreamWriteStr("Fault in Phase 2\n"); if (rxBuffer[0] == IR3566B_REG_PHASE_FAULT_PHASE3) usbctrlDebugStreamWriteStr("Fault in Phase 3\n"); if (rxBuffer[0] == IR3566B_REG_PHASE_FAULT_PHASE4) usbctrlDebugStreamWriteStr("Fault in Phase 4\n"); if (rxBuffer[0] == IR3566B_REG_PHASE_FAULT_PHASE5) usbctrlDebugStreamWriteStr("Fault in Phase 5\n"); if (rxBuffer[0] == IR3566B_REG_PHASE_FAULT_PHASE6) usbctrlDebugStreamWriteStr("Fault in Phase 6\n"); if (rxBuffer[0] == IR3566B_REG_PHASE_FAULT_PHASE7) usbctrlDebugStreamWriteStr("Fault in Phase 7\n"); /* clear the phase fault */ txBuffer[0] = IR3566B_REG_CLEAR_PHASE_FAULT; txBuffer[1] = IR3566B_REG_CLEAR_PHASE_FAULT_BIT; req.addr = TWI_IR3566B_STARTADDR + ir; req.tx = txBuffer; req.txLength = 2; req.rx = rxBuffer; req.rxLength = 0; twiQueueRequest(TWI_BUS_IR3566B, &req); } state = queryInputVoltageTS; } break; /* * Regulator Input Voltage */ case queryInputVoltageTS: txBuffer[0] = IR3566B_REG_VIN_SUPPLY; req.addr = TWI_IR3566B_STARTADDR + ir; req.tx = txBuffer; req.txLength = 1; req.rx = rxBuffer; req.rxLength = 1; twiQueueRequest(TWI_BUS_IR3566B, &req); state = waitForInputVoltageTS; break; case waitForInputVoltageTS: if (!req.pending) { if (req.result == TWI_SUCCESS) moduleStatus[0].inputMillivolts[ir] = (uint16_t) ((uint32_t) rxBuffer[0] * 1000 / 8); state = queryOutputVoltageTS; } break; /* * Regulator Output Voltage */ case queryOutputVoltageTS: txBuffer[0] = IR3566B_REG_L1_VOUT; req.addr = TWI_IR3566B_STARTADDR + ir; req.tx = txBuffer; req.txLength = 1; req.rx = rxBuffer; req.rxLength = 1; twiQueueRequest(TWI_BUS_IR3566B, &req); state = waitForOutputVoltageTS; break; case waitForOutputVoltageTS: if (!req.pending) { if (req.result == TWI_SUCCESS) { moduleStatus[0].outputMillivolts[ir] = (uint16_t) ((uint32_t) rxBuffer[0] * 1000 / 128); } if (++ir < 4) { state = queryRegulatorTemperature1TS; } else { state = idleTS; } } break; /* * Board Temperatures */ case queryBoardTempsTS: txBuffer[0] = TWICMD_BOARD_TEMPERATURES; req.addr = TWI_SLAVE_STARTADDR + slave; req.tx = txBuffer; req.txLength = 1; req.rx = rxBuffer; req.rxLength = 8; twiQueueRequest(TWI_BUS_UC, &req); state = waitForBoardTempsTS; break; case waitForBoardTempsTS: if (!req.pending) { if (req.result == TWI_SUCCESS) { for (i = 0; i < 4; i++) { v = ((uint16_t) rxBuffer[i * 2 + 0] << 8) | rxBuffer[i * 2 + 1]; gwq_update_board_temperature((slave + 1) * 4 + i, v); } } state = queryTachsTS; } break; /* * Board Tachs */ case queryTachsTS: txBuffer[0] = TWICMD_TACHS; req.addr = TWI_SLAVE_STARTADDR + slave; req.tx = txBuffer; req.txLength = 1; req.rx = rxBuffer; req.rxLength = 8; twiQueueRequest(TWI_BUS_UC, &req); state = waitForTachsTS; break; case waitForTachsTS: if (!req.pending) { if (req.result == TWI_SUCCESS) { for (i = 0; i < 4; i++) { v = ((uint16_t) rxBuffer[i * 2 + 0] << 8) | rxBuffer[i * 2 + 1]; gwq_update_tach((slave + 1) * 4 + i, v); } } state = queryPowerStatusTS; } break; /* * Board Power Status */ case queryPowerStatusTS: txBuffer[0] = TWICMD_POWER_STATUS; req.addr = TWI_SLAVE_STARTADDR + slave; req.tx = txBuffer; req.txLength = 1; req.rx = rxBuffer; req.rxLength = 18; twiQueueRequest(TWI_BUS_UC, &req); state = waitForPowerStatusTS; break; case waitForPowerStatusTS: if (!req.pending) { if (req.result == TWI_SUCCESS) { for (i = 0; i < 4; i++) { v = ((uint16_t) rxBuffer[i * 4 + 2] << 8) | rxBuffer[i * 4 + 3]; moduleStatus[slave + 1].inputMillivolts[i] = v; v = ((uint16_t) rxBuffer[i * 4 + 4] << 8) | rxBuffer[i * 4 + 5]; moduleStatus[slave + 1].outputMillivolts[i] = v; } } if (++slave < ucinfo.num_slaves) state = queryBoardTempsTS; else state = idleTS; } break; } }