static int mpegaudio_command(struct em8300_s *em, int cmd)
{
em8300_waitfor(em, ucregister(MA_Command), 0xffff, 0xffff);
pr_debug("em8300-%d: MA_Command: %d\n", em->instance, cmd);
write_ucregister(MA_Command, cmd);
return em8300_waitfor(em, ucregister(MA_Status), cmd, 0xffff);
}
int em8300_writeregblock(struct em8300_s *em, int offset, unsigned *buf, int len)
{
int i;
writel(offset & 0xffff, &em->mem[0x1c11]);
writel((offset >> 16) & 0xffff, &em->mem[0x1c12]);
writel(len, &em->mem[0x1c13]);
writel(len, &em->mem[0x1c14]);
writel(0, &em->mem[0x1c15]);
writel(1, &em->mem[0x1c16]);
writel(1, &em->mem[0x1c17]);
writel(offset & 0xffff, &em->mem[0x1c18]);
writel((offset >> 16) & 0xffff, &em->mem[0x1c19]);
writel(1, &em->mem[0x1c1a]);
for (i = 0; i < len / 4; i++) {
writel(*buf++, &em->mem[0x11800]);
}
if (em8300_waitfor(em, 0x1c1a, 0, 1)) {
return -ETIME;
}
return 0;
}
int em8300_setregblock(struct em8300_s *em, int offset, int val, int len)
{
int i;
for (i = 1000; i; i--) {
if (!read_register(0x1c1a)) {
break;
}
if (!i) {
return -ETIME;
}
}
#if 0 /* FIXME: was in the zeev01 branch, verify if it is necessary */
val = val | (val << 8) | (val << 16) | (val << 24);
#endif
writel(offset & 0xffff, &em->mem[0x1c11]);
writel((offset >> 16) & 0xffff, &em->mem[0x1c12]);
writel(len, &em->mem[0x1c13]);
writel(len, &em->mem[0x1c14]);
writel(0, &em->mem[0x1c15]);
writel(1, &em->mem[0x1c16]);
writel(1, &em->mem[0x1c17]);
writel(offset & 0xffff, &em->mem[0x1c18]);
writel(0, &em->mem[0x1c19]);
writel(1, &em->mem[0x1c1a]);
for (i = 0; i < len / 4; i++) {
writel(val, &em->mem[0x11800]);
}
switch (len % 4) {
case 1:
writel(val, &em->mem[0x10000]);
break;
case 2:
writel(val, &em->mem[0x10800]);
break;
case 3:
writel(val, &em->mem[0x11000]);
break;
}
for (i = 1000; i; i--) {
if (!read_register(0x1c1a)) {
break;
}
if (!i) {
return -ETIME;
}
}
#if 0 /* FIXME: was in zeev01 branch, verify if it is necessary */
if (em8300_waitfor(em, 0x1c1a, 0, 1))
return -ETIME;
#endif
return 0;
}
int em8300_dicom_update(struct em8300_s *em)
{
int ret;
int vmode_ntsc = 1;
if (em->config.model.dicom_other_pal) {
vmode_ntsc = (em->video_mode == EM8300_VIDEOMODE_NTSC);
}
if ((ret = em8300_waitfor(em, ucregister(DICOM_UpdateFlag), 0, 1))) {
return ret;
}
if (em->overlay_enabled) {
sub_4288c(em, em->overlay_frame_xpos, em->overlay_frame_ypos, em->overlay_frame_width,
em->overlay_frame_height, em->overlay_a[EM9010_ATTRIBUTE_XOFFSET],
em->overlay_a[EM9010_ATTRIBUTE_YOFFSET], em->overlay_a[EM9010_ATTRIBUTE_XCORR], em->overlay_double_y);
} else {
int f_vs, f_hs, f_vo, f_ho;
int v_vs, v_hs, v_vo, v_ho;
v_vs = f_vs = tvmodematrix[em->video_mode].vertsize;
v_hs = f_hs = tvmodematrix[em->video_mode].horizsize;
v_vo = f_vo = tvmodematrix[em->video_mode].vertoffset;
v_ho = f_ho = tvmodematrix[em->video_mode].horizoffset;
f_vo += ((100 - em->zoom) * f_vs + 100) / 200;
f_ho += 2 * (((100 - em->zoom) * f_hs + 200) / 400);
v_vo += ((100 - em->zoom) * v_vs + 100) / 200;
v_ho += 2 * (((100 - em->zoom) * v_hs + 200) / 400);
f_vs = (em->zoom * f_vs + 50) / 100;
f_hs = (em->zoom * f_hs + 50) / 100;
v_vs = (em->zoom * v_vs + 50) / 100;
v_hs = (em->zoom * v_hs + 50) / 100;
write_ucregister(DICOM_FrameTop, f_vo);
write_ucregister(DICOM_FrameBottom, f_vo + f_vs - 1);
write_ucregister(DICOM_FrameLeft, f_ho);
write_ucregister(DICOM_FrameRight, f_ho + f_hs - 1);
write_ucregister(DICOM_VisibleTop, v_vo);
write_ucregister(DICOM_VisibleBottom, v_vo + v_vs - 1);
write_ucregister(DICOM_VisibleLeft, v_ho);
write_ucregister(DICOM_VisibleRight,v_ho + v_hs - 1);
}
if (em->aspect_ratio == EM8300_ASPECTRATIO_16_9) {
em->dicom_tvout |= 0x10;
} else {
em->dicom_tvout &= ~0x10;
}
write_ucregister(DICOM_TvOut, em->dicom_tvout);
if (em->overlay_enabled) {
write_register(0x1f47, 0x0);
write_register(0x1f5e, 0x1afe);
write_ucregister(DICOM_Control, 0x9afe);
#if 0 /* don't know if this is necessary yet */
#ifdef EM8300_DICOM_0x1f5e_0x1efe
write_register(0x1f5e, 0x1efe);
#else
write_register(0x1f5e, 0x1afe);
#endif
#ifdef EM8300_DICOM_CONTROL_0x9efe
write_ucregister(DICOM_Control, 0x9efe);
#else
write_ucregister(DICOM_Control, 0x9afe);
#endif
#endif
} else {
if (em->encoder_type == ENCODER_BT865) {
write_register(0x1f47, 0x0);
if (em->video_mode == EM8300_VIDEOMODE_NTSC) {
write_register(EM8300_HSYNC_LO, 134);
write_register(EM8300_HSYNC_HI, 720);
} else {
write_register(EM8300_HSYNC_LO, 140);
write_register(EM8300_HSYNC_HI, 720);
}
if (vmode_ntsc) {
write_register(EM8300_VSYNC_HI, 260);
write_register(0x1f5e, 0xfefe);
} else {
write_register(EM8300_VSYNC_HI, 310);
write_register(0x1f5e, 0x9cfe);
}
write_ucregister(DICOM_VSyncLo1, 0x1);
write_ucregister(DICOM_VSyncLo2, 0x0);
write_ucregister(DICOM_VSyncDelay1, 0xd2);
write_ucregister(DICOM_VSyncDelay2, 0x00);
write_register(0x1f46, 0x00);
write_register(0x1f47, 0x1f);
write_ucregister(DICOM_Control, 0x9efe);
} else { /* ADV7170 or ADV7175A */
write_register(0x1f47, 0x18);
if (vmode_ntsc) {
if (em->config.model.dicom_fix) {
write_register(0x1f5e, 0x1efe);
} else {
write_register(0x1f5e, 0x1afe);
}
if (em->config.model.dicom_control) {
write_ucregister(DICOM_Control, 0x9efe);
} else {
write_ucregister(DICOM_Control, 0x9afe);
}
} else {
if (em->config.model.dicom_fix) {
write_register(0x1f5e, 0x1afe);
} else {
write_register(0x1f5e, 0x1efe);
}
if (em->config.model.dicom_control) {
write_ucregister(DICOM_Control, 0x9afe);
} else {
write_ucregister(DICOM_Control, 0x9efe);
}
}
}
}
pr_debug("em8300-%d: vmode_ntsc: %d\n", em->card_nr, vmode_ntsc);
pr_debug("em8300-%d: dicom_other_pal: %d\n", em->card_nr, em->config.model.dicom_other_pal);
pr_debug("em8300-%d: dicom_control: %d\n", em->card_nr, em->config.model.dicom_control);
pr_debug("em8300-%d: dicom_fix: %d\n", em->card_nr, em->config.model.dicom_fix);
write_ucregister(DICOM_UpdateFlag, 1);
return em8300_waitfor(em, ucregister(DICOM_UpdateFlag), 0, 1);
}
int em8300_dicom_update(struct em8300_s *em)
{
int ret;
int vmode_ntsc = 1;
int f_vs, f_hs, f_vo, f_ho;
int v_vs, v_hs, v_vo, v_ho;
if (em->config.model.dicom_other_pal) {
vmode_ntsc = (em->video_mode == V4L2_STD_NTSC);
}
if ((ret = em8300_waitfor(em, ucregister(DICOM_UpdateFlag), 0, 1))) {
return ret;
}
v_vs = f_vs = tvmodematrix[em->video_mode].vertsize;
v_hs = f_hs = tvmodematrix[em->video_mode].horizsize;
v_vo = f_vo = tvmodematrix[em->video_mode].vertoffset;
v_ho = f_ho = tvmodematrix[em->video_mode].horizoffset;
f_vo += ((100 - em->zoom) * f_vs + 100) / 200;
f_ho += 2 * (((100 - em->zoom) * f_hs + 200) / 400);
v_vo += ((100 - em->zoom) * v_vs + 100) / 200;
v_ho += 2 * (((100 - em->zoom) * v_hs + 200) / 400);
f_vs = (em->zoom * f_vs + 50) / 100;
f_hs = (em->zoom * f_hs + 50) / 100;
v_vs = (em->zoom * v_vs + 50) / 100;
v_hs = (em->zoom * v_hs + 50) / 100;
write_ucregister(DICOM_FrameTop, f_vo);
write_ucregister(DICOM_FrameBottom, f_vo + f_vs - 1);
write_ucregister(DICOM_FrameLeft, f_ho);
write_ucregister(DICOM_FrameRight, f_ho + f_hs - 1);
write_ucregister(DICOM_VisibleTop, v_vo);
write_ucregister(DICOM_VisibleBottom, v_vo + v_vs - 1);
write_ucregister(DICOM_VisibleLeft, v_ho);
write_ucregister(DICOM_VisibleRight,v_ho + v_hs - 1);
if (em->aspect_ratio == EM8300_ASPECTRATIO_16_9) {
em->dicom_tvout |= 0x10;
} else {
em->dicom_tvout &= ~0x10;
}
write_ucregister(DICOM_TvOut, em->dicom_tvout);
if (em->encoder_type == ENCODER_BT865) {
write_register(0x1f47, 0x0);
if (em->video_mode == V4L2_STD_NTSC) {
write_register(VIDEO_HSYNC_LO, 134);
write_register(VIDEO_HSYNC_HI, 720);
} else {
write_register(VIDEO_HSYNC_LO, 140);
write_register(VIDEO_HSYNC_HI, 720);
}
if (vmode_ntsc) {
write_register(VIDEO_VSYNC_HI, 260);
write_register(0x1f5e, 0xfefe);
} else {
write_register(VIDEO_VSYNC_HI, 310);
write_register(0x1f5e, 0x9cfe);
}
write_ucregister(DICOM_VSyncLo1, 0x1);
write_ucregister(DICOM_VSyncLo2, 0x0);
write_ucregister(DICOM_VSyncDelay1, 0xd2);
write_ucregister(DICOM_VSyncDelay2, 0x00);
write_register(0x1f46, 0x00);
write_register(0x1f47, 0x1f);
write_ucregister(DICOM_Control, 0x9efe);
} else { /* ADV7170 or ADV7175A */
write_register(0x1f47, 0x18);
if (vmode_ntsc) {
if (em->config.model.dicom_fix) {
write_register(0x1f5e, 0x1efe);
} else {
write_register(0x1f5e, 0x1afe);
}
if (em->config.model.dicom_control) {
write_ucregister(DICOM_Control, 0x9efe);
} else {
write_ucregister(DICOM_Control, 0x9afe);
}
} else {
if (em->config.model.dicom_fix) {
write_register(0x1f5e, 0x1afe);
} else {
write_register(0x1f5e, 0x1efe);
}
if (em->config.model.dicom_control) {
write_ucregister(DICOM_Control, 0x9afe);
} else {
write_ucregister(DICOM_Control, 0x9efe);
}
}
}
pr_debug("em8300-%d: vmode_ntsc: %d\n", em->instance, vmode_ntsc);
pr_debug("em8300-%d: dicom_other_pal: %d\n", em->instance, em->config.model.dicom_other_pal);
pr_debug("em8300-%d: dicom_control: %d\n", em->instance, em->config.model.dicom_control);
pr_debug("em8300-%d: dicom_fix: %d\n", em->instance, em->config.model.dicom_fix);
write_ucregister(DICOM_UpdateFlag, 1);
return em8300_waitfor(em, ucregister(DICOM_UpdateFlag), 0, 1);
}
