void setup_systemclock()
{
/* enable the crystal oscillator */
CGU_SetXTALOSC(XTAL_FREQ);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
/* connect the cpu to the xtal */
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M4);
/* connect the PLL to the xtal */
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
/* configure the PLL to 120 MHz */
CGU_SetPLL1(10);
while((LPC_CGU->PLL1_STAT&1) == 0x0);
/* enable the PLL */
CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
/* connect to the CPU core */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M4);
SystemCoreClock = 120000000;
/* wait one msec */
emc_WaitUS(1000);
/* Change the clock to 204 MHz */
CGU_SetPLL1(17);
while((LPC_CGU->PLL1_STAT&1) == 0x0);
SystemCoreClock = 204000000;
CGU_ClockSourceFrequency[CGU_CLKSRC_PLL1] = SystemCoreClock;
}
void emc_WaitMS(uint32_t ms)
{
emc_WaitUS(ms * 1000);
}
void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits)
{
// adjust the CCU delaye for EMI (default to zero)
//LPC_SCU->EMCCLKDELAY = (CLK0_DELAY | (CLKE0_DELAY << 16));
// Move all clock delays together
LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY)
| (CLK0_DELAY << 4)
| (CLK0_DELAY << 8)
| (CLK0_DELAY << 12));
/* Initialize EMC to interface with SDRAM */
LPC_EMC->CONTROL = 0x00000001; /* Enable the external memory controller */
LPC_EMC->CONFIG = 0;
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14));
LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14));
LPC_EMC->DYNAMICRASCAS0 = (3 << 0) | (3 << 8); // aem
LPC_EMC->DYNAMICRASCAS2 = (3 << 0) | (3 << 8); // aem
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY;
// LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet
// LPC_EMC->DYNAMICRAS = 3;
// LPC_EMC->DYNAMICSREX = 5;
// LPC_EMC->DYNAMICAPR = 0;
// LPC_EMC->DYNAMICDAL = 4;
// LPC_EMC->DYNAMICWR = 1;
// LPC_EMC->DYNAMICRC = 5;
// LPC_EMC->DYNAMICRFC = 5;
// LPC_EMC->DYNAMICXSR = 5;
// LPC_EMC->DYNAMICRRD = 1;
// LPC_EMC->DYNAMICMRD = 1;
LPC_EMC->DYNAMICRP = 2; // calculated from xls sheet for 120 MHz
LPC_EMC->DYNAMICRAS = 5;
LPC_EMC->DYNAMICSREX = 8;
LPC_EMC->DYNAMICAPR = 1;
LPC_EMC->DYNAMICDAL = 5;
LPC_EMC->DYNAMICWR = 1;
LPC_EMC->DYNAMICRC = 8;
LPC_EMC->DYNAMICRFC = 8;
LPC_EMC->DYNAMICXSR = 8;
LPC_EMC->DYNAMICRRD = 1;
LPC_EMC->DYNAMICMRD = 1;
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
emc_WaitUS(100);
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
LPC_EMC->DYNAMICREFRESH = 2;
emc_WaitUS(100);
// LPC_EMC->DYNAMICREFRESH = 50;
LPC_EMC->DYNAMICREFRESH = 118;
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
// if(u32DataBus == 0)
// {
// /* burst size 8 */
// *((volatile uint32_t *)(u32BaseAddr | ((3 | (3 << 4)) << (u32ColAddrBits + 1))));
// }
// else
// {
// /* burst size 4 */
// *((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2))));
// }
if(u32DataBus == 0) // burst size 8, CAS3
{
*((volatile uint32_t *)(u32BaseAddr | ((3UL | (3UL << 4)) << (u32ColAddrBits + 2 + 1))));
}
else // burst size 4, CAS3
{
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (3UL << 4)) << (u32ColAddrBits + 2 + 2))));
}
LPC_EMC->DYNAMICCONTROL = 0; // EMC_CE_ENABLE | EMC_CS_ENABLE;
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14)) | EMC_B_ENABLE;
LPC_EMC->DYNAMICCONFIG1 = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14)) | EMC_B_ENABLE;
LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14)) | EMC_B_ENABLE;
LPC_EMC->DYNAMICCONFIG3 = ((u32Width << 7) | (u32Size << 9)/* | (1UL << 12)*/ | (u32DataBus << 14)) | EMC_B_ENABLE;
}
